From ca7a51d116811084fc4c5689e9fde705b286e0cb Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Mon, 27 Oct 2014 13:29:39 +0000
Subject: [PATCH] Added Arria10 DDIO IP from ip_arria10_ddio library to
tech_iobuf.
---
libraries/technology/iobuf/hdllib.cfg | 2 +-
.../iobuf/tech_iobuf_component_pkg.vhd | 33 +++++++++++++++++++
.../technology/iobuf/tech_iobuf_ddio_in.vhd | 7 ++++
.../technology/iobuf/tech_iobuf_ddio_out.vhd | 9 ++++-
4 files changed, 49 insertions(+), 2 deletions(-)
diff --git a/libraries/technology/iobuf/hdllib.cfg b/libraries/technology/iobuf/hdllib.cfg
index 3c4b7d2ebf..d99955fbe7 100644
--- a/libraries/technology/iobuf/hdllib.cfg
+++ b/libraries/technology/iobuf/hdllib.cfg
@@ -1,6 +1,6 @@
hdl_lib_name = tech_iobuf
hdl_library_clause_name = tech_iobuf_lib
-hdl_lib_uses = technology ip_stratixiv
+hdl_lib_uses = technology ip_stratixiv ip_arria10_ddio
hdl_lib_technology =
build_dir_sim = $HDL_BUILD_DIR
diff --git a/libraries/technology/iobuf/tech_iobuf_component_pkg.vhd b/libraries/technology/iobuf/tech_iobuf_component_pkg.vhd
index 936c729d91..dce04fc43e 100644
--- a/libraries/technology/iobuf/tech_iobuf_component_pkg.vhd
+++ b/libraries/technology/iobuf/tech_iobuf_component_pkg.vhd
@@ -60,4 +60,37 @@ PACKAGE tech_iobuf_component_pkg IS
);
END COMPONENT;
+
+ -----------------------------------------------------------------------------
+ -- ip_arria10
+ -----------------------------------------------------------------------------
+
+ COMPONENT ip_arria10_ddio_in IS
+ GENERIC (
+ g_width : NATURAL := 1
+ );
+ PORT (
+ in_dat : IN STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+ in_clk : IN STD_LOGIC;
+ in_clk_en : IN STD_LOGIC := '1'; -- Not Connected
+ rst : IN STD_LOGIC := '0';
+ out_dat_hi : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+ out_dat_lo : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_ddio_out IS
+ GENERIC(
+ g_width : NATURAL := 1
+ );
+ PORT (
+ rst : IN STD_LOGIC := '0';
+ in_clk : IN STD_LOGIC;
+ in_clk_en : IN STD_LOGIC := '1'; -- Not Connected
+ in_dat_hi : IN STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+ in_dat_lo : IN STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+ out_dat : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
END tech_iobuf_component_pkg;
diff --git a/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd b/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd
index 70272e2092..114cb7f597 100644
--- a/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd
+++ b/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd
@@ -27,6 +27,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_lib;
+LIBRARY ip_arria10_ddio_lib;
ENTITY tech_iobuf_ddio_in IS
GENERIC (
@@ -54,4 +55,10 @@ BEGIN
PORT MAP (in_dat, in_clk, in_clk_en, rst, out_dat_hi, out_dat_lo);
END GENERATE;
+ gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ u0 : ip_arria10_ddio_in
+ GENERIC MAP (g_width)
+ PORT MAP (in_dat, in_clk, in_clk_en, rst, out_dat_hi, out_dat_lo);
+ END GENERATE;
+
END ARCHITECTURE;
\ No newline at end of file
diff --git a/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd b/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd
index 2832c82db2..36a747ba58 100644
--- a/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd
+++ b/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd
@@ -27,6 +27,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_lib;
+LIBRARY ip_arria10_ddio_lib;
ENTITY tech_iobuf_ddio_out IS
GENERIC (
@@ -53,5 +54,11 @@ BEGIN
GENERIC MAP ("Stratix IV", g_width)
PORT MAP (rst, in_clk, in_clk_en, in_dat_hi, in_dat_lo, out_dat);
END GENERATE;
-
+
+ gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ u0 : ip_arria10_ddio_out
+ GENERIC MAP (g_width)
+ PORT MAP (rst, in_clk, in_clk_en, in_dat_hi, in_dat_lo, out_dat);
+ END GENERATE;
+
END ARCHITECTURE;
\ No newline at end of file
--
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