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Commit c8dd5e16 authored by Reinier van der Walle's avatar Reinier van der Walle
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Merge branch 'L2SDP-541' into 'master' 

added missing scynchronization

Closes L2SDP-541

See merge request desp/hdl!178
parents ca3e313c 839ea367
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1 merge request!178added missing scynchronization
Pipeline #22382 passed
Stage: simulation
Stage: synthesis
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libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
+ 26
− 18
View file @ c8dd5e16
......@@ -102,6 +102,7 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
SIGNAL rx_csr_lane_powerdown_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL xcvr_rst_ctrl_rx_ready_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL rx_xcvr_ready_in_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL mm_rx_xcvr_ready_in_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL pll_reset_async_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL pll_reset_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL xcvr_rst_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS => '1');
......@@ -115,7 +116,7 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
SIGNAL rxframe_rst_n_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL f2_div1_cnt_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL core_pll_locked : STD_LOGIC;
SIGNAL core_pll_locked_reg : STD_LOGIC;
SIGNAL mm_core_pll_locked_reg : STD_LOGIC;
SIGNAL jesd204b_sysref_1 : STD_LOGIC;
SIGNAL jesd204b_sysref_2 : STD_LOGIC;
SIGNAL jesd204b_sysref_frameclk_1 : STD_LOGIC;
......@@ -325,16 +326,17 @@ BEGIN
irq => open,
clk => mm_clk, -- use clk = mm_clk for av_* port
csr_reset => mm_rst,
reset1_dsrt_qual => core_pll_locked_reg, -- core pll_locked synchronised to clk = mm_clk domain
reset1_dsrt_qual => mm_core_pll_locked_reg, -- core pll_locked synchronised to clk = mm_clk domain
reset2_dsrt_qual => '1', -- Tied to '1' in example design. Tx xcvr is not used.
reset5_dsrt_qual => rx_xcvr_ready_in_arr(i),
reset5_dsrt_qual => mm_rx_xcvr_ready_in_arr(i),
reset_in0 => mm_rst,
-- reset_out* signals are in mm_clk domain
reset_out0 => pll_reset_async_arr(i), -- Use channel 0 to reset the core pll
reset_out1 => xcvr_rst_arr(i), -- Use channel 1 to reset the transceiver reset controller
reset_out2 => open,
reset_out3 => open,
reset_out4 => open,
reset_out5 => rx_avs_rst_arr(i), -- in mm_clk domain
reset_out5 => rx_avs_rst_arr(i),
reset_out6 => rxlink_rst_async_arr(i),
reset_out7 => rxframe_rst_async_arr(i)
);
......@@ -347,8 +349,6 @@ BEGIN
out_rst => pll_reset_arr(i)
);
-- No need to synchronize xcvr_rst as it is synchronized in ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12
-- synchronize rxlink reset
u_common_areset_rxlink : ENTITY common_lib.common_areset
PORT MAP (
......@@ -367,6 +367,17 @@ BEGIN
rx_xcvr_ready_in_arr(i) <= '1' when rx_csr_lane_powerdown_arr(i)='1' OR xcvr_rst_ctrl_rx_ready_arr(i)='1' else '0';
-- synchronize rx_xcvr_ready_in_arr to mm_clk
u_common_areset_rx_xcvr_ready : ENTITY common_lib.common_areset
GENERIC MAP (
g_in_rst_level => '0', -- rst is asserted immediately in_rst = '0'
g_rst_level => '0' -- When in_rst is asserted, out_rst = '0'
)
PORT MAP (
in_rst => rx_xcvr_ready_in_arr(i),
clk => mm_clk,
out_rst => mm_rx_xcvr_ready_in_arr(i)
);
-- Invert thr active-low resets
rx_avs_rst_n_arr(i) <= not rx_avs_rst_arr(i);
......@@ -374,7 +385,6 @@ BEGIN
rxframe_rst_n_arr(i) <= not rxframe_rst_arr(i);
-----------------------------------------------------------------------------
-- Minimal deframer (transport layer)
-----------------------------------------------------------------------------
......@@ -470,7 +480,7 @@ BEGIN
PORT MAP (
in_rst => core_pll_locked,
clk => mm_clk,
out_rst => core_pll_locked_reg
out_rst => mm_core_pll_locked_reg
);
......@@ -523,8 +533,6 @@ BEGIN
miso_arr => jesd204b_miso_arr
);
END str;
libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
+ 25
− 18
View file @ c8dd5e16
......@@ -102,6 +102,7 @@ ARCHITECTURE str OF ip_arria10_e2sg_jesd204b IS
SIGNAL rx_csr_lane_powerdown_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL xcvr_rst_ctrl_rx_ready_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL rx_xcvr_ready_in_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL mm_rx_xcvr_ready_in_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL pll_reset_async_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL pll_reset_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL xcvr_rst_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS => '1');
......@@ -115,7 +116,7 @@ ARCHITECTURE str OF ip_arria10_e2sg_jesd204b IS
SIGNAL rxframe_rst_n_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL f2_div1_cnt_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL core_pll_locked : STD_LOGIC;
SIGNAL core_pll_locked_reg : STD_LOGIC;
SIGNAL mm_core_pll_locked_reg : STD_LOGIC;
SIGNAL jesd204b_sysref_1 : STD_LOGIC;
SIGNAL jesd204b_sysref_2 : STD_LOGIC;
SIGNAL jesd204b_sysref_frameclk_1 : STD_LOGIC;
......@@ -325,16 +326,17 @@ BEGIN
irq => open,
clk => mm_clk, -- use clk = mm_clk for av_* port
csr_reset => mm_rst,
reset1_dsrt_qual => core_pll_locked_reg, -- core pll_locked synchronised to clk = mm_clk domain
reset1_dsrt_qual => mm_core_pll_locked_reg, -- core pll_locked synchronised to clk = mm_clk domain
reset2_dsrt_qual => '1', -- Tied to '1' in example design. Tx xcvr is not used.
reset5_dsrt_qual => rx_xcvr_ready_in_arr(i),
reset5_dsrt_qual => mm_rx_xcvr_ready_in_arr(i),
reset_in0 => mm_rst,
-- reset_out* signals are in mm_clk domain
reset_out0 => pll_reset_async_arr(i), -- Use channel 0 to reset the core pll
reset_out1 => xcvr_rst_arr(i), -- Use channel 1 to reset the transceiver reset controller
reset_out2 => open,
reset_out3 => open,
reset_out4 => open,
reset_out5 => rx_avs_rst_arr(i), -- in mm_clk domain
reset_out5 => rx_avs_rst_arr(i),
reset_out6 => rxlink_rst_async_arr(i),
reset_out7 => rxframe_rst_async_arr(i)
);
......@@ -347,8 +349,6 @@ BEGIN
out_rst => pll_reset_arr(i)
);
-- No need to synchronize xcvr_rst as it is synchronized in ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12
-- synchronize rxlink reset
u_common_areset_rxlink : ENTITY common_lib.common_areset
PORT MAP (
......@@ -365,8 +365,18 @@ BEGIN
out_rst => rxframe_rst_arr(i)
);
rx_xcvr_ready_in_arr(i) <= '1' when rx_csr_lane_powerdown_arr(i)='1' OR xcvr_rst_ctrl_rx_ready_arr(i)='1' else '0';
-- synchronize rx_xcvr_ready_in_arr to mm_clk
u_common_areset_rx_xcvr_ready : ENTITY common_lib.common_areset
GENERIC MAP (
g_in_rst_level => '0', -- rst is asserted immediately in_rst = '0'
g_rst_level => '0' -- When in_rst is asserted, out_rst = '0'
)
PORT MAP (
in_rst => rx_xcvr_ready_in_arr(i),
clk => mm_clk,
out_rst => mm_rx_xcvr_ready_in_arr(i)
);
-- Invert thr active-low resets
rx_avs_rst_n_arr(i) <= not rx_avs_rst_arr(i);
......@@ -374,7 +384,6 @@ BEGIN
rxframe_rst_n_arr(i) <= not rxframe_rst_arr(i);
-----------------------------------------------------------------------------
-- Minimal deframer (transport layer)
-----------------------------------------------------------------------------
......@@ -470,7 +479,7 @@ BEGIN
PORT MAP (
in_rst => core_pll_locked,
clk => mm_clk,
out_rst => core_pll_locked_reg
out_rst => mm_core_pll_locked_reg
);
......@@ -523,8 +532,6 @@ BEGIN
miso_arr => jesd204b_miso_arr
);
END str;
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