L2SDP-180, ntb_mms_* now working.

libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd

@@ -20,7 +20,7 @@
 -- Author:
 -- . Pieter Donker
 -- Purpose:
--- . test bench for common_variable_delay.vhd to test enable by signal mm interface
+-- . test bench for mms_common_variable_delay.vhd to test enable by signal mm interface
 -- Description:
 -- . see common_variable_delay.vhd
 -- --------------------------------------------------------------------------
@@ -41,7 +41,7 @@ ARCHITECTURE tb OF tb_mms_common_variable_delay IS
   CONSTANT c_clk_period       : TIME    := 10 ns;
   CONSTANT c_trigger_interval : NATURAL := 40;  -- in clk's
   CONSTANT c_mm_addr_enable   : NATURAL := 0;
-  CONSTANT c_cross_clock_domain_latency : NATURAL := 20;
+  CONSTANT c_cross_clock_domain_latency : NATURAL := 40;
   
   SIGNAL tb_end : STD_LOGIC := '0';
   SIGNAL rst    : STD_LOGIC;
@@ -64,20 +64,23 @@ BEGIN
     WAIT UNTIL rst='0';
     proc_common_wait_some_cycles(clk, 10);
      
-    proc_mem_mm_bus_wr(c_mm_addr_enable, 0, clk, mm_miso, mm_mosi);
+    proc_mem_mm_bus_wr(c_mm_addr_enable, 1, clk, mm_miso, mm_mosi);
     proc_common_wait_some_cycles(clk, c_cross_clock_domain_latency);
     proc_mem_mm_bus_rd(c_mm_addr_enable, clk, mm_miso, mm_mosi);
     proc_mem_mm_bus_rd_latency(1, clk);
-    enable <= TO_UINT(mm_miso.rddata(0 DOWNTO 0));
-    ASSERT enable = 0 REPORT "enable not off" SEVERITY ERROR;
+    enable <= TO_UINT(mm_miso.rddata(1 DOWNTO 0));
+    proc_common_wait_some_cycles(clk, 1);
+    ASSERT enable = 1 REPORT "enable not on" SEVERITY ERROR;
 
-    proc_mem_mm_bus_wr(c_mm_addr_enable, 1, clk, mm_miso, mm_mosi);
+    proc_mem_mm_bus_wr(c_mm_addr_enable, 0, clk, mm_miso, mm_mosi);
     proc_common_wait_some_cycles(clk, c_cross_clock_domain_latency);
     proc_mem_mm_bus_rd(c_mm_addr_enable, clk, mm_miso, mm_mosi);
     proc_mem_mm_bus_rd_latency(1, clk);
-    enable <= TO_UINT(mm_miso.rddata(1 DOWNTO 0));
-    ASSERT enable = 1 REPORT "enable not on" SEVERITY ERROR;
+    enable <= TO_UINT(mm_miso.rddata(0 DOWNTO 0));
+    proc_common_wait_some_cycles(clk, 1);
+    ASSERT enable = 0 REPORT "enable not off" SEVERITY ERROR;
 
+    proc_common_wait_some_cycles(clk, 100);
     tb_end <= '1';
     WAIT;
   END PROCESS;