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Commit c5f82828 authored by Eric Kooistra's avatar Eric Kooistra
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Rename c_sdp_jesd204b_mm_jesd_ctrl_reg into c_sdp_mm_jesd_ctrl_reg.

parent 20254aca
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1 merge request!258Shortened sync interval and used pps_rst to make the tb simulate faster (few...
...@@ -160,7 +160,7 @@ BEGIN ...@@ -160,7 +160,7 @@ BEGIN
-- in an SDP application assumes that the block timing of the out_sosi_arr(i) only contains -- in an SDP application assumes that the block timing of the out_sosi_arr(i) only contains
-- complete blocks, so from sop to eop. -- complete blocks, so from sop to eop.
mm_rst_internal <= mm_rst OR mm_jesd_ctrl_reg(31); mm_rst_internal <= mm_rst OR mm_jesd_ctrl_reg(c_sdp_jesd_ctrl_reset_bi);
gen_jesd_disable : FOR I IN 0 TO c_sdp_S_pn-1 GENERATE gen_jesd_disable : FOR I IN 0 TO c_sdp_S_pn-1 GENERATE
jesd204b_disable_arr(i) <= mm_jesd_ctrl_reg(i); jesd204b_disable_arr(i) <= mm_jesd_ctrl_reg(i);
END GENERATE; END GENERATE;
...@@ -512,7 +512,7 @@ BEGIN ...@@ -512,7 +512,7 @@ BEGIN
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
u_mm_jesd_ctrl_reg : ENTITY common_lib.common_reg_r_w u_mm_jesd_ctrl_reg : ENTITY common_lib.common_reg_r_w
GENERIC MAP ( GENERIC MAP (
g_reg => c_sdp_jesd204b_mm_jesd_ctrl_reg, g_reg => c_sdp_mm_jesd_ctrl_reg,
g_init_reg => (OTHERS => '0') g_init_reg => (OTHERS => '0')
) )
PORT MAP ( PORT MAP (
...@@ -520,11 +520,11 @@ BEGIN ...@@ -520,11 +520,11 @@ BEGIN
clk => mm_clk, clk => mm_clk,
-- control side -- control side
wr_en => jesd_ctrl_mosi.wr, wr_en => jesd_ctrl_mosi.wr,
wr_adr => jesd_ctrl_mosi.address(c_sdp_jesd204b_mm_jesd_ctrl_reg.adr_w-1 DOWNTO 0), wr_adr => jesd_ctrl_mosi.address(c_sdp_mm_jesd_ctrl_reg.adr_w-1 DOWNTO 0),
wr_dat => jesd_ctrl_mosi.wrdata(c_sdp_jesd204b_mm_jesd_ctrl_reg.dat_w-1 DOWNTO 0), wr_dat => jesd_ctrl_mosi.wrdata(c_sdp_mm_jesd_ctrl_reg.dat_w-1 DOWNTO 0),
rd_en => jesd_ctrl_mosi.rd, rd_en => jesd_ctrl_mosi.rd,
rd_adr => jesd_ctrl_mosi.address(c_sdp_jesd204b_mm_jesd_ctrl_reg.adr_w-1 DOWNTO 0), rd_adr => jesd_ctrl_mosi.address(c_sdp_mm_jesd_ctrl_reg.adr_w-1 DOWNTO 0),
rd_dat => jesd_ctrl_miso.rddata(c_sdp_jesd204b_mm_jesd_ctrl_reg.dat_w-1 DOWNTO 0), rd_dat => jesd_ctrl_miso.rddata(c_sdp_mm_jesd_ctrl_reg.dat_w-1 DOWNTO 0),
rd_val => OPEN, rd_val => OPEN,
-- data side -- data side
out_reg => mm_jesd_ctrl_reg, out_reg => mm_jesd_ctrl_reg,
......
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