diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
index cfa0669c9591a4cf79d57b65f837ba2392b0faf3..f38182ca78c3f78bb68b963f1010f8822675c8a3 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
@@ -160,7 +160,7 @@ BEGIN
   -- in an SDP application assumes that the block timing of the out_sosi_arr(i) only contains
   -- complete blocks, so from sop to eop.
 
-  mm_rst_internal <= mm_rst OR mm_jesd_ctrl_reg(31);
+  mm_rst_internal <= mm_rst OR mm_jesd_ctrl_reg(c_sdp_jesd_ctrl_reset_bi);
   gen_jesd_disable : FOR I IN 0 TO c_sdp_S_pn-1 GENERATE
     jesd204b_disable_arr(i) <= mm_jesd_ctrl_reg(i);
   END GENERATE;
@@ -512,7 +512,7 @@ BEGIN
   -----------------------------------------------------------------------------
   u_mm_jesd_ctrl_reg : ENTITY common_lib.common_reg_r_w
   GENERIC MAP (
-    g_reg       => c_sdp_jesd204b_mm_jesd_ctrl_reg,
+    g_reg       => c_sdp_mm_jesd_ctrl_reg,
     g_init_reg  => (OTHERS => '0')
   )
   PORT MAP (
@@ -520,11 +520,11 @@ BEGIN
     clk       => mm_clk,
     -- control side
     wr_en     => jesd_ctrl_mosi.wr,
-    wr_adr    => jesd_ctrl_mosi.address(c_sdp_jesd204b_mm_jesd_ctrl_reg.adr_w-1 DOWNTO 0),
-    wr_dat    => jesd_ctrl_mosi.wrdata(c_sdp_jesd204b_mm_jesd_ctrl_reg.dat_w-1 DOWNTO 0),
+    wr_adr    => jesd_ctrl_mosi.address(c_sdp_mm_jesd_ctrl_reg.adr_w-1 DOWNTO 0),
+    wr_dat    => jesd_ctrl_mosi.wrdata(c_sdp_mm_jesd_ctrl_reg.dat_w-1 DOWNTO 0),
     rd_en     => jesd_ctrl_mosi.rd,
-    rd_adr    => jesd_ctrl_mosi.address(c_sdp_jesd204b_mm_jesd_ctrl_reg.adr_w-1 DOWNTO 0),
-    rd_dat    => jesd_ctrl_miso.rddata(c_sdp_jesd204b_mm_jesd_ctrl_reg.dat_w-1 DOWNTO 0),
+    rd_adr    => jesd_ctrl_mosi.address(c_sdp_mm_jesd_ctrl_reg.adr_w-1 DOWNTO 0),
+    rd_dat    => jesd_ctrl_miso.rddata(c_sdp_mm_jesd_ctrl_reg.dat_w-1 DOWNTO 0),
     rd_val    => OPEN,
     -- data side
     out_reg   => mm_jesd_ctrl_reg,