Use hdl_lib_include_ip to include DDR3 IP. Removed hdl_lib_excludes.

boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg

@@ -3,9 +3,7 @@ hdl_library_clause_name = unb1_test_all_lib
 hdl_lib_uses_synth = unb1_board unb1_test
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_stratixiv
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave
-                   ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
-                   ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
+hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_800_master
 
 synth_files =
     unb1_test_all.vhd

boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg

@@ -3,9 +3,7 @@ hdl_library_clause_name = unb1_test_ddr_lib
 hdl_lib_uses_synth = unb1_board unb1_test
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_stratixiv
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave
-                   ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
-                   ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
+hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_800_master
 
 synth_files =
     unb1_test_ddr.vhd

boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg

@@ -3,10 +3,7 @@ hdl_library_clause_name = unb1_test_ddr_16g_MB_I_lib
 hdl_lib_uses_synth = unb1_board unb1_test
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_stratixiv
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master
-                   ip_stratixiv_ddr3_uphy_4g_800_slave
-                   ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
-                   ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
+hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_16g_dual_rank_800
 
 
 synth_files =

boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg

@@ -3,10 +3,7 @@ hdl_library_clause_name = unb1_test_ddr_16g_MB_II_lib
 hdl_lib_uses_synth = unb1_board unb1_test
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_stratixiv
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master
-                   ip_stratixiv_ddr3_uphy_4g_800_slave
-                   ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
-                   ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
+hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_16g_dual_rank_800
 
 synth_files =
     unb1_test_ddr_16g_MB_II.vhd

boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg

@@ -3,10 +3,7 @@ hdl_library_clause_name = unb1_test_ddr_16g_MB_I_II_lib
 hdl_lib_uses_synth = unb1_board unb1_test
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_stratixiv
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
-                   ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
-                   ip_stratixiv_ddr3_uphy_4g_800_master
-                   ip_stratixiv_ddr3_uphy_4g_800_slave
+hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_16g_dual_rank_800
 
 synth_files =
     unb1_test_ddr_16g_MB_I_II.vhd

boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg

@@ -3,10 +3,7 @@ hdl_library_clause_name = unb1_test_ddr_MB_I_lib
 hdl_lib_uses_synth = unb1_board unb1_test
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_stratixiv
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_16g_dual_rank_800
-                   ip_stratixiv_ddr3_uphy_4g_800_slave
-                   ip_stratixiv_ddr3_uphy_4g_800_master
-                   ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
+hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
 
 synth_files =
     unb1_test_ddr_MB_I.vhd

boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg

@@ -3,11 +3,7 @@ hdl_library_clause_name = unb1_test_ddr_MB_II_lib
 hdl_lib_uses_synth = unb1_board unb1_test
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_stratixiv
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_16g_dual_rank_800
-                   ip_stratixiv_ddr3_uphy_4g_800_slave
-                   ip_stratixiv_ddr3_uphy_4g_800_master
-                   ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
-
+hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
 
 synth_files =
     unb1_test_ddr_MB_II.vhd

boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg

@@ -3,10 +3,7 @@ hdl_library_clause_name = unb1_test_ddr_MB_I_II_lib
 hdl_lib_uses_synth = unb1_board unb1_test
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_stratixiv
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_16g_dual_rank_800
-                   ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
-                   ip_stratixiv_ddr3_uphy_4g_800_master
-                   ip_stratixiv_ddr3_uphy_4g_800_slave
+hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
 
 synth_files =
     unb1_test_ddr_MB_I_II.vhd