Merge branch 'master' into L2SDP-215

libraries/dsp/fringe_stop/tb/vhdl/tb_mmf_fringe_stop_unit.vhd

@@ -255,23 +255,29 @@ BEGIN
       mmf_mm_bus_rd(c_mm_file_ram_fringe_stop_step, 0, rd_data, mm_clk);
       ASSERT TO_UINT(rd_data)=c_in_step2 REPORT "Wrong first written step readback value, unexpected page swap" SEVERITY ERROR;
 
+      REPORT "MM done " & INTEGER'IMAGE(g_tb_index) SEVERITY NOTE;
+
       -------------------------------------------------------------------------
       -- Test FS step for one phasor period
       -------------------------------------------------------------------------
       -- Wait for at least one fringe stop phase period
       v_data := out_re;
       proc_common_wait_until_value(v_data+1, dp_clk, out_re);  -- wait until out_re+1, initial (out_re, out_im) = (-c_in_amplitude, 0)
+      REPORT "Phasor start " & INTEGER'IMAGE(g_tb_index) SEVERITY NOTE;
       tb_state <= "Phasor start  ";
       proc_common_wait_until_evt(dp_clk, out_re);              -- wait until out_re+1 changes
       proc_common_wait_until_value(v_data, dp_clk, out_re);    -- wait until out_re again
       proc_common_wait_until_value(v_data+1, dp_clk, out_re);  -- wait until out_re+1 again
+      REPORT "Phasor end " & INTEGER'IMAGE(g_tb_index) SEVERITY NOTE;
       tb_state <= "Phasor end    ";
 
       -- Wait some more sync intervals
       proc_common_wait_some_cycles(dp_clk, c_in_sync_interval*3);
 
+      REPORT "tb_almost_end " & INTEGER'IMAGE(g_tb_index) SEVERITY NOTE;
       tb_almost_end <= '1';
       proc_common_wait_some_cycles(dp_clk, 10);
+      REPORT "tb_end " & INTEGER'IMAGE(g_tb_index) SEVERITY NOTE;
       tb_end <= '1';
     END IF;
     WAIT;