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Commit d41002ff authored by Eric Kooistra's avatar Eric Kooistra
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Added notes to track tb flow in regression test log report.

parent f37ee0a2
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......@@ -255,23 +255,29 @@ BEGIN
mmf_mm_bus_rd(c_mm_file_ram_fringe_stop_step, 0, rd_data, mm_clk);
ASSERT TO_UINT(rd_data)=c_in_step2 REPORT "Wrong first written step readback value, unexpected page swap" SEVERITY ERROR;
REPORT "MM done " & INTEGER'IMAGE(g_tb_index) SEVERITY NOTE;
-------------------------------------------------------------------------
-- Test FS step for one phasor period
-------------------------------------------------------------------------
-- Wait for at least one fringe stop phase period
v_data := out_re;
proc_common_wait_until_value(v_data+1, dp_clk, out_re); -- wait until out_re+1, initial (out_re, out_im) = (-c_in_amplitude, 0)
REPORT "Phasor start " & INTEGER'IMAGE(g_tb_index) SEVERITY NOTE;
tb_state <= "Phasor start ";
proc_common_wait_until_evt(dp_clk, out_re); -- wait until out_re+1 changes
proc_common_wait_until_value(v_data, dp_clk, out_re); -- wait until out_re again
proc_common_wait_until_value(v_data+1, dp_clk, out_re); -- wait until out_re+1 again
REPORT "Phasor end " & INTEGER'IMAGE(g_tb_index) SEVERITY NOTE;
tb_state <= "Phasor end ";
-- Wait some more sync intervals
proc_common_wait_some_cycles(dp_clk, c_in_sync_interval*3);
REPORT "tb_almost_end " & INTEGER'IMAGE(g_tb_index) SEVERITY NOTE;
tb_almost_end <= '1';
proc_common_wait_some_cycles(dp_clk, 10);
REPORT "tb_end " & INTEGER'IMAGE(g_tb_index) SEVERITY NOTE;
tb_end <= '1';
END IF;
WAIT;
......
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