Added c_sim_level.

libraries/technology/10gbase_r/tb_tech_10gbase_r.vhd

@@ -56,7 +56,8 @@ END tb_tech_10gbase_r;
 ARCHITECTURE tb OF tb_tech_10gbase_r IS
 
   CONSTANT c_sim               : BOOLEAN:= TRUE;
-  CONSTANT phy_loopback_delay  : TIME :=  1 ns;
+  CONSTANT c_sim_level         : NATURAL := 0;     -- 0 = use IP; 1 = use fast serdes model (not useful here, because no proper xgmii_tx_dc_arr stimuli)
+  CONSTANT phy_loopback_delay  : TIME :=  sel_a_b(c_sim_level=0, 1 ns, 0 ns);
   CONSTANT c_nof_channels      : NATURAL := 2;
   
   SIGNAL tb_end             : STD_LOGIC := '0';
@@ -67,7 +68,7 @@ ARCHITECTURE tb OF tb_tech_10gbase_r IS
   -- XGMII interface
   SIGNAL xgmii_tx_ready_arr : STD_LOGIC_VECTOR(c_nof_channels-1 DOWNTO 0);
   SIGNAL xgmii_rx_ready_arr : STD_LOGIC_VECTOR(c_nof_channels-1 DOWNTO 0);
-  SIGNAL xgmii_tx_dc_arr    : t_xgmii_dc_arr(c_nof_channels-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'X'));  -- '0', '1'
+  SIGNAL xgmii_tx_dc_arr    : t_xgmii_dc_arr(c_nof_channels-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));  -- '0', '1'
   SIGNAL xgmii_rx_dc_arr    : t_xgmii_dc_arr(c_nof_channels-1 DOWNTO 0);
 
   -- PHY serial interface
@@ -110,6 +111,7 @@ BEGIN
   GENERIC MAP (
     g_technology       => g_technology,
     g_sim              => c_sim,
+    g_sim_level        => c_sim_level,
     g_nof_channels     => c_nof_channels
   )
   PORT MAP (