added clear register

libraries/base/dp/src/vhdl/dp_block_validate_bsn_at_sync.vhd

@@ -56,6 +56,7 @@
 --  =====================================================================
 --  0                   [31..0] RO  nof_sync_discarded      0x0    
 --  1                   [31..0] RO  nof_sync                0x0   
+--  2                   [31..0] RW  clear                   0x0 read or write to clear counters  
 --  =====================================================================
 -------------------------------------------------------------------------------
 LIBRARY IEEE, common_lib;
@@ -89,8 +90,8 @@ END dp_block_validate_bsn_at_sync;
 
 ARCHITECTURE rtl OF dp_block_validate_bsn_at_sync IS
 
-  CONSTANT c_nof_regs   : NATURAL := 2;
-
+  CONSTANT c_nof_regs   : NATURAL := 3;
+  CONSTANT c_clear_adr  : NATURAL := c_nof_regs-1;
   -- Define the actual size of the MM slave register
   CONSTANT c_mm_reg : t_c_mem := (latency  => 1,
                                   adr_w    => ceil_log2(c_nof_regs),
@@ -101,8 +102,8 @@ ARCHITECTURE rtl OF dp_block_validate_bsn_at_sync IS
   -- Registers in st_clk domain
   SIGNAL count_reg        : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0) := (OTHERS=>'0');
 
-  SIGNAL mm_cnt_clr       : STD_LOGIC_VECTOR(c_nof_regs-1 DOWNTO 0); 
-  SIGNAL cnt_clr          : STD_LOGIC_VECTOR(c_nof_regs-1 DOWNTO 0); 
+  SIGNAL mm_cnt_clr       : STD_LOGIC; 
+  SIGNAL cnt_clr          : STD_LOGIC; 
   SIGNAL cnt_sync         : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
   SIGNAL cnt_sync_en      : STD_LOGIC;
   SIGNAL cnt_discarded    : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
@@ -118,18 +119,16 @@ ARCHITECTURE rtl OF dp_block_validate_bsn_at_sync IS
   
 BEGIN
  
-  gen_cnt_clr : FOR I IN 0 TO c_nof_regs-1 GENERATE
-    mm_cnt_clr(I) <= reg_mosi.rd WHEN TO_UINT(reg_mosi.address(c_mm_reg.adr_w-1 DOWNTO 0)) = I ELSE '0' ;
+  mm_cnt_clr <= (reg_mosi.rd OR reg_mosi.wr) WHEN TO_UINT(reg_mosi.address(c_mm_reg.adr_w-1 DOWNTO 0)) = c_clear_adr ELSE '0' ;
   u_common_spulse : ENTITY common_lib.common_spulse
     PORT MAP (
       in_rst    => mm_rst,
       in_clk    => mm_clk,
-      in_pulse  => mm_cnt_clr(I),
+      in_pulse  => mm_cnt_clr,
       out_rst   => dp_rst,
       out_clk   => dp_clk,
-      out_pulse => cnt_clr(I)
+      out_pulse => cnt_clr
     );
-  END GENERATE;
 
   -- discarded counter
   cnt_discarded_en <= '1' WHEN in_sosi.sync = '1' AND bsn_ok = '0' ELSE '0';
@@ -141,7 +140,7 @@ BEGIN
     rst => dp_rst,
     clk => dp_clk,
   
-    cnt_clr => cnt_clr(0), 
+    cnt_clr => cnt_clr, 
     cnt_en  => cnt_discarded_en,
     count   => cnt_discarded
   );
@@ -155,7 +154,7 @@ BEGIN
     rst => dp_rst,
     clk => dp_clk,
 
-    cnt_clr => cnt_clr(1), 
+    cnt_clr => cnt_clr, 
     cnt_en  => in_sosi.sync,
     count   => cnt_sync
   );

libraries/base/dp/src/vhdl/dp_block_validate_err.vhd

@@ -52,6 +52,7 @@
 --  g_nof_err_counts-1  [31..0] RO  err_count_index_[g_nof_err_counts-1]  0x0           
 --  g_nof_err_counts    [31..0] RO  total_discarded_blocks                0x0           
 --  g_nof_err_counts+1  [31..0] RO  total_block_count                     0x0           
+--  g_nof_err_counts+2  [31..0] RW  clear                                 0x0 read or write to clear counters
 --  ====================================================================================
 -------------------------------------------------------------------------------
 LIBRARY IEEE, common_lib;
@@ -101,7 +102,8 @@ ARCHITECTURE rtl OF dp_block_validate_err IS
 
   CONSTANT c_max_cnt    : STD_LOGIC_VECTOR(g_cnt_w-1 DOWNTO 0) := (OTHERS => '1');
   CONSTANT c_nof_err_ok : NATURAL := ceil_div(g_max_block_size, g_min_block_size);
-  CONSTANT c_nof_regs   : NATURAL := g_nof_err_counts + 2;
+  CONSTANT c_nof_regs   : NATURAL := g_nof_err_counts + 3;
+  CONSTANT c_clear_adr  : NATURAL := c_nof_regs-1;
 
   TYPE t_cnt_err_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(g_cnt_w-1 DOWNTO 0);
 
@@ -115,8 +117,8 @@ ARCHITECTURE rtl OF dp_block_validate_err IS
   -- Registers in st_clk domain
   SIGNAL count_reg     : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0) := (OTHERS=>'0');
 
-  SIGNAL mm_cnt_clr       : STD_LOGIC_VECTOR(c_nof_regs-1 DOWNTO 0);
-  SIGNAL cnt_clr          : STD_LOGIC_VECTOR(c_nof_regs-1 DOWNTO 0);
+  SIGNAL mm_cnt_clr       : STD_LOGIC;
+  SIGNAL cnt_clr          : STD_LOGIC;
   SIGNAL cnt_blk          : STD_LOGIC_VECTOR(g_cnt_w-1 DOWNTO 0);
   SIGNAL cnt_blk_en       : STD_LOGIC;
   SIGNAL cnt_discarded    : STD_LOGIC_VECTOR(g_cnt_w-1 DOWNTO 0);
@@ -137,18 +139,16 @@ ARCHITECTURE rtl OF dp_block_validate_err IS
   
 BEGIN
  
-  gen_cnt_clr : FOR I IN 0 TO c_nof_regs-1 GENERATE
-    mm_cnt_clr(I) <= reg_mosi.rd WHEN TO_UINT(reg_mosi.address(c_mm_reg.adr_w-1 DOWNTO 0)) = I ELSE '0' ;
+  mm_cnt_clr <= (reg_mosi.rd OR reg_mosi.wr) WHEN TO_UINT(reg_mosi.address(c_mm_reg.adr_w-1 DOWNTO 0)) = c_clear_adr ELSE '0' ;
   u_common_spulse : ENTITY common_lib.common_spulse
     PORT MAP (
       in_rst    => mm_rst,
       in_clk    => mm_clk,
-      in_pulse  => mm_cnt_clr(I),
+      in_pulse  => mm_cnt_clr,
       out_rst   => dp_rst,
       out_clk   => dp_clk,
-      out_pulse => cnt_clr(I)
+      out_pulse => cnt_clr
     );
-  END GENERATE;
 
   -- block counter
   cnt_blk_en <= snk_in.eop WHEN UNSIGNED(cnt_blk) < UNSIGNED(c_max_cnt) ELSE '0';
@@ -160,7 +160,7 @@ BEGIN
     rst => dp_rst,
     clk => dp_clk,
 
-    cnt_clr => cnt_clr(g_nof_err_counts+1), 
+    cnt_clr => cnt_clr, 
     cnt_en  => cnt_blk_en,
     count   => cnt_blk
   );
@@ -176,7 +176,7 @@ BEGIN
     rst => dp_rst,
     clk => dp_clk,
 
-    cnt_clr => cnt_clr(g_nof_err_counts), 
+    cnt_clr => cnt_clr, 
     cnt_en  => cnt_discarded_en,
     count   => cnt_discarded
   );
@@ -192,7 +192,7 @@ BEGIN
       rst => dp_rst,
       clk => dp_clk,
   
-      cnt_clr => cnt_clr(I), 
+      cnt_clr => cnt_clr, 
       cnt_en  => cnt_err_en(I),
       count   => cnt_err(I)
     );