processed review comments

libraries/base/dp/src/vhdl/dp_block_validate_bsn_at_sync.vhd

@@ -102,10 +102,6 @@ ARCHITECTURE rtl OF dp_block_validate_bsn_at_sync IS
   SIGNAL count_reg        : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0) := (OTHERS=>'0');
 
   SIGNAL mm_cnt_clr       : STD_LOGIC_VECTOR(c_nof_regs-1 DOWNTO 0); 
-  SIGNAL mm_cnt_clr_reg   : STD_LOGIC_VECTOR(c_nof_regs-1 DOWNTO 0); 
-  SIGNAL mm_cnt_clr_done  : STD_LOGIC;
-  SIGNAL cnt_clr_en       : STD_LOGIC;
-  SIGNAL cnt_clr_dat      : STD_LOGIC_VECTOR(c_nof_regs-1 DOWNTO 0); 
   SIGNAL cnt_clr          : STD_LOGIC_VECTOR(c_nof_regs-1 DOWNTO 0); 
   SIGNAL cnt_sync         : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
   SIGNAL cnt_sync_en      : STD_LOGIC;
@@ -122,25 +118,18 @@ ARCHITECTURE rtl OF dp_block_validate_bsn_at_sync IS
   
 BEGIN
  
-  mm_cnt_clr_reg <= (OTHERS => '0') WHEN mm_rst = '1' ELSE mm_cnt_clr WHEN rising_edge(mm_clk) ELSE mm_cnt_clr_reg;
-  gen_err_cnt_clr : FOR I IN 0 TO c_nof_regs-1 GENERATE
-    mm_cnt_clr(I) <= '1' WHEN reg_mosi.rd = '1' AND TO_UINT(reg_mosi.address(c_mm_reg.adr_w-1 DOWNTO 0)) = I ELSE 
-                     '0' WHEN mm_cnt_clr_done = '1' ELSE mm_cnt_clr_reg(I);
-  END GENERATE;
-
-  u_common_reg_cross_cnt_clr : ENTITY common_lib.common_reg_cross_domain
+  gen_cnt_clr : FOR I IN 0 TO c_nof_regs-1 GENERATE
+    mm_cnt_clr(I) <= reg_mosi.rd WHEN TO_UINT(reg_mosi.address(c_mm_reg.adr_w-1 DOWNTO 0)) = I ELSE '0' ;
+    u_common_spulse : ENTITY common_lib.common_spulse
     PORT MAP (
       in_rst    => mm_rst,
       in_clk    => mm_clk,
-    in_new    => reg_mosi.rd,
-    in_dat    => mm_cnt_clr,
-    in_done   => mm_cnt_clr_done,
+      in_pulse  => mm_cnt_clr(I),
       out_rst   => dp_rst,
       out_clk   => dp_clk,
-    out_dat   => cnt_clr_dat,
-    out_new   => cnt_clr_en
+      out_pulse => cnt_clr(I)
     );
-  cnt_clr <= cnt_clr_dat WHEN cnt_clr_en = '1' ELSE (OTHERS => '0');
+  END GENERATE;
 
   -- discarded counter
   cnt_discarded_en <= '1' WHEN in_sosi.sync = '1' AND bsn_ok = '0' ELSE '0';

libraries/base/dp/src/vhdl/dp_block_validate_err.vhd

@@ -116,10 +116,6 @@ ARCHITECTURE rtl OF dp_block_validate_err IS
   SIGNAL count_reg     : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0) := (OTHERS=>'0');
 
   SIGNAL mm_cnt_clr       : STD_LOGIC_VECTOR(c_nof_regs-1 DOWNTO 0);
-  SIGNAL mm_cnt_clr_reg   : STD_LOGIC_VECTOR(c_nof_regs-1 DOWNTO 0) := (OTHERS => '0');
-  SIGNAL mm_cnt_clr_done  : STD_LOGIC;
-  SIGNAL cnt_clr_en       : STD_LOGIC;
-  SIGNAL cnt_clr_dat      : STD_LOGIC_VECTOR(c_nof_regs-1 DOWNTO 0); 
   SIGNAL cnt_clr          : STD_LOGIC_VECTOR(c_nof_regs-1 DOWNTO 0);
   SIGNAL cnt_blk          : STD_LOGIC_VECTOR(g_cnt_w-1 DOWNTO 0);
   SIGNAL cnt_blk_en       : STD_LOGIC;
@@ -141,25 +137,18 @@ ARCHITECTURE rtl OF dp_block_validate_err IS
   
 BEGIN
  
-  mm_cnt_clr_reg <= (OTHERS => '0') WHEN mm_rst = '1' ELSE mm_cnt_clr WHEN rising_edge(mm_clk) ELSE mm_cnt_clr_reg;
-  gen_err_cnt_clr : FOR I IN 0 TO c_nof_regs-1 GENERATE
-    mm_cnt_clr(I) <= '1' WHEN reg_mosi.rd = '1' AND TO_UINT(reg_mosi.address(c_mm_reg.adr_w-1 DOWNTO 0)) = I ELSE 
-                     '0' WHEN mm_cnt_clr_done = '1' ELSE mm_cnt_clr_reg(I);
-  END GENERATE;
-
-  u_common_reg_cross_cnt_clr : ENTITY common_lib.common_reg_cross_domain
+  gen_cnt_clr : FOR I IN 0 TO c_nof_regs-1 GENERATE
+    mm_cnt_clr(I) <= reg_mosi.rd WHEN TO_UINT(reg_mosi.address(c_mm_reg.adr_w-1 DOWNTO 0)) = I ELSE '0' ;
+    u_common_spulse : ENTITY common_lib.common_spulse
     PORT MAP (
       in_rst    => mm_rst,
       in_clk    => mm_clk,
-    in_new    => reg_mosi.rd,
-    in_dat    => mm_cnt_clr,
-    in_done   => mm_cnt_clr_done,
+      in_pulse  => mm_cnt_clr(I),
       out_rst   => dp_rst,
       out_clk   => dp_clk,
-    out_dat   => cnt_clr_dat,
-    out_new   => cnt_clr_en
+      out_pulse => cnt_clr(I)
     );
-  cnt_clr <= cnt_clr_dat WHEN cnt_clr_en = '1' ELSE (OTHERS => '0');
+  END GENERATE;
 
   -- block counter
   cnt_blk_en <= snk_in.eop WHEN UNSIGNED(cnt_blk) < UNSIGNED(c_max_cnt) ELSE '0';