Renamed trc_rst into tr_rst.

libraries/io/tr_xaui/tb/vhdl/sim_xaui.vhd

@@ -32,7 +32,7 @@ ENTITY sim_xaui IS
   PORT (   
     -- Transceiver PLL reference clock   
     tr_clk                  : IN  STD_LOGIC;
-    trc_rst                 : IN  STD_LOGIC;
+    tr_rst                  : IN  STD_LOGIC;
 
     -- Calibration & reconfig clock
     cal_rec_clk             : IN  STD_LOGIC;
@@ -122,7 +122,7 @@ BEGIN
       PORT MAP (
           
         tr_clk             => tr_clk,  
-        tr_rst             => trc_rst,
+        tr_rst             => tr_rst,
          
         tx_in_data         => xgmii_tx_d(i)(j*c_xaui_serdes_data_w+c_xaui_serdes_data_w-1 DOWNTO j*c_xaui_serdes_data_w),
         tx_in_ctrl         => xgmii_tx_c(i)(j*c_xaui_serdes_ctrl_w+c_xaui_serdes_ctrl_w-1 DOWNTO j*c_xaui_serdes_ctrl_w),
@@ -138,7 +138,7 @@ BEGIN
       PORT MAP (
           
         tr_clk             => tr_clk,  
-        tr_rst             => trc_rst,
+        tr_rst             => tr_rst,
          
         rx_out_data        => xgmii_rx_d(i)(j*c_xaui_serdes_data_w+c_xaui_serdes_data_w-1 DOWNTO j*c_xaui_serdes_data_w),
         rx_out_ctrl        => xgmii_rx_c(i)(j*c_xaui_serdes_ctrl_w+c_xaui_serdes_ctrl_w-1 DOWNTO j*c_xaui_serdes_ctrl_w),