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Commit 274dfc7c authored by Eric Kooistra's avatar Eric Kooistra
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Use '_arr' and renamed trc_rst into tr_rst.

parent 6d1c17a8
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libraries/technology/xaui/tech_xaui.vhd
+ 13
− 14
View file @ 274dfc7c
......@@ -36,7 +36,6 @@ ENTITY tech_xaui IS
PORT (
-- Transceiver PLL reference clock
tr_clk : IN STD_LOGIC;
trc_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
mm_rst : IN STD_LOGIC;
......@@ -44,21 +43,21 @@ ENTITY tech_xaui IS
-- Calibration & reconfig clock
cal_rec_clk : IN STD_LOGIC;
tx_clk : IN STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
rx_clk : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
tx_clk_arr : IN STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
rx_clk_arr : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
crc_rx_ready : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0); --crc = synchronous to Cal_Rec_Clk
crc_tx_ready : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
crc_rx_ready_arr : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0); --crc = synchronous to Cal_Rec_Clk
crc_tx_ready_arr : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
a_rx_channelaligned : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
a_rx_channelaligned_arr : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
-- XGMII interface
xgmii_tx_dc : IN t_xgmii_dc_arr(g_nof_xaui-1 DOWNTO 0);
xgmii_rx_dc : OUT t_xgmii_dc_arr(g_nof_xaui-1 DOWNTO 0);
xgmii_tx_dc_arr : IN t_xgmii_dc_arr(g_nof_xaui-1 DOWNTO 0);
xgmii_rx_dc_arr : OUT t_xgmii_dc_arr(g_nof_xaui-1 DOWNTO 0);
-- Serial I/O
xaui_rx : IN t_xaui_arr(g_nof_xaui-1 DOWNTO 0);
xaui_tx : OUT t_xaui_arr(g_nof_xaui-1 DOWNTO 0);
xaui_rx_arr : IN t_xaui_arr(g_nof_xaui-1 DOWNTO 0);
xaui_tx_arr : OUT t_xaui_arr(g_nof_xaui-1 DOWNTO 0);
xaui_mosi : IN t_mem_mosi := c_mem_mosi_rst;
xaui_miso : OUT t_mem_miso
......@@ -73,10 +72,10 @@ BEGIN
gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
u0 : ENTITY work.tech_xaui_stratixiv
GENERIC MAP (g_nof_xaui)
PORT MAP (tr_clk, trc_rst, mm_clk, mm_rst, cal_rec_clk, tx_clk, rx_clk,
crc_rx_ready, crc_tx_ready, a_rx_channelaligned,
xgmii_tx_dc, xgmii_rx_dc,
xaui_rx, xaui_tx,
PORT MAP (tr_clk, mm_clk, mm_rst, cal_rec_clk, tx_clk_arr, rx_clk_arr,
crc_rx_ready_arr, crc_tx_ready_arr, a_rx_channelaligned_arr,
xgmii_tx_dc_arr, xgmii_rx_dc_arr,
xaui_rx_arr, xaui_tx_arr,
xaui_mosi, xaui_miso);
END GENERATE;
......
libraries/technology/xaui/tech_xaui_stratixiv.vhd
+ 45
− 46
View file @ 274dfc7c
......@@ -38,7 +38,6 @@ ENTITY tech_xaui_stratixiv IS
PORT (
-- Transceiver PLL reference clock
tr_clk : IN STD_LOGIC;
trc_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
mm_rst : IN STD_LOGIC;
......@@ -46,19 +45,19 @@ ENTITY tech_xaui_stratixiv IS
-- Calibration & reconfig clock
cal_rec_clk : IN STD_LOGIC;
tx_clk : IN STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
rx_clk : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
tx_clk_arr : IN STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
rx_clk_arr : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
crc_rx_ready : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0); --crc = synchronous to Cal_Rec_Clk
crc_tx_ready : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
crc_rx_ready_arr : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0); --crc = synchronous to Cal_Rec_Clk
crc_tx_ready_arr : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
a_rx_channelaligned : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
a_rx_channelaligned_arr : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
xgmii_tx_dc : IN t_xgmii_dc_arr(g_nof_xaui-1 DOWNTO 0);
xgmii_rx_dc : OUT t_xgmii_dc_arr(g_nof_xaui-1 DOWNTO 0);
xgmii_tx_dc_arr : IN t_xgmii_dc_arr(g_nof_xaui-1 DOWNTO 0);
xgmii_rx_dc_arr : OUT t_xgmii_dc_arr(g_nof_xaui-1 DOWNTO 0);
xaui_rx : IN t_xaui_arr(g_nof_xaui-1 DOWNTO 0);
xaui_tx : OUT t_xaui_arr(g_nof_xaui-1 DOWNTO 0);
xaui_rx_arr : IN t_xaui_arr(g_nof_xaui-1 DOWNTO 0);
xaui_tx_arr : OUT t_xaui_arr(g_nof_xaui-1 DOWNTO 0);
xaui_mosi : IN t_mem_mosi := c_mem_mosi_rst;
xaui_miso : OUT t_mem_miso
......@@ -100,14 +99,14 @@ BEGIN
u_ip_phy_xaui : ip_stratixiv_phy_xaui_0
PORT MAP (
pll_ref_clk => tr_clk,
xgmii_tx_clk => tx_clk(i),
xgmii_rx_clk => rx_clk(i),
xgmii_rx_dc => xgmii_rx_dc(i),
xgmii_tx_dc => xgmii_tx_dc(i),
xaui_rx_serial_data => xaui_rx(i),
xaui_tx_serial_data => xaui_tx(i),
rx_ready => crc_rx_ready(i),
tx_ready => crc_tx_ready(i),
xgmii_tx_clk => tx_clk_arr(i),
xgmii_rx_clk => rx_clk_arr(i),
xgmii_rx_dc => xgmii_rx_dc_arr(i),
xgmii_tx_dc => xgmii_tx_dc_arr(i),
xaui_rx_serial_data => xaui_rx_arr(i),
xaui_tx_serial_data => xaui_tx_arr(i),
rx_ready => crc_rx_ready_arr(i),
tx_ready => crc_tx_ready_arr(i),
phy_mgmt_clk => mm_clk,
phy_mgmt_clk_reset => mm_rst,
phy_mgmt_address => xaui_mosi_arr(i).address(c_xaui_mosi_addr_w-1 DOWNTO 0),
......@@ -117,7 +116,7 @@ BEGIN
phy_mgmt_writedata => xaui_mosi_arr(i).wrdata(c_word_w-1 DOWNTO 0),
phy_mgmt_waitrequest => xaui_miso_arr(i).waitrequest,
rx_channelaligned => a_rx_channelaligned(i),
rx_channelaligned => a_rx_channelaligned_arr(i),
-- Reconfig block connections
reconfig_to_xcvr => reconfig_0_togxb,
......@@ -140,14 +139,14 @@ BEGIN
u_ip_phy_xaui : ip_stratixiv_phy_xaui_1
PORT MAP (
pll_ref_clk => tr_clk,
xgmii_tx_clk => tx_clk(i),
xgmii_rx_clk => rx_clk(i),
xgmii_rx_dc => xgmii_rx_dc(i),
xgmii_tx_dc => xgmii_tx_dc(i),
xaui_rx_serial_data => xaui_rx(i),
xaui_tx_serial_data => xaui_tx(i),
rx_ready => crc_rx_ready(i),
tx_ready => crc_tx_ready(i),
xgmii_tx_clk => tx_clk_arr(i),
xgmii_rx_clk => rx_clk_arr(i),
xgmii_rx_dc => xgmii_rx_dc_arr(i),
xgmii_tx_dc => xgmii_tx_dc_arr(i),
xaui_rx_serial_data => xaui_rx_arr(i),
xaui_tx_serial_data => xaui_tx_arr(i),
rx_ready => crc_rx_ready_arr(i),
tx_ready => crc_tx_ready_arr(i),
phy_mgmt_clk => mm_clk,
phy_mgmt_clk_reset => mm_rst,
phy_mgmt_address => xaui_mosi_arr(i).address(c_xaui_mosi_addr_w-1 DOWNTO 0),
......@@ -157,7 +156,7 @@ BEGIN
phy_mgmt_writedata => xaui_mosi_arr(i).wrdata(c_word_w-1 DOWNTO 0),
phy_mgmt_waitrequest => xaui_miso_arr(i).waitrequest,
rx_channelaligned => a_rx_channelaligned(i),
rx_channelaligned => a_rx_channelaligned_arr(i),
-- Reconfig block connections
reconfig_to_xcvr => reconfig_1_togxb,
......@@ -180,14 +179,14 @@ BEGIN
u_ip_phy_xaui : ip_stratixiv_phy_xaui_2
PORT MAP (
pll_ref_clk => tr_clk,
xgmii_tx_clk => tx_clk(i),
xgmii_rx_clk => rx_clk(i),
xgmii_rx_dc => xgmii_rx_dc(i),
xgmii_tx_dc => xgmii_tx_dc(i),
xaui_rx_serial_data => xaui_rx(i),
xaui_tx_serial_data => xaui_tx(i),
rx_ready => crc_rx_ready(i),
tx_ready => crc_tx_ready(i),
xgmii_tx_clk => tx_clk_arr(i),
xgmii_rx_clk => rx_clk_arr(i),
xgmii_rx_dc => xgmii_rx_dc_arr(i),
xgmii_tx_dc => xgmii_tx_dc_arr(i),
xaui_rx_serial_data => xaui_rx_arr(i),
xaui_tx_serial_data => xaui_tx_arr(i),
rx_ready => crc_rx_ready_arr(i),
tx_ready => crc_tx_ready_arr(i),
phy_mgmt_clk => mm_clk,
phy_mgmt_clk_reset => mm_rst,
phy_mgmt_address => xaui_mosi_arr(i).address(c_xaui_mosi_addr_w-1 DOWNTO 0),
......@@ -197,7 +196,7 @@ BEGIN
phy_mgmt_writedata => xaui_mosi_arr(i).wrdata(c_word_w-1 DOWNTO 0),
phy_mgmt_waitrequest => xaui_miso_arr(i).waitrequest,
rx_channelaligned => a_rx_channelaligned(i),
rx_channelaligned => a_rx_channelaligned_arr(i),
-- Reconfig block connections
reconfig_to_xcvr => reconfig_2_togxb,
......@@ -220,14 +219,14 @@ BEGIN
u_ip_phy_xaui : ip_stratixiv_phy_xaui_soft
PORT MAP (
pll_ref_clk => tr_clk,
xgmii_tx_clk => tx_clk(i),
xgmii_rx_clk => rx_clk(i),
xgmii_rx_dc => xgmii_rx_dc(i),
xgmii_tx_dc => xgmii_tx_dc(i),
xaui_rx_serial_data => xaui_rx(i),
xaui_tx_serial_data => xaui_tx(i),
rx_ready => crc_rx_ready(i),
tx_ready => crc_tx_ready(i),
xgmii_tx_clk => tx_clk_arr(i),
xgmii_rx_clk => rx_clk_arr(i),
xgmii_rx_dc => xgmii_rx_dc_arr(i),
xgmii_tx_dc => xgmii_tx_dc_arr(i),
xaui_rx_serial_data => xaui_rx_arr(i),
xaui_tx_serial_data => xaui_tx_arr(i),
rx_ready => crc_rx_ready_arr(i),
tx_ready => crc_tx_ready_arr(i),
phy_mgmt_clk => mm_clk,
phy_mgmt_clk_reset => mm_rst,
phy_mgmt_address => xaui_mosi_arr(i).address(c_xaui_mosi_addr_w-1 DOWNTO 0),
......@@ -237,7 +236,7 @@ BEGIN
phy_mgmt_writedata => xaui_mosi_arr(i).wrdata(c_word_w-1 DOWNTO 0),
phy_mgmt_waitrequest => xaui_miso_arr(i).waitrequest,
rx_channelaligned => a_rx_channelaligned(i),
rx_channelaligned => a_rx_channelaligned_arr(i),
-- Reconfig block connections
reconfig_to_xcvr => reconfig_soft_togxb,
......
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