added the ip_arria10_e3sge3 hdl_lib_uses_synth keys

libraries/technology/clkbuf/hdllib.cfg

 hdl_lib_name = tech_clkbuf
 hdl_library_clause_name = tech_clkbuf_lib
-hdl_lib_uses_synth = technology ip_arria10_clkbuf_global common
+hdl_lib_uses_synth = technology ip_arria10_clkbuf_global ip_arria10_e3sge3_clkbuf_global common
 hdl_lib_uses_sim = 
 
 hdl_lib_technology = 

libraries/technology/flash/hdllib.cfg

@@ -4,6 +4,8 @@ hdl_lib_uses_synth = technology
                ip_stratixiv_flash
                ip_arria10_asmi_parallel
                ip_arria10_remote_update
+               ip_arria10_e3sge3_asmi_parallel
+               ip_arria10_e3sge3_remote_update
 hdl_lib_uses_sim = 
 
 hdl_lib_technology = 

libraries/technology/fpga_temp_sens/hdllib.cfg

 hdl_lib_name = tech_fpga_temp_sens
 hdl_library_clause_name = tech_fpga_temp_sens_lib
-hdl_lib_uses_synth = technology common ip_arria10_temp_sense
+hdl_lib_uses_synth = technology common ip_arria10_temp_sense ip_arria10_e3sge3_temp_sense
 hdl_lib_uses_sim = 
 
 hdl_lib_technology = 

libraries/technology/fpga_voltage_sens/hdllib.cfg

 hdl_lib_name = tech_fpga_voltage_sens
 hdl_library_clause_name = tech_fpga_voltage_sens_lib
-hdl_lib_uses_synth = technology common ip_arria10_voltage_sense
+hdl_lib_uses_synth = technology common ip_arria10_voltage_sense ip_arria10_e3sge3_voltage_sense
 hdl_lib_uses_sim = 
 
 hdl_lib_technology = 

libraries/technology/fractional_pll/hdllib.cfg

 hdl_lib_name = tech_fractional_pll
 hdl_library_clause_name = tech_fractional_pll_lib
-hdl_lib_uses_synth = technology ip_arria10_fractional_pll_clk200 ip_arria10_fractional_pll_clk125 common
+hdl_lib_uses_synth = technology ip_arria10_fractional_pll_clk200 ip_arria10_fractional_pll_clk125 ip_arria10_e3sge3_fractional_pll_clk200 ip_arria10_e3sge3_fractional_pll_clk125 common
 hdl_lib_uses_sim = 
 
 hdl_lib_technology = 

libraries/technology/iobuf/hdllib.cfg

 hdl_lib_name = tech_iobuf
 hdl_library_clause_name = tech_iobuf_lib
-hdl_lib_uses_synth = technology ip_stratixiv_ddio ip_arria10_ddio
+hdl_lib_uses_synth = technology ip_stratixiv_ddio ip_arria10_ddio ip_arria10_e3sge3_ddio
 hdl_lib_uses_sim = 
 
 hdl_lib_technology = 

libraries/technology/pll/hdllib.cfg

 hdl_lib_name = tech_pll
 hdl_library_clause_name = tech_pll_lib
-hdl_lib_uses_synth = technology ip_stratixiv_pll ip_arria10_pll_xgmii_mac_clocks ip_arria10_pll_clk200 ip_arria10_pll_clk25 ip_stratixiv_pll_clk25 ip_arria10_pll_clk125 common
+hdl_lib_uses_synth = technology 
+                     ip_stratixiv_pll
+                     ip_arria10_pll_xgmii_mac_clocks
+                     ip_arria10_pll_clk200
+                     ip_arria10_pll_clk25
+                     ip_stratixiv_pll_clk25
+                     ip_arria10_pll_clk125
+                     ip_arria10_e3sge3_pll_xgmii_mac_clocks
+                     ip_arria10_e3sge3_pll_clk200
+                     ip_arria10_e3sge3_pll_clk25
+                     ip_arria10_e3sge3_pll_clk125
+                     common
 hdl_lib_uses_sim = 
 
 hdl_lib_technology = 

libraries/technology/tse/hdllib.cfg

@@ -3,6 +3,7 @@ hdl_library_clause_name = tech_tse_lib
 hdl_lib_uses_synth = technology
                ip_stratixiv_tse_sgmii_lvds ip_stratixiv_tse_sgmii_gx
                ip_arria10_tse_sgmii_lvds   ip_arria10_tse_sgmii_gx
+               ip_arria10_e3sge3_tse_sgmii_lvds   ip_arria10_e3sge3_tse_sgmii_gx
                common dp
 hdl_lib_uses_sim =