Corrected dp_clk in comment.

libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd

@@ -128,7 +128,7 @@ BEGIN
   -- The synchronous start_pulse and sync_in in the dp_clk domain cannot be
   -- passed on via two separate common_spulse instances, because then they may
   -- appear at different clock cycles in the mm_clk domain, due to that the
-  -- mm_clk and mm_clk are asynchronous on HW. Therefore use mm_sync_level to
+  -- dp_clk and mm_clk are asynchronous on HW. Therefore use mm_sync_level to
   -- pass on sync_in.
   u_common_spulse_sync : ENTITY common_lib.common_spulse
   GENERIC MAP (