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Commit c102607f authored by Comore's avatar Comore
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Added first version for digital receiver UNB1 back node

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hdl_lib_name = dig_receiver_bn
hdl_library_clause_name = dig_receiver_bn_lib
hdl_lib_uses_synth = common mm dp unb1_board diag
hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
synth_top_level_entity = dig_receiver_bn
quartus_copy_files =
quartus/sopc_dig_receiver_bn.sopc .
modelsim_copy_files =
synth_files =
src/vhdl/adc_lvds.vhd
src/vhdl/dig_receiver_mm.vhd
src/vhdl/dig_rec_bn.vhd
src/vhdl/node_dr_1st_stage.vhd
test_bench_files =
quartus_qsf_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_vhdl_files =
quartus_qip_files =
quartus_sdc_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
set_global_assignment -name QIP_FILE $::env(UNB)/Firmware/modules/common/build/synth/quartus/common.qip
set_global_assignment -name QIP_FILE $::env(UNB)/Firmware/modules/easics/build/synth/quartus/easics.qip
set_global_assignment -name QIP_FILE $::env(UNB)/Firmware/modules/dp/build/synth/quartus/dp_stream.qip
set_global_assignment -name QIP_FILE $::env(UNB)/Firmware/modules/dp/build/synth/quartus/dp_packetize.qip
set_global_assignment -name QIP_FILE $::env(UNB)/Firmware/modules/util/build/synth/quartus/util.qip
set_global_assignment -name QIP_FILE $::env(UNB)/Firmware/modules/ppsh/build/synth/quartus/ppsh.qip
set_global_assignment -name QIP_FILE $::env(UNB)/Firmware/modules/tse/build/synth/quartus/tse.qip
set_global_assignment -name QIP_FILE $::env(UNB)/Firmware/designs/unb_common/build/synth/quartus/unb_common.qip
set_global_assignment -name QIP_FILE $::env(UNB)/Firmware/modules/Lofar/diag/build/synth/quartus/diag.qip
set_global_assignment -name QIP_FILE $::env(UNB)/Firmware/modules/Lofar/i2c/build/synth/quartus/i2c.qip
set_global_assignment -name QIP_FILE $::env(UNB)/Firmware/modules/tr_nonbonded/build/synth/quartus/tr_nonbonded.qip
set_global_assignment -name SEARCH_PATH $::env(UNB)/Firmware/modules/MegaWizard/tse_sgmii_lvds
set_global_assignment -name SEARCH_PATH $::env(UNB)/Firmware/modules/MegaWizard/tse_sgmii_lvds/triple_speed_ethernet-library
set_global_assignment -name SEARCH_PATH $::env(UNB)/Firmware/modules/ddr3_test/src/ip
set_global_assignment -name SEARCH_PATH $::env(UNB)/Firmware/modules/ddr3_test/src/ip/altmemphy-library
set_global_assignment -name QIP_FILE $::env(DRC)/modules/common/build/synth/quartus/DigRec_lib.qip
set_global_assignment -name QIP_FILE $::env(DRC)/modules/test_source/build/synth/quartus/test_generator.qip
set_global_assignment -name QIP_FILE $::env(DRC)/modules/mesh_interface/build/synth/quartus/mesh_interface.qip
set_global_assignment -name QIP_FILE $::env(DRC)/modules/dr_1st_chip_stage/build/synth/quartus/dr_1st_stage.qip
# Pin assignments
# Pin files
set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_general_pins.tcl
set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_other_pins.tcl
set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_tr_clk_pins.tcl
set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(UNB)/Firmware/designs/unb_common/src/tcl/BACK_NODE_mesh_pins.tcl
set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(UNB)/Firmware/designs/unb_common/src/tcl/BACK_NODE_adc_pins.tcl
------------------------------------------------------------------------------
--
-- Design to test Digital Receiver 1st stage (BN)
--
-- Created 23-04-2010 by GC
-- $Author:
-- Description
-- Application for Digital Receiver
-- Includes a (very simple) LVDS receiver
-- a test pattern generator
-- first stage (backnode) of the Digita Receiver application
--
------------------------------------------------------------------------------
--
-- Copyright (C) 2011
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-- INAF (Istituto Nazionale di Radioastronomia)
-- Osservatorio Astrofisico di Arcetri
-- Largo E. Fermi 5 - 50125 Firenze - Italy
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- $Log:
--
LIBRARY IEEE, common_lib, digrec_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
--USE digrec_lib.digrec_pkg.ALL;
ENTITY adc_lvds IS
PORT (
-- GENERAL CHIP PIN
adc_bi : IN t_slv_8_arr(0 TO 3);
adc_clk : IN std_logic_vector(0 TO 3);
adc_scl : OUT std_logic_vector(0 TO 3);
adc_sda : INOUT std_logic_vector(0 TO 3);
-- Output interface
dsp_clk : IN STD_LOGIC;
data_out : OUT signed(63 DOWNTO 0)
);
END adc_lvds;
ARCHITECTURE almost_dummy OF adc_lvds IS
component stratixiv_ddio_in is
port (
datain : in std_logic;
clk : in std_logic;
regoutlo : out std_logic;
regouthi : out std_logic);
end component;
CONSTANT c_data_w : INTEGER := 8;
TYPE t_in_data_arr IS ARRAY(0 to 7) OF SIGNED(7 DOWNTO 0);
SIGNAL rx_data : t_in_data_arr;
BEGIN
u_rx_lvds_abcd : for i in adc_bi'RANGE generate
ddio : for j in adc_bi(0)'RANGE GENERATE
dd_reg : stratixiv_ddio_in
PORT MAP (
datain => adc_bi(i)(j),
regoutlo => rx_data(i)(j),
regouthi => rx_data(i+4)(j),
clk => adc_clk(i)
);
END GENERATE;
END GENERATE;
ADC_SCL <= "0000";
ADC_SDA <= "ZZZZ";
PROCESS
BEGIN
WAIT UNTIL rising_edge(dsp_clk);
FOR i IN 0 TO 7 LOOP
data_out((i+1)*c_data_w-1 DOWNTO i*c_data_w) <= rx_data(i);
END LOOP;
END PROCESS;
END ARCHITECTURE;
This diff is collapsed.
------------------------------------------------------------------------------
--
-- Design to test Digital Receiver 1st stage (BN)
--
-- Created 23-04-2010 by GC
-- $Author:
-- Description
-- Application for Digital Receiver
-- Includes a (very simple) LVDS receiver
-- a test pattern generator
-- first stage (backnode) of the Digita Receiver application
--
------------------------------------------------------------------------------
--
-- Copyright (C) 2011
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-- INAF (Istituto Nazionale di Radioastronomia)
-- Osservatorio Astrofisico di Arcetri
-- Largo E. Fermi 5 - 50125 Firenze - Italy
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- $Log:
--
library ieee;
use ieee.std_logic_1164.all;
USE IEEE.NUMERIC_STD.ALL;
LIBRARY common_lib, dp_lib;
LIBRARY test_generator_lib,digital_receiver_lib;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
--USE unb_common_lib.unb_common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
ENTITY node_dr_1st_stage IS
PORT (
-- mm interface
mm_clock : IN STD_LOGIC;
mm_reset : IN STD_LOGIC;
mm_test_generator_mosi : IN t_mem_mosi;
mm_test_generator_miso : OUT t_mem_miso;
mm_dr_1st_stage_mosi : IN t_mem_mosi;
mm_dr_1st_stage_miso : OUT t_mem_miso;
dsp_clk : IN STD_LOGIC;
stb_1ms : IN STD_LOGIC;
stb_1s : IN STD_LOGIC;
test_point : OUT std_logic_vector(2 DOWNTO 0);
-- input
adc_bi : IN t_slv_8_arr(0 to 3);
adc_clk : IN std_logic_vector(0 TO 3);
adc_scl : OUT std_logic_vector(0 TO 3);
adc_sda : INOUT std_logic_vector(0 TO 3);
-- output
data_out : OUT t_dp_sosi_arr(0 to 3)
);
END entity node_dr_1st_stage;
architecture str of node_dr_1st_stage is
SIGNAL adc_data : signed(63 DOWNTO 0);
SIGNAL stage_input : signed(63 DOWNTO 0);
SIGNAL stage_output : SIGNED(63 DOWNTO 0);
SIGNAL pps_delayed : STD_LOGIC;
SIGNAL test_point_1st_stage : std_logic_vector(3 DOWNTO 0);
CONSTANT c_module_delay : INTEGER := 37; -- just to give a value, for now
BEGIN
adc: ENTITY work.adc_lvds
PORT MAP (
adc_bi => adc_bi,
adc_clk => adc_clk,
adc_scl => adc_scl,
adc_sda => adc_sda,
dsp_clk => dsp_clk,
data_out => adc_data
);
testgen: ENTITY test_generator_lib.test_generator_mm
PORT MAP (
mm_clock => mm_clock,
mm_reset => mm_reset,
mm_mosi => mm_test_generator_mosi,
mm_miso => mm_test_generator_miso,
test_point => test_point(0),
dsp_clock => dsp_clk,
stb_1s => stb_1s,
stb_1ms => stb_1ms,
data_in => adc_data,
data_out => stage_input
);
stage: ENTITY work.mms_dr_1st_stage
PORT MAP (
mm_clock => mm_clock,
mm_reset => mm_reset,
mm_mosi => mm_dr_1st_stage_mosi,
mm_miso => mm_dr_1st_stage_miso,
test_point => test_point_1st_stage,
dsp_clock => dsp_clk,
-- stb_1s => stb_1s,
stb_1ms => stb_1ms,
data_in => stage_input,
data_out => stage_output
);
--
-- delay PPS by amunt fo internal delay in module
--
del_pps: ENTITY digrec_lib.pulse_delay_n
GENERIC MAP (
delay => c_module_delay )
PORT MAP (
clock => dsp_clk,
input => stb_1ms,
output => pps_delayed );
PROCESS(stage_output)
BEGIN
FOR i IN 0 TO 3 LOOP
data_out(i).data <= (OTHERS => '0');
data_out(i).data(47 DOWNTO 0) <=
std_logic_vector(stage_output(i)(1)(1)) & "0000" &
std_logic_vector(stage_output(i)(1)(0)) & "0000" &
std_logic_vector(stage_output(i)(0)(1)) & "0000" &
std_logic_vector(stage_output(i)(0)(0)) & "0000";
data_out(i).valid <= '1';
data_out(i).sop <= pps_delayed;
END LOOP;
END PROCESS;
test_point(1) <= test_point_1st_stage(0);
test_point(2) <= test_point_1st_stage(1);
end architecture;
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