diff --git a/applications/dig_receiver/designs/dig_receiver_bn/hdllib.cfg b/applications/dig_receiver/designs/dig_receiver_bn/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..d2ab4f43f3088dd1d52ddb2f40c38b29cc476ec9
--- /dev/null
+++ b/applications/dig_receiver/designs/dig_receiver_bn/hdllib.cfg
@@ -0,0 +1,32 @@
+hdl_lib_name = dig_receiver_bn
+hdl_library_clause_name = dig_receiver_bn_lib
+hdl_lib_uses_synth = common mm dp unb1_board diag
+hdl_lib_uses_sim =
+
+hdl_lib_technology = ip_stratixiv
+
+synth_top_level_entity = dig_receiver_bn
+
+quartus_copy_files =
+ quartus/sopc_dig_receiver_bn.sopc .
+
+modelsim_copy_files =
+
+synth_files =
+ src/vhdl/adc_lvds.vhd
+ src/vhdl/dig_receiver_mm.vhd
+ src/vhdl/dig_rec_bn.vhd
+ src/vhdl/node_dr_1st_stage.vhd
+
+test_bench_files =
+
+quartus_qsf_files =
+ $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+
+quartus_vhdl_files =
+
+quartus_qip_files =
+
+quartus_sdc_files =
+ $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+
diff --git a/applications/dig_receiver/designs/dig_receiver_bn/quartus/sopc_dig_receiver_bn.sopc b/applications/dig_receiver/designs/dig_receiver_bn/quartus/sopc_dig_receiver_bn.sopc
new file mode 100644
index 0000000000000000000000000000000000000000..98a991ad30529c56b422c190564fed11ac4a0d28
--- /dev/null
+++ b/applications/dig_receiver/designs/dig_receiver_bn/quartus/sopc_dig_receiver_bn.sopc
@@ -0,0 +1,1665 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="sopc_dig_receiver_bn">
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element altpll_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element jtag_uart_0.avalon_jtag_slave
+ {
+ datum baseAddress
+ {
+ value = "25840";
+ type = "long";
+ }
+ }
+ element avs_eth_0
+ {
+ datum _sortIndex
+ {
+ value = "7";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element altpll_0.c0
+ {
+ datum _clockDomain
+ {
+ value = "mm_clk";
+ type = "String";
+ }
+ }
+ element altpll_0.c1
+ {
+ datum _clockDomain
+ {
+ value = "cal_clk";
+ type = "String";
+ }
+ }
+ element altpll_0.c2
+ {
+ datum _clockDomain
+ {
+ value = "tse_clk";
+ type = "String";
+ }
+ }
+ element altpll_0.c3
+ {
+ datum _clockDomain
+ {
+ value = "dp_clk";
+ type = "String";
+ }
+ }
+ element clk_0
+ {
+ datum _sortIndex
+ {
+ value = "4";
+ type = "int";
+ }
+ }
+ element cpu_0
+ {
+ datum _sortIndex
+ {
+ value = "3";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{output_language=VHDL, output_directory=/home/comore/UniBoard_FP7/UniBoard/trunk/Firmware/designs/dr_1st_chip_stage/build/synth/quartus}";
+ type = "String";
+ }
+ datum sopceditor_expanded
+ {
+ value = "1";
+ type = "boolean";
+ }
+ }
+ element eth_10ginst_0
+ {
+ datum _sortIndex
+ {
+ value = "25";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element eth_10ginst_1
+ {
+ datum _sortIndex
+ {
+ value = "26";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element eth_10ginst_2
+ {
+ datum _sortIndex
+ {
+ value = "27";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element cpu_0.jtag_debug_module
+ {
+ datum baseAddress
+ {
+ value = "14336";
+ type = "long";
+ }
+ }
+ element jtag_uart_0
+ {
+ datum _sortIndex
+ {
+ value = "2";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_wdi.mem
+ {
+ datum baseAddress
+ {
+ value = "12288";
+ type = "long";
+ }
+ }
+ element udp_packetizer_st_2.mem
+ {
+ datum baseAddress
+ {
+ value = "25344";
+ type = "long";
+ }
+ }
+ element reg_dpmm_ctrl.mem
+ {
+ datum baseAddress
+ {
+ value = "25864";
+ type = "long";
+ }
+ }
+ element reg_tr_xaui.mem
+ {
+ datum baseAddress
+ {
+ value = "16384";
+ type = "long";
+ }
+ }
+ element reg_system_info.mem
+ {
+ datum baseAddress
+ {
+ value = "24960";
+ type = "long";
+ }
+ }
+ element eth_10ginst_2.mem
+ {
+ datum baseAddress
+ {
+ value = "22528";
+ type = "long";
+ }
+ }
+ element reg_unb_sens.mem
+ {
+ datum baseAddress
+ {
+ value = "25696";
+ type = "long";
+ }
+ }
+ element reg_dpmm_data.mem
+ {
+ datum baseAddress
+ {
+ value = "25856";
+ type = "long";
+ }
+ }
+ element reg_dr_1st_stage.mem
+ {
+ datum baseAddress
+ {
+ value = "24704";
+ type = "long";
+ }
+ }
+ element reg_epcs.mem
+ {
+ datum baseAddress
+ {
+ value = "25728";
+ type = "long";
+ }
+ }
+ element pio_pps.mem
+ {
+ datum baseAddress
+ {
+ value = "25848";
+ type = "long";
+ }
+ }
+ element udp_packetizer_st_1.mem
+ {
+ datum baseAddress
+ {
+ value = "25216";
+ type = "long";
+ }
+ }
+ element reg_remu.mem
+ {
+ datum baseAddress
+ {
+ value = "25760";
+ type = "long";
+ }
+ }
+ element reg_test_generator.mem
+ {
+ datum baseAddress
+ {
+ value = "24576";
+ type = "long";
+ }
+ }
+ element udp_packetizer_st_0.mem
+ {
+ datum baseAddress
+ {
+ value = "25088";
+ type = "long";
+ }
+ }
+ element eth_10ginst_1.mem
+ {
+ datum baseAddress
+ {
+ value = "20480";
+ type = "long";
+ }
+ }
+ element reg_tr_nonbonded.mem
+ {
+ datum baseAddress
+ {
+ value = "25472";
+ type = "long";
+ }
+ }
+ element eth_10ginst_0.mem
+ {
+ datum baseAddress
+ {
+ value = "18432";
+ type = "long";
+ }
+ }
+ element reg_mmdp_ctrl.mem
+ {
+ datum baseAddress
+ {
+ value = "25880";
+ type = "long";
+ }
+ }
+ element reg_mmdp_data.mem
+ {
+ datum baseAddress
+ {
+ value = "25872";
+ type = "long";
+ }
+ }
+ element reg_mesh.mem
+ {
+ datum baseAddress
+ {
+ value = "24832";
+ type = "long";
+ }
+ }
+ element rom_system_info.mem
+ {
+ datum baseAddress
+ {
+ value = "8192";
+ type = "long";
+ }
+ }
+ element avs_eth_0.mms_ram
+ {
+ datum baseAddress
+ {
+ value = "4096";
+ type = "long";
+ }
+ }
+ element avs_eth_0.mms_reg
+ {
+ datum baseAddress
+ {
+ value = "25600";
+ type = "long";
+ }
+ }
+ element avs_eth_0.mms_tse
+ {
+ datum baseAddress
+ {
+ value = "0";
+ type = "long";
+ }
+ }
+ element onchip_memory2_0
+ {
+ datum _sortIndex
+ {
+ value = "1";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element pio_debug_wave
+ {
+ datum _sortIndex
+ {
+ value = "6";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element pio_pps
+ {
+ datum _sortIndex
+ {
+ value = "13";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element pio_wdi
+ {
+ datum _sortIndex
+ {
+ value = "14";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element altpll_0.pll_slave
+ {
+ datum _lockedAddress
+ {
+ value = "0";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "25792";
+ type = "long";
+ }
+ }
+ element reg_dpmm_ctrl
+ {
+ datum _sortIndex
+ {
+ value = "19";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_dpmm_data
+ {
+ datum _sortIndex
+ {
+ value = "18";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_dr_1st_stage
+ {
+ datum _sortIndex
+ {
+ value = "10";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_epcs
+ {
+ datum _sortIndex
+ {
+ value = "22";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_mesh
+ {
+ datum _sortIndex
+ {
+ value = "11";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_mmdp_ctrl
+ {
+ datum _sortIndex
+ {
+ value = "21";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_mmdp_data
+ {
+ datum _sortIndex
+ {
+ value = "20";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_remu
+ {
+ datum _sortIndex
+ {
+ value = "23";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_system_info
+ {
+ datum _sortIndex
+ {
+ value = "16";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_test_generator
+ {
+ datum _sortIndex
+ {
+ value = "9";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_tr_nonbonded
+ {
+ datum _sortIndex
+ {
+ value = "12";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_tr_xaui
+ {
+ datum _sortIndex
+ {
+ value = "24";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_unb_sens
+ {
+ datum _sortIndex
+ {
+ value = "8";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_wdi
+ {
+ datum _sortIndex
+ {
+ value = "15";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element rom_system_info
+ {
+ datum _sortIndex
+ {
+ value = "17";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element pio_debug_wave.s1
+ {
+ datum baseAddress
+ {
+ value = "25808";
+ type = "long";
+ }
+ }
+ element onchip_memory2_0.s1
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "131072";
+ type = "long";
+ }
+ }
+ element timer_0.s1
+ {
+ datum baseAddress
+ {
+ value = "25664";
+ type = "long";
+ }
+ }
+ element pio_wdi.s1
+ {
+ datum baseAddress
+ {
+ value = "25824";
+ type = "long";
+ }
+ }
+ element sopc_dig_receiver_bn
+ {
+ }
+ element timer_0
+ {
+ datum _sortIndex
+ {
+ value = "5";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element udp_packetizer_st_0
+ {
+ datum _sortIndex
+ {
+ value = "28";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element udp_packetizer_st_1
+ {
+ datum _sortIndex
+ {
+ value = "29";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element udp_packetizer_st_2
+ {
+ datum _sortIndex
+ {
+ value = "30";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="EP4SGX230KF40C2" />
+ <parameter name="deviceFamily" value="STRATIXIV" />
+ <parameter name="deviceSpeedGrade" value="" />
+ <parameter name="fabricMode" value="SOPC" />
+ <parameter name="generateLegacySim" value="true" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="true" />
+ <parameter name="hdlLanguage" value="VHDL" />
+ <parameter name="maxAdditionalLatency" value="0" />
+ <parameter name="projectName" value="dig_receiver_bn.qpf" />
+ <parameter name="sopcBorderPoints" value="true" />
+ <parameter name="systemHash" value="-136766889575" />
+ <parameter name="timeStamp" value="1445264044704" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <module kind="clock_source" version="11.1" enabled="1" name="clk_0">
+ <parameter name="clockFrequency" value="25000000" />
+ <parameter name="clockFrequencyKnown" value="true" />
+ <parameter name="inputClockFrequency" value="0" />
+ <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <module kind="altera_nios2" version="11.1" enabled="1" name="cpu_0">
+ <parameter name="userDefinedSettings" value="" />
+ <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
+ <parameter name="setting_showUnpublishedSettings" value="false" />
+ <parameter name="setting_showInternalSettings" value="false" />
+ <parameter name="setting_shadowRegisterSets" value="0" />
+ <parameter name="setting_preciseSlaveAccessErrorException" value="false" />
+ <parameter name="setting_preciseIllegalMemAccessException" value="false" />
+ <parameter name="setting_preciseDivisionErrorException" value="false" />
+ <parameter name="setting_performanceCounter" value="false" />
+ <parameter name="setting_perfCounterWidth" value="_32" />
+ <parameter name="setting_interruptControllerType" value="Internal" />
+ <parameter name="setting_illegalMemAccessDetection" value="false" />
+ <parameter name="setting_illegalInstructionsTrap" value="false" />
+ <parameter name="setting_fullWaveformSignals" value="false" />
+ <parameter name="setting_extraExceptionInfo" value="false" />
+ <parameter name="setting_exportPCB" value="false" />
+ <parameter name="setting_debugSimGen" value="false" />
+ <parameter name="setting_clearXBitsLDNonBypass" value="true" />
+ <parameter name="setting_branchPredictionType" value="Automatic" />
+ <parameter name="setting_bit31BypassDCache" value="true" />
+ <parameter name="setting_bigEndian" value="false" />
+ <parameter name="setting_bhtPtrSz" value="_8" />
+ <parameter name="setting_bhtIndexPcOnly" value="false" />
+ <parameter name="setting_avalonDebugPortPresent" value="false" />
+ <parameter name="setting_alwaysEncrypt" value="true" />
+ <parameter name="setting_allowFullAddressRange" value="false" />
+ <parameter name="setting_activateTrace" value="true" />
+ <parameter name="setting_activateTestEndChecker" value="false" />
+ <parameter name="setting_activateMonitors" value="true" />
+ <parameter name="setting_activateModelChecker" value="false" />
+ <parameter name="setting_HDLSimCachesCleared" value="true" />
+ <parameter name="setting_HBreakTest" value="false" />
+ <parameter name="resetSlave" value="onchip_memory2_0.s1" />
+ <parameter name="resetOffset" value="0" />
+ <parameter name="muldiv_multiplierType" value="NoneSmall" />
+ <parameter name="muldiv_divider" value="false" />
+ <parameter name="mpu_useLimit" value="false" />
+ <parameter name="mpu_numOfInstRegion" value="8" />
+ <parameter name="mpu_numOfDataRegion" value="8" />
+ <parameter name="mpu_minInstRegionSize" value="_12" />
+ <parameter name="mpu_minDataRegionSize" value="_12" />
+ <parameter name="mpu_enabled" value="false" />
+ <parameter name="mmu_uitlbNumEntries" value="_4" />
+ <parameter name="mmu_udtlbNumEntries" value="_6" />
+ <parameter name="mmu_tlbPtrSz" value="_7" />
+ <parameter name="mmu_tlbNumWays" value="_16" />
+ <parameter name="mmu_processIDNumBits" value="_8" />
+ <parameter name="mmu_enabled" value="false" />
+ <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
+ <parameter name="mmu_TLBMissExcSlave" value="" />
+ <parameter name="mmu_TLBMissExcOffset" value="0" />
+ <parameter name="manuallyAssignCpuID" value="false" />
+ <parameter name="internalIrqMaskSystemInfo" value="7" />
+ <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
+ <parameter name="instAddrWidth" value="18" />
+ <parameter name="impl" value="Small" />
+ <parameter name="icache_size" value="_4096" />
+ <parameter name="icache_ramBlockType" value="Automatic" />
+ <parameter name="icache_numTCIM" value="_0" />
+ <parameter name="icache_burstType" value="None" />
+ <parameter name="exceptionSlave" value="onchip_memory2_0.s1" />
+ <parameter name="exceptionOffset" value="32" />
+ <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 1 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 1 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 1 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+ <parameter name="deviceFamilyName" value="Stratix IV" />
+ <parameter name="debug_triggerArming" value="true" />
+ <parameter name="debug_level" value="Level1" />
+ <parameter name="debug_jtagInstanceID" value="0" />
+ <parameter name="debug_embeddedPLL" value="true" />
+ <parameter name="debug_debugReqSignals" value="false" />
+ <parameter name="debug_assignJtagInstanceID" value="false" />
+ <parameter name="debug_OCIOnchipTrace" value="_128" />
+ <parameter name="dcache_size" value="_2048" />
+ <parameter name="dcache_ramBlockType" value="Automatic" />
+ <parameter name="dcache_omitDataMaster" value="false" />
+ <parameter name="dcache_numTCDM" value="_0" />
+ <parameter name="dcache_lineSize" value="_32" />
+ <parameter name="dcache_bursts" value="false" />
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='avs_eth_0.mms_tse' start='0x0' end='0x1000' /><slave name='avs_eth_0.mms_ram' start='0x1000' end='0x2000' /><slave name='rom_system_info.mem' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='reg_tr_xaui.mem' start='0x4000' end='0x4800' /><slave name='eth_10ginst_0.mem' start='0x4800' end='0x5000' /><slave name='eth_10ginst_1.mem' start='0x5000' end='0x5800' /><slave name='eth_10ginst_2.mem' start='0x5800' end='0x6000' /><slave name='reg_test_generator.mem' start='0x6000' end='0x6080' /><slave name='reg_dr_1st_stage.mem' start='0x6080' end='0x6100' /><slave name='reg_mesh.mem' start='0x6100' end='0x6180' /><slave name='reg_system_info.mem' start='0x6180' end='0x6200' /><slave name='udp_packetizer_st_0.mem' start='0x6200' end='0x6280' /><slave name='udp_packetizer_st_1.mem' start='0x6280' end='0x6300' /><slave name='udp_packetizer_st_2.mem' start='0x6300' end='0x6380' /><slave name='reg_tr_nonbonded.mem' start='0x6380' end='0x6400' /><slave name='avs_eth_0.mms_reg' start='0x6400' end='0x6440' /><slave name='timer_0.s1' start='0x6440' end='0x6460' /><slave name='reg_unb_sens.mem' start='0x6460' end='0x6480' /><slave name='reg_epcs.mem' start='0x6480' end='0x64A0' /><slave name='reg_remu.mem' start='0x64A0' end='0x64C0' /><slave name='altpll_0.pll_slave' start='0x64C0' end='0x64D0' /><slave name='pio_debug_wave.s1' start='0x64D0' end='0x64E0' /><slave name='pio_wdi.s1' start='0x64E0' end='0x64F0' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x64F0' end='0x64F8' /><slave name='pio_pps.mem' start='0x64F8' end='0x6500' /><slave name='reg_dpmm_data.mem' start='0x6500' end='0x6508' /><slave name='reg_dpmm_ctrl.mem' start='0x6508' end='0x6510' /><slave name='reg_mmdp_data.mem' start='0x6510' end='0x6518' /><slave name='reg_mmdp_ctrl.mem' start='0x6518' end='0x6520' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
+ <parameter name="dataAddrWidth" value="18" />
+ <parameter name="customInstSlavesSystemInfo" value="<info/>" />
+ <parameter name="cpuReset" value="false" />
+ <parameter name="cpuID" value="0" />
+ <parameter name="clockFrequency" value="125000000" />
+ <parameter name="breakSlave">cpu_0.jtag_debug_module</parameter>
+ <parameter name="breakOffset" value="32" />
+ </module>
+ <module
+ kind="altera_avalon_onchip_memory2"
+ version="11.1"
+ enabled="1"
+ name="onchip_memory2_0">
+ <parameter name="allowInSystemMemoryContentEditor" value="false" />
+ <parameter name="autoInitializationFileName" value="onchip_memory2_0" />
+ <parameter name="blockType" value="M144K" />
+ <parameter name="dataWidth" value="32" />
+ <parameter name="deviceFamily" value="Stratix IV" />
+ <parameter name="dualPort" value="false" />
+ <parameter name="initMemContent" value="true" />
+ <parameter name="initializationFileName" value="onchip_memory2_0" />
+ <parameter name="instanceID" value="NONE" />
+ <parameter name="memorySize" value="131072" />
+ <parameter name="readDuringWriteMode" value="DONT_CARE" />
+ <parameter name="simAllowMRAMContentsFile" value="false" />
+ <parameter name="simMemInitOnlyFilename" value="0" />
+ <parameter name="singleClockOperation" value="false" />
+ <parameter name="slave1Latency" value="1" />
+ <parameter name="slave2Latency" value="1" />
+ <parameter name="useNonDefaultInitFile" value="false" />
+ <parameter name="useShallowMemBlocks" value="false" />
+ <parameter name="writable" value="true" />
+ </module>
+ <module
+ kind="altera_avalon_jtag_uart"
+ version="11.1"
+ enabled="1"
+ name="jtag_uart_0">
+ <parameter name="allowMultipleConnections" value="false" />
+ <parameter name="hubInstanceID" value="0" />
+ <parameter name="readBufferDepth" value="64" />
+ <parameter name="readIRQThreshold" value="8" />
+ <parameter name="simInputCharacterStream"><![CDATA[a
+q]]></parameter>
+ <parameter name="simInteractiveOptions">INTERACTIVE_ASCII_OUTPUT</parameter>
+ <parameter name="useRegistersForReadBuffer" value="false" />
+ <parameter name="useRegistersForWriteBuffer" value="false" />
+ <parameter name="useRelativePathForSimFile" value="false" />
+ <parameter name="writeBufferDepth" value="64" />
+ <parameter name="writeIRQThreshold" value="8" />
+ </module>
+ <module kind="altpll" version="11.1" enabled="1" name="altpll_0">
+ <parameter name="HIDDEN_CUSTOM_ELABORATION">altpll_avalon_elaboration</parameter>
+ <parameter name="HIDDEN_CUSTOM_POST_EDIT">altpll_avalon_post_edit</parameter>
+ <parameter name="INTENDED_DEVICE_FAMILY" value="Stratix IV" />
+ <parameter name="WIDTH_CLOCK" value="10" />
+ <parameter name="WIDTH_PHASECOUNTERSELECT" value="" />
+ <parameter name="PRIMARY_CLOCK" value="" />
+ <parameter name="INCLK0_INPUT_FREQUENCY" value="40000" />
+ <parameter name="INCLK1_INPUT_FREQUENCY" value="" />
+ <parameter name="OPERATION_MODE" value="NORMAL" />
+ <parameter name="PLL_TYPE" value="AUTO" />
+ <parameter name="QUALIFY_CONF_DONE" value="" />
+ <parameter name="COMPENSATE_CLOCK" value="CLK0" />
+ <parameter name="SCAN_CHAIN" value="" />
+ <parameter name="GATE_LOCK_SIGNAL" value="" />
+ <parameter name="GATE_LOCK_COUNTER" value="" />
+ <parameter name="LOCK_HIGH" value="" />
+ <parameter name="LOCK_LOW" value="" />
+ <parameter name="VALID_LOCK_MULTIPLIER" value="" />
+ <parameter name="INVALID_LOCK_MULTIPLIER" value="" />
+ <parameter name="SWITCH_OVER_ON_LOSSCLK" value="" />
+ <parameter name="SWITCH_OVER_ON_GATED_LOCK" value="" />
+ <parameter name="ENABLE_SWITCH_OVER_COUNTER" value="" />
+ <parameter name="SKIP_VCO" value="" />
+ <parameter name="SWITCH_OVER_COUNTER" value="" />
+ <parameter name="SWITCH_OVER_TYPE" value="" />
+ <parameter name="FEEDBACK_SOURCE" value="" />
+ <parameter name="BANDWIDTH" value="" />
+ <parameter name="BANDWIDTH_TYPE" value="AUTO" />
+ <parameter name="SPREAD_FREQUENCY" value="" />
+ <parameter name="DOWN_SPREAD" value="" />
+ <parameter name="SELF_RESET_ON_GATED_LOSS_LOCK" value="" />
+ <parameter name="SELF_RESET_ON_LOSS_LOCK" value="" />
+ <parameter name="CLK0_MULTIPLY_BY" value="5" />
+ <parameter name="CLK1_MULTIPLY_BY" value="8" />
+ <parameter name="CLK2_MULTIPLY_BY" value="5" />
+ <parameter name="CLK3_MULTIPLY_BY" value="8" />
+ <parameter name="CLK4_MULTIPLY_BY" value="" />
+ <parameter name="CLK5_MULTIPLY_BY" value="" />
+ <parameter name="CLK6_MULTIPLY_BY" value="" />
+ <parameter name="CLK7_MULTIPLY_BY" value="" />
+ <parameter name="CLK8_MULTIPLY_BY" value="" />
+ <parameter name="CLK9_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK0_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK1_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK2_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK3_MULTIPLY_BY" value="" />
+ <parameter name="CLK0_DIVIDE_BY" value="1" />
+ <parameter name="CLK1_DIVIDE_BY" value="5" />
+ <parameter name="CLK2_DIVIDE_BY" value="1" />
+ <parameter name="CLK3_DIVIDE_BY" value="1" />
+ <parameter name="CLK4_DIVIDE_BY" value="" />
+ <parameter name="CLK5_DIVIDE_BY" value="" />
+ <parameter name="CLK6_DIVIDE_BY" value="" />
+ <parameter name="CLK7_DIVIDE_BY" value="" />
+ <parameter name="CLK8_DIVIDE_BY" value="" />
+ <parameter name="CLK9_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK0_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK1_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK2_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK3_DIVIDE_BY" value="" />
+ <parameter name="CLK0_PHASE_SHIFT" value="0" />
+ <parameter name="CLK1_PHASE_SHIFT" value="0" />
+ <parameter name="CLK2_PHASE_SHIFT" value="0" />
+ <parameter name="CLK3_PHASE_SHIFT" value="0" />
+ <parameter name="CLK4_PHASE_SHIFT" value="" />
+ <parameter name="CLK5_PHASE_SHIFT" value="" />
+ <parameter name="CLK6_PHASE_SHIFT" value="" />
+ <parameter name="CLK7_PHASE_SHIFT" value="" />
+ <parameter name="CLK8_PHASE_SHIFT" value="" />
+ <parameter name="CLK9_PHASE_SHIFT" value="" />
+ <parameter name="EXTCLK0_PHASE_SHIFT" value="" />
+ <parameter name="EXTCLK1_PHASE_SHIFT" value="" />
+ <parameter name="EXTCLK2_PHASE_SHIFT" value="" />
+ <parameter name="EXTCLK3_PHASE_SHIFT" value="" />
+ <parameter name="CLK0_DUTY_CYCLE" value="50" />
+ <parameter name="CLK1_DUTY_CYCLE" value="50" />
+ <parameter name="CLK2_DUTY_CYCLE" value="50" />
+ <parameter name="CLK3_DUTY_CYCLE" value="50" />
+ <parameter name="CLK4_DUTY_CYCLE" value="" />
+ <parameter name="CLK5_DUTY_CYCLE" value="" />
+ <parameter name="CLK6_DUTY_CYCLE" value="" />
+ <parameter name="CLK7_DUTY_CYCLE" value="" />
+ <parameter name="CLK8_DUTY_CYCLE" value="" />
+ <parameter name="CLK9_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK0_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK1_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK2_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK3_DUTY_CYCLE" value="" />
+ <parameter name="PORT_clkena0" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena1" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena2" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena3" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena4" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena5" value="PORT_UNUSED" />
+ <parameter name="PORT_extclkena0" value="" />
+ <parameter name="PORT_extclkena1" value="" />
+ <parameter name="PORT_extclkena2" value="" />
+ <parameter name="PORT_extclkena3" value="" />
+ <parameter name="PORT_extclk0" value="" />
+ <parameter name="PORT_extclk1" value="" />
+ <parameter name="PORT_extclk2" value="" />
+ <parameter name="PORT_extclk3" value="" />
+ <parameter name="PORT_CLKBAD0" value="PORT_UNUSED" />
+ <parameter name="PORT_CLKBAD1" value="PORT_UNUSED" />
+ <parameter name="PORT_clk0" value="PORT_USED" />
+ <parameter name="PORT_clk1" value="PORT_USED" />
+ <parameter name="PORT_clk2" value="PORT_USED" />
+ <parameter name="PORT_clk3" value="PORT_USED" />
+ <parameter name="PORT_clk4" value="PORT_UNUSED" />
+ <parameter name="PORT_clk5" value="PORT_UNUSED" />
+ <parameter name="PORT_clk6" value="PORT_UNUSED" />
+ <parameter name="PORT_clk7" value="PORT_UNUSED" />
+ <parameter name="PORT_clk8" value="PORT_UNUSED" />
+ <parameter name="PORT_clk9" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANDATA" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANDATAOUT" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANDONE" value="PORT_UNUSED" />
+ <parameter name="PORT_SCLKOUT1" value="" />
+ <parameter name="PORT_SCLKOUT0" value="" />
+ <parameter name="PORT_ACTIVECLOCK" value="PORT_UNUSED" />
+ <parameter name="PORT_CLKLOSS" value="PORT_UNUSED" />
+ <parameter name="PORT_INCLK1" value="PORT_UNUSED" />
+ <parameter name="PORT_INCLK0" value="PORT_USED" />
+ <parameter name="PORT_FBIN" value="PORT_UNUSED" />
+ <parameter name="PORT_PLLENA" value="PORT_UNUSED" />
+ <parameter name="PORT_CLKSWITCH" value="PORT_UNUSED" />
+ <parameter name="PORT_ARESET" value="PORT_UNUSED" />
+ <parameter name="PORT_PFDENA" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANCLK" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANACLR" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANREAD" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANWRITE" value="PORT_UNUSED" />
+ <parameter name="PORT_ENABLE0" value="" />
+ <parameter name="PORT_ENABLE1" value="" />
+ <parameter name="PORT_LOCKED" value="PORT_USED" />
+ <parameter name="PORT_CONFIGUPDATE" value="PORT_UNUSED" />
+ <parameter name="PORT_FBOUT" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASEDONE" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASESTEP" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASEUPDOWN" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANCLKENA" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASECOUNTERSELECT" value="PORT_UNUSED" />
+ <parameter name="PORT_VCOOVERRANGE" value="" />
+ <parameter name="PORT_VCOUNDERRANGE" value="" />
+ <parameter name="DPA_MULTIPLY_BY" value="" />
+ <parameter name="DPA_DIVIDE_BY" value="" />
+ <parameter name="DPA_DIVIDER" value="" />
+ <parameter name="VCO_MULTIPLY_BY" value="" />
+ <parameter name="VCO_DIVIDE_BY" value="" />
+ <parameter name="SCLKOUT0_PHASE_SHIFT" value="" />
+ <parameter name="SCLKOUT1_PHASE_SHIFT" value="" />
+ <parameter name="VCO_FREQUENCY_CONTROL" value="" />
+ <parameter name="VCO_PHASE_SHIFT_STEP" value="" />
+ <parameter name="USING_FBMIMICBIDIR_PORT" value="OFF" />
+ <parameter name="SCAN_CHAIN_MIF_FILE" value="" />
+ <parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
+ <parameter name="HIDDEN_CONSTANTS">CT#CLK2_DIVIDE_BY 1 CT#PORT_clk9 PORT_UNUSED CT#PORT_clk8 PORT_UNUSED CT#PORT_clk7 PORT_UNUSED CT#PORT_clk6 PORT_UNUSED CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_USED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 1 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT 0 CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 10 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 8 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 40000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_FBOUT PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 5 CT#INTENDED_DEVICE_FAMILY {Stratix IV} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 5 CT#CLK3_MULTIPLY_BY 8 CT#USING_FBMIMICBIDIR_PORT OFF CT#PORT_LOCKED PORT_USED</parameter>
+ <parameter name="HIDDEN_PRIVATES">PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 25.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#OUTPUT_FREQ_UNIT3 MHz PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK3 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#LVDS_PHASE_SHIFT_UNIT3 deg PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#OUTPUT_FREQ_MODE3 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ3 200.00000000 PT#OUTPUT_FREQ2 125.00000000 PT#OUTPUT_FREQ1 40.00000000 PT#OUTPUT_FREQ0 125.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT3 0.00000000 PT#PHASE_SHIFT2 0.00000000 PT#DIV_FACTOR3 1 PT#PHASE_SHIFT1 0.00000000 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE3 200.000000 PT#EFF_OUTPUT_FREQ_VALUE2 125.000000 PT#EFF_OUTPUT_FREQ_VALUE1 40.000000 PT#EFF_OUTPUT_FREQ_VALUE0 125.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK3 1 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT3 deg PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR3 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE3 50.00000000 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {Stratix IV} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1256297171721465.mif PT#ACTIVECLK_CHECK 0</parameter>
+ <parameter name="HIDDEN_USED_PORTS">UP#locked used UP#c3 used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used</parameter>
+ <parameter name="HIDDEN_IS_NUMERIC">IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK3_DIVIDE_BY 1 IN#CLK1_MULTIPLY_BY 1 IN#CLK3_DUTY_CYCLE 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR3 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#CLK3_MULTIPLY_BY 1 IN#MULT_FACTOR3 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1</parameter>
+ <parameter name="HIDDEN_MF_PORTS">MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1</parameter>
+ <parameter name="HIDDEN_IF_PORTS">IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#c3 {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}</parameter>
+ <parameter name="HIDDEN_IS_FIRST_EDIT" value="0" />
+ <parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE" value="25000000" />
+ <parameter name="AUTO_DEVICE_FAMILY" value="Stratix IV" />
+ </module>
+ <module
+ kind="altera_avalon_pio"
+ version="11.1"
+ enabled="1"
+ name="pio_debug_wave">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="125000000" />
+ <parameter name="direction" value="Output" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="32" />
+ </module>
+ <module kind="altera_avalon_timer" version="11.1" enabled="1" name="timer_0">
+ <parameter name="alwaysRun" value="true" />
+ <parameter name="counterSize" value="32" />
+ <parameter name="fixedPeriod" value="true" />
+ <parameter name="period" value="1" />
+ <parameter name="periodUnits" value="MSEC" />
+ <parameter name="resetOutput" value="false" />
+ <parameter name="snapshot" value="false" />
+ <parameter name="systemFrequency" value="125000000" />
+ <parameter name="timeoutPulseOutput" value="false" />
+ <parameter name="timerPreset">SIMPLE_PERIODIC_INTERRUPT</parameter>
+ </module>
+ <module kind="altera_avalon_pio" version="11.1" enabled="1" name="pio_wdi">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="125000000" />
+ <parameter name="direction" value="Output" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="1" />
+ </module>
+ <module kind="avs2_eth_coe" version="1.0" enabled="1" name="avs_eth_0">
+ <parameter name="AUTO_MM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_unb_sens">
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_test_generator">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_dr_1st_stage">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_mesh">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_tr_nonbonded">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="pio_pps">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_system_info">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="rom_system_info">
+ <parameter name="g_adr_w" value="10" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_dpmm_data">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_dpmm_ctrl">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_mmdp_data">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_mmdp_ctrl">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_epcs">
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_remu">
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module
+ kind="avs_common_mm_readlatency0"
+ version="1.0"
+ enabled="1"
+ name="reg_tr_xaui">
+ <parameter name="g_adr_w" value="9" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module
+ kind="avs_common_mm_readlatency0"
+ version="1.0"
+ enabled="1"
+ name="eth_10ginst_0">
+ <parameter name="g_adr_w" value="9" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module
+ kind="avs_common_mm_readlatency0"
+ version="1.0"
+ enabled="1"
+ name="eth_10ginst_1">
+ <parameter name="g_adr_w" value="9" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module
+ kind="avs_common_mm_readlatency0"
+ version="1.0"
+ enabled="1"
+ name="eth_10ginst_2">
+ <parameter name="g_adr_w" value="9" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="udp_packetizer_st_0">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="udp_packetizer_st_1">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="udp_packetizer_st_2">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_wdi">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.instruction_master"
+ end="cpu_0.jtag_debug_module">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3800" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="cpu_0.jtag_debug_module">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3800" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.instruction_master"
+ end="onchip_memory2_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00020000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="onchip_memory2_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00020000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="jtag_uart_0.avalon_jtag_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x64f0" />
+ </connection>
+ <connection
+ kind="interrupt"
+ version="11.1"
+ start="cpu_0.d_irq"
+ end="jtag_uart_0.irq">
+ <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="altpll_0.pll_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x64c0" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="cpu_0.clk" />
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="jtag_uart_0.clk" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="altpll_0.inclk_interface" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="pio_debug_wave.clk" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="pio_debug_wave.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x64d0" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="timer_0.clk" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="timer_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x6440" />
+ </connection>
+ <connection kind="interrupt" version="11.1" start="cpu_0.d_irq" end="timer_0.irq">
+ <parameter name="irqNumber" value="1" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="pio_wdi.clk" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="pio_wdi.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x64e0" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="onchip_memory2_0.clk1" />
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="avs_eth_0.mm" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="avs_eth_0.mms_tse">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="avs_eth_0.mms_reg">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x6400" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="avs_eth_0.mms_ram">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x1000" />
+ </connection>
+ <connection
+ kind="interrupt"
+ version="11.1"
+ start="cpu_0.d_irq"
+ end="avs_eth_0.interrupt">
+ <parameter name="irqNumber" value="2" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_unb_sens.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_unb_sens.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x6460" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_test_generator.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_test_generator.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x6000" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_dr_1st_stage.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_dr_1st_stage.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x6080" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="reg_mesh.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_mesh.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x6100" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="pio_pps.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="pio_pps.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x64f8" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_system_info.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_system_info.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x6180" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="rom_system_info.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="rom_system_info.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x2000" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_dpmm_data.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_dpmm_data.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x6500" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_dpmm_ctrl.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_dpmm_ctrl.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x6508" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_mmdp_data.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_mmdp_data.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x6510" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_mmdp_ctrl.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_mmdp_ctrl.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x6518" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="reg_epcs.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_epcs.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x6480" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="reg_remu.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_remu.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x64a0" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_tr_xaui.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_tr_xaui.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x4000" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="eth_10ginst_0.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="eth_10ginst_0.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x4800" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="eth_10ginst_1.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="eth_10ginst_1.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x5000" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="eth_10ginst_2.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="eth_10ginst_2.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x5800" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="udp_packetizer_st_0.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="udp_packetizer_st_0.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x6200" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="udp_packetizer_st_1.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="udp_packetizer_st_1.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x6280" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="udp_packetizer_st_2.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="udp_packetizer_st_2.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x6300" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_tr_nonbonded.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x6380" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_tr_nonbonded.system" />
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="reg_wdi.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_wdi.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3000" />
+ </connection>
+</system>
diff --git a/applications/dig_receiver/designs/dig_receiver_bn/src/tcl/dig_receiver_bn.tcl b/applications/dig_receiver/designs/dig_receiver_bn/src/tcl/dig_receiver_bn.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..f34c98ab5e5b9f39abc874dc4ffec0b1d9a65972
--- /dev/null
+++ b/applications/dig_receiver/designs/dig_receiver_bn/src/tcl/dig_receiver_bn.tcl
@@ -0,0 +1,19 @@
+set_global_assignment -name QIP_FILE $::env(UNB)/Firmware/modules/common/build/synth/quartus/common.qip
+set_global_assignment -name QIP_FILE $::env(UNB)/Firmware/modules/easics/build/synth/quartus/easics.qip
+set_global_assignment -name QIP_FILE $::env(UNB)/Firmware/modules/dp/build/synth/quartus/dp_stream.qip
+set_global_assignment -name QIP_FILE $::env(UNB)/Firmware/modules/dp/build/synth/quartus/dp_packetize.qip
+set_global_assignment -name QIP_FILE $::env(UNB)/Firmware/modules/util/build/synth/quartus/util.qip
+set_global_assignment -name QIP_FILE $::env(UNB)/Firmware/modules/ppsh/build/synth/quartus/ppsh.qip
+set_global_assignment -name QIP_FILE $::env(UNB)/Firmware/modules/tse/build/synth/quartus/tse.qip
+set_global_assignment -name QIP_FILE $::env(UNB)/Firmware/designs/unb_common/build/synth/quartus/unb_common.qip
+set_global_assignment -name QIP_FILE $::env(UNB)/Firmware/modules/Lofar/diag/build/synth/quartus/diag.qip
+set_global_assignment -name QIP_FILE $::env(UNB)/Firmware/modules/Lofar/i2c/build/synth/quartus/i2c.qip
+set_global_assignment -name QIP_FILE $::env(UNB)/Firmware/modules/tr_nonbonded/build/synth/quartus/tr_nonbonded.qip
+set_global_assignment -name SEARCH_PATH $::env(UNB)/Firmware/modules/MegaWizard/tse_sgmii_lvds
+set_global_assignment -name SEARCH_PATH $::env(UNB)/Firmware/modules/MegaWizard/tse_sgmii_lvds/triple_speed_ethernet-library
+set_global_assignment -name SEARCH_PATH $::env(UNB)/Firmware/modules/ddr3_test/src/ip
+set_global_assignment -name SEARCH_PATH $::env(UNB)/Firmware/modules/ddr3_test/src/ip/altmemphy-library
+set_global_assignment -name QIP_FILE $::env(DRC)/modules/common/build/synth/quartus/DigRec_lib.qip
+set_global_assignment -name QIP_FILE $::env(DRC)/modules/test_source/build/synth/quartus/test_generator.qip
+set_global_assignment -name QIP_FILE $::env(DRC)/modules/mesh_interface/build/synth/quartus/mesh_interface.qip
+set_global_assignment -name QIP_FILE $::env(DRC)/modules/dr_1st_chip_stage/build/synth/quartus/dr_1st_stage.qip
diff --git a/applications/dig_receiver/designs/dig_receiver_bn/src/tcl/dig_receiver_bn_pins.tcl b/applications/dig_receiver/designs/dig_receiver_bn/src/tcl/dig_receiver_bn_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..0db797c152e7ba37e19062f075167a60906bb8c4
--- /dev/null
+++ b/applications/dig_receiver/designs/dig_receiver_bn/src/tcl/dig_receiver_bn_pins.tcl
@@ -0,0 +1,10 @@
+# Pin assignments
+
+# Pin files
+set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_general_pins.tcl
+set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
+set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
+set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_other_pins.tcl
+set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_tr_clk_pins.tcl
+set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(UNB)/Firmware/designs/unb_common/src/tcl/BACK_NODE_mesh_pins.tcl
+set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(UNB)/Firmware/designs/unb_common/src/tcl/BACK_NODE_adc_pins.tcl
diff --git a/applications/dig_receiver/designs/dig_receiver_bn/src/vhdl/adc_lvds.vhd b/applications/dig_receiver/designs/dig_receiver_bn/src/vhdl/adc_lvds.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..71256c0be38754c9fd47168b1b684949e06f60d3
--- /dev/null
+++ b/applications/dig_receiver/designs/dig_receiver_bn/src/vhdl/adc_lvds.vhd
@@ -0,0 +1,103 @@
+------------------------------------------------------------------------------
+--
+-- Design to test Digital Receiver 1st stage (BN)
+--
+-- Created 23-04-2010 by GC
+-- $Author:
+-- Description
+-- Application for Digital Receiver
+-- Includes a (very simple) LVDS receiver
+-- a test pattern generator
+-- first stage (backnode) of the Digita Receiver application
+--
+------------------------------------------------------------------------------
+--
+-- Copyright (C) 2011
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+--
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+-- INAF (Istituto Nazionale di Radioastronomia)
+-- Osservatorio Astrofisico di Arcetri
+-- Largo E. Fermi 5 - 50125 Firenze - Italy
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+-- $Log:
+--
+
+
+LIBRARY IEEE, common_lib, digrec_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+--USE digrec_lib.digrec_pkg.ALL;
+
+ENTITY adc_lvds IS
+ PORT (
+ -- GENERAL CHIP PIN
+ adc_bi : IN t_slv_8_arr(0 TO 3);
+ adc_clk : IN std_logic_vector(0 TO 3);
+ adc_scl : OUT std_logic_vector(0 TO 3);
+ adc_sda : INOUT std_logic_vector(0 TO 3);
+
+ -- Output interface
+ dsp_clk : IN STD_LOGIC;
+ data_out : OUT signed(63 DOWNTO 0)
+ );
+END adc_lvds;
+
+ARCHITECTURE almost_dummy OF adc_lvds IS
+
+ component stratixiv_ddio_in is
+ port (
+ datain : in std_logic;
+ clk : in std_logic;
+ regoutlo : out std_logic;
+ regouthi : out std_logic);
+ end component;
+
+CONSTANT c_data_w : INTEGER := 8;
+TYPE t_in_data_arr IS ARRAY(0 to 7) OF SIGNED(7 DOWNTO 0);
+SIGNAL rx_data : t_in_data_arr;
+
+BEGIN
+
+u_rx_lvds_abcd : for i in adc_bi'RANGE generate
+ ddio : for j in adc_bi(0)'RANGE GENERATE
+ dd_reg : stratixiv_ddio_in
+ PORT MAP (
+ datain => adc_bi(i)(j),
+ regoutlo => rx_data(i)(j),
+ regouthi => rx_data(i+4)(j),
+ clk => adc_clk(i)
+ );
+ END GENERATE;
+
+ END GENERATE;
+
+ ADC_SCL <= "0000";
+ ADC_SDA <= "ZZZZ";
+
+ PROCESS
+ BEGIN
+ WAIT UNTIL rising_edge(dsp_clk);
+ FOR i IN 0 TO 7 LOOP
+ data_out((i+1)*c_data_w-1 DOWNTO i*c_data_w) <= rx_data(i);
+ END LOOP;
+ END PROCESS;
+
+END ARCHITECTURE;
+
+
diff --git a/applications/dig_receiver/designs/dig_receiver_bn/src/vhdl/dig_rec_bn.vhd b/applications/dig_receiver/designs/dig_receiver_bn/src/vhdl/dig_rec_bn.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ae0de40fa5a4c1401a8c1505015f96d5cf720038
--- /dev/null
+++ b/applications/dig_receiver/designs/dig_receiver_bn/src/vhdl/dig_rec_bn.vhd
@@ -0,0 +1,580 @@
+------------------------------------------------------------------------------
+--
+-- Design to test Digital Receiver 1st stage (BN)
+--
+-- Created 23-04-2010 by GC
+-- $Author:
+-- Purpose
+-- combine pinning and infrastructure designs for the general IO,
+-- Avalon component, dr_1st_stage peripheral, LVDS receiver
+-- and the FN_BN transceivers.
+--
+-- See if any conflicts arise
+-- Investigate resource utilisation and power consumption
+--
+-- Input occurs from LVDS ports, with samples 0->A; 1->B, 2->C, 3->D
+-- Main clock is from external SMA connector at frequency g_ext_clk_freq
+-- Output towards the FN-BN mesh
+------------------------------------------------------------------------------
+--
+-- Copyright (C) 2011
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+--
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+-- INAF (Istituto Nazionale di Radioastronomia)
+-- Osservatorio Astrofisico di Arcetri
+-- Largo E. Fermi 5 - 50125 Firenze - Italy
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+-- $Log:
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+USE IEEE.NUMERIC_STD.ALL;
+LIBRARY common_lib, unb1_board_lib, dp_lib, tse_lib, bf_lib;
+LIBRARY mesh_lib, digrec_lib;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+--USE tse_lib.tse_pkg.ALL;
+--USE tse_lib.eth_pkg.ALL;
+
+
+ENTITY dig_receiver_bn IS
+GENERIC (
+ -- General
+ g_sim : BOOLEAN := FALSE;
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ -- g_fw_version : t_unb_fw_version := (2, 0); -- firmware version x.y
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_stamp_svn : NATURAL := 0; -- SVN revision -- set by QSF
+ -- Auxiliary Interface
+ -- g_aux : t_c_unb_aux := c_unb_aux;
+ g_ext_clk_freq : NATURAL := 256*10**6 -- Frequency of the external CLK signal
+ -- Design specific
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ -- SA_CLK : IN STD_LOGIC; -- SerDes Clock IO (10GbE)
+ SB_CLK : IN STD_LOGIC; -- SerDes Clock IO (10GbE)
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+ -- FPGA Interconnects Front-Node Back-Node
+ -- 3rd link connected to CMU link not used
+ --
+ FN_BN_0_TX : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ -- FN_BN_0_RX : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+ FN_BN_1_TX : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ -- FN_BN_1_RX : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+ FN_BN_2_TX : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ -- FN_BN_2_RX : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+ FN_BN_3_TX : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+ -- FN_BN_3_RX : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+
+ -- ADC Interface
+ ADC_BI_A : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ ADC_BI_A_CLK : IN STD_LOGIC;
+ ADC_BI_B : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ ADC_BI_B_CLK : IN STD_LOGIC;
+ ADC_BI_C : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ ADC_BI_C_CLK : IN STD_LOGIC;
+ ADC_BI_D : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ ADC_BI_D_CLK : IN STD_LOGIC;
+ ADC_SCL : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+ ADC_SDA : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+
+ -- 1GbE Control Interface
+ ETH_clk : IN STD_LOGIC;
+ ETH_SGIN : IN STD_LOGIC;
+ ETH_SGOUT : OUT STD_LOGIC;
+
+ -- I2C Interface to Sensors
+ sens_sc : INOUT STD_LOGIC;
+ sens_sd : INOUT STD_LOGIC;
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0)
+ );
+END entity dig_receiver_bn;
+
+architecture str of dig_receiver_bn is
+
+-- UniBoard -- IP base address used by unb_os : 10.99.xx.yy
+ CONSTANT c_base_ip : STD_LOGIC_VECTOR(16-1 DOWNTO 0) := X"0A63";
+ -- Firmware version x.y
+ CONSTANT c_fw_version : t_unb1_board_fw_version := (1, 1);
+ CONSTANT c_design_name : STRING := "Digital Receiver BN";
+ CONSTANT c_design_note : STRING := "draft";
+ -- Use PHY Interface
+ -- TYPE t_c_unb_use_phy IS RECORD
+ -- eth1g : NATURAL;
+ -- eth10g : NATURAL;
+ -- tr_mesh : NATURAL;
+ -- tr_back : NATURAL;
+ -- ddr3_I : NATURAL;
+ -- ddr3_II : NATURAL;
+ -- adc : NATURAL;
+ -- wdi : NATURAL;
+ -- END RECORD;
+ -- In simulation we don't need the 1GbE core for MM control, deselect it in c_use_phy based on g_sim
+ CONSTANT c_use_phy : t_c_unb1_board_use_phy := (sel_a_b(g_sim, 0, 1), 0, 1, 0, 0, 0, 1, 1);
+
+ CONSTANT c_use_qsys : BOOLEAN := FALSE;
+ --g_design_name="unb1_minimal_qsys";
+ CONSTANT c_use_sopc : BOOLEAN := NOT c_use_qsys;
+--I2C sens
+ SIGNAL reg_unb_sens_mosi : t_mem_mosi; -- mms_unb_sens registers
+ SIGNAL reg_unb_sens_miso : t_mem_miso;
+
+-- MM register interfaces
+ SIGNAL reg_wdi_mosi : t_mem_mosi;
+ SIGNAL reg_wdi_miso : t_mem_miso;
+ SIGNAL reg_unb_system_info_mosi : t_mem_mosi;
+ SIGNAL reg_unb_system_info_miso : t_mem_miso;
+ SIGNAL rom_unb_system_info_mosi : t_mem_mosi;
+ SIGNAL rom_unb_system_info_miso : t_mem_miso;
+ SIGNAL reg_ppsh_mosi : t_mem_mosi;
+ SIGNAL reg_ppsh_miso : t_mem_miso;
+
+ -- eth1g
+ SIGNAL eth1g_tse_clk : STD_LOGIC;
+ SIGNAL eth1g_mm_rst : STD_LOGIC;
+ SIGNAL eth1g_tse_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH TSE MAC registers
+ SIGNAL eth1g_tse_miso : t_mem_miso;
+ SIGNAL eth1g_reg_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH control and status registers
+ SIGNAL eth1g_reg_miso : t_mem_miso;
+ SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt
+ SIGNAL eth1g_ram_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH rx frame and tx frame memory
+ SIGNAL eth1g_ram_miso : t_mem_miso;
+ -- SIGNAL eth1g_led : t_tse_led;
+
+ -- EPCS read
+ SIGNAL reg_dpmm_data_mosi : t_mem_mosi;
+ SIGNAL reg_dpmm_data_miso : t_mem_miso;
+ SIGNAL reg_dpmm_ctrl_mosi : t_mem_mosi;
+ SIGNAL reg_dpmm_ctrl_miso : t_mem_miso;
+
+ -- EPCS write
+ SIGNAL reg_mmdp_data_mosi : t_mem_mosi;
+ SIGNAL reg_mmdp_data_miso : t_mem_miso;
+ SIGNAL reg_mmdp_ctrl_mosi : t_mem_mosi;
+ SIGNAL reg_mmdp_ctrl_miso : t_mem_miso;
+
+ -- EPCS status/control
+ SIGNAL reg_epcs_mosi : t_mem_mosi;
+ SIGNAL reg_epcs_miso : t_mem_miso;
+
+ -- Remote Update
+ SIGNAL reg_remu_mosi : t_mem_mosi;
+ SIGNAL reg_remu_miso : t_mem_miso;
+
+ -- MM external peripheral
+ -- tr_back = eth10g (not used)
+ SIGNAL eth10g_mm_rst : STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS=>'1');
+ SIGNAL eth10g_mac_rst_n : STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS=>'1');
+ SIGNAL eth10g_tpg_mosi_arr : t_mem_mosi_arr(2 DOWNTO 0) := (OTHERS=>c_mem_mosi_rst);
+ SIGNAL eth10g_tpg_miso_arr : t_mem_miso_arr(2 DOWNTO 0) := (OTHERS=>c_mem_miso_rst);
+ SIGNAL eth10g_udp_mosi_arr : t_mem_mosi_arr(2 DOWNTO 0) := (OTHERS=>c_mem_mosi_rst);
+ SIGNAL eth10g_udp_miso_arr : t_mem_miso_arr(2 DOWNTO 0) := (OTHERS=>c_mem_miso_rst);
+ SIGNAL eth10g_mac_mosi_arr : t_mem_mosi_arr(2 DOWNTO 0) := (OTHERS=>c_mem_mosi_rst);
+ SIGNAL eth10g_mac_miso_arr : t_mem_miso_arr(2 DOWNTO 0) := (OTHERS=>c_mem_miso_rst);
+
+ -- ADC input
+ SIGNAL reg_adc_lvds_mosi : t_mem_mosi;
+ SIGNAL reg_adc_lvds_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL adc_bi : t_slv_8_arr(0 to 3);
+ SIGNAL adc_clk : std_logic_vector(0 TO 3);
+
+ -- Test generator
+ SIGNAL reg_test_generator_mosi : t_mem_mosi;
+ SIGNAL reg_test_generator_miso : t_mem_miso;
+
+ -- DR 1st stage
+ SIGNAL reg_dr_1st_stage_mosi : t_mem_mosi;
+ SIGNAL reg_dr_1st_stage_miso : t_mem_miso;
+ SIGNAL data_out_to_mesh : t_dp_sosi_arr(0 TO 3);
+
+ -- Dig. rec. 2nd stage (not used)
+ SIGNAL reg_dr_2nd_stage_mosi : t_mem_mosi;
+ SIGNAL reg_dr_2nd_stage_miso : t_mem_miso := c_mem_miso_rst;
+
+ -- mesh link
+ SIGNAL reg_mesh_mosi : t_mem_mosi;
+ SIGNAL reg_mesh_miso : t_mem_miso;
+ SIGNAL reg_tr_nonbonded_mosi : t_mem_mosi;
+ SIGNAL reg_tr_nonbonded_miso : t_mem_miso;
+ SIGNAL fn_bn_tx : std_logic_vector(11 DOWNTO 0);
+ SIGNAL fn_bn_rx : std_logic_vector(11 DOWNTO 0);
+
+ -- timing
+ SIGNAL dp_pps : STD_LOGIC;
+ SIGNAL dp_rst : STD_LOGIC;
+ SIGNAL dp_clk : STD_LOGIC;
+ SIGNAL stb_1ms : STD_LOGIC;
+ SIGNAL stb_1s : STD_LOGIC;
+ SIGNAL led_pps : STD_LOGIC;
+ -- signals for buffering clocks
+ SIGNAL clk_0 : STD_LOGIC;
+ SIGNAL sys_clk : STD_LOGIC;
+ SIGNAL sys_locked : STD_LOGIC;
+ SIGNAL ETH_clk_0 : STD_LOGIC;
+ -- timing
+ SIGNAL xo_clk : STD_LOGIC;
+ SIGNAL xo_rst : STD_LOGIC;
+ SIGNAL xo_rst_n : STD_LOGIC;
+ SIGNAL mm_clk : STD_LOGIC;
+ SIGNAL mm_rst : STD_LOGIC;
+ SIGNAL mm_locked : STD_LOGIC;
+ SIGNAL cal_clk : STD_LOGIC;
+ SIGNAL epcs_clk : STD_LOGIC;
+ -- PIOs
+ SIGNAL pout_debug_wave : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ SIGNAL pin_pps : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ SIGNAL pout_wdi : STD_LOGIC;
+ --SIGNAL pin_system_info : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ -- system ID
+ SIGNAL this_chip_id : STD_LOGIC_VECTOR(c_unb1_board_nof_chip_w-1 DOWNTO 0);
+ SIGNAL this_bck_id : STD_LOGIC_VECTOR(c_unb1_board_nof_uniboard_w-1 DOWNTO 0);
+ SIGNAL cs_sim : STD_LOGIC;
+
+begin
+
+-----------------------------------------------------------------------------
+ -- SOPC system
+ -----------------------------------------------------------------------------
+
+u_control : ENTITY work.dig_receiver_mm
+PORT MAP (
+ -- 1) global signals:
+ xo_clk => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
+ reset_n => xo_rst_n,
+ mm_clk => mm_clk, -- PLL clk[0]=125 MHz system clock that the NIOS2 & MM bus run on
+ cal_clk => cal_clk, -- PLL clk[1]=40 MHz calibration clock for the IO reconfiguration
+ tse_clk => eth1g_tse_clk,-- PLL clk[2]=125 MHz dedicated clock for the 1 Gbit Ethern
+ dp_clk => dp_clk,
+ -- the_altpll_
+ mm_locked => mm_locked,
+ -- the_avs_eth_0
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+ -- the_reg_unb_sens
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+ -- System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+ -- the_reg_adc_lvds
+ reg_adc_lvds_mosi => reg_adc_lvds_mosi,
+ reg_adc_lvds_miso => reg_adc_lvds_miso,
+ -- the_reg_test_generator
+ reg_test_generator_mosi => reg_test_generator_mosi,
+ reg_test_generator_miso => reg_test_generator_miso,
+ -- the_reg_dr_1st_stage
+ reg_dr_1st_stage_mosi => reg_dr_1st_stage_mosi,
+ reg_dr_1st_stage_miso => reg_dr_1st_stage_miso,
+ -- the_reg_dr_2nd_stage
+ reg_dr_2nd_stage_mosi => reg_dr_2nd_stage_mosi,
+ reg_dr_2nd_stage_miso => reg_dr_2nd_stage_miso,
+ -- the_reg_mesh_tx
+ reg_mesh_mosi => reg_mesh_mosi,
+ reg_mesh_miso => reg_mesh_miso,
+ -- the_reg_tr_nonbonded
+ reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
+ reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
+ -- the_eth_10ginst_0
+ eth10g_mac_mosi_arr => eth10g_mac_mosi_arr,
+ eth10g_mac_miso_arr => eth10g_mac_miso_arr,
+ -- the_udp_packetizer_st_0
+ eth10g_udp_mosi_arr => eth10g_udp_mosi_arr,
+ eth10g_udp_miso_arr => eth10g_udp_miso_arr,
+ -- the_pio_debug_wave
+ pout_debug_wave => pout_debug_wave,
+ -- the_pio_pps
+ -- in_port_to_the_pio_pps => pin_pps,
+ -- the_pio_system_info
+ -- in_port_to_the_pio_system_info => pin_system_info,
+ -- the_pio_wdi
+ pout_wdi => pout_wdi
+ );
+ -----------------------------------------------------------------------------
+ -- General control function
+ -----------------------------------------------------------------------------
+ u_ctrl : ENTITY unb1_board_lib.ctrl_unb1_board
+ GENERIC MAP (
+ -- General
+ g_sim => g_sim,
+ g_base_ip => c_base_ip,
+ g_design_name => c_design_name,
+ g_design_note => c_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_aux => c_unb1_board_aux,
+
+ g_sim_flash_model => FALSE,
+ g_dp_clk_freq => g_ext_clk_freq,
+ g_udp_offload => FALSE,
+ g_app_led_green => TRUE,
+ -- Auxiliary Interface
+ g_use_phy => c_use_phy,
+ g_dp_clk_use_pll => TRUE,
+ g_xo_clk_use_pll => FALSE
+ )
+ PORT MAP (
+ --
+ -- >>> SOPC system with conduit peripheral MM bus
+ --
+ -- System
+ cs_sim => cs_sim, --out
+ xo_clk => xo_clk, -- out 25 MHz from pin, reference for the PLL in the SOPC design
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n, -- out to SOPC design
+ mm_clk => mm_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ mm_clk_out => OPEN,
+ mm_locked => mm_locked, --
+ mm_locked_out => OPEN,
+ mm_rst => mm_rst, -- to SOPC slaves
+ epcs_clk => epcs_clk,
+
+ dp_rst => dp_rst, -- synced to dp_clk
+ dp_clk => dp_clk, -- clock for dp logic (200 or 256 MHz
+ dp_pps => dp_pps, -- pps to dp logic
+ dp_rst_in => dp_rst, -- must be connected with previous 2
+ dp_clk_in => dp_clk,
+ -- output identificatives
+ this_chip_id => this_chip_id,
+ this_bck_id => this_bck_id,
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+ --
+ app_led_green => led_pps,
+ --
+ -- >>> Ctrl FPGA pins
+ --
+ -- General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO(c_unb1_board_testio.tst_lo-1 DOWNTO 0)
+ => TESTIO(c_unb1_board_testio.tst_lo-1 DOWNTO 0),
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
+
+--
+-- Application
+--
+--
+-- Input data remapping
+--
+process(ADC_BI_A,ADC_BI_B,ADC_BI_C,ADC_BI_D,
+ ADC_BI_A_CLK, ADC_BI_B_CLK, ADC_BI_C_CLK, ADC_BI_D_CLK)
+ BEGIN
+ adc_bi(0) <= ADC_BI_A;
+ adc_bi(1) <= ADC_BI_B;
+ adc_bi(2) <= ADC_BI_C;
+ adc_bi(3) <= ADC_BI_D;
+ adc_clk(0) <= ADC_BI_A_CLK;
+ adc_clk(1) <= ADC_BI_B_CLK;
+ adc_clk(2) <= ADC_BI_C_CLK;
+ adc_clk(3) <= ADC_BI_D_CLK;
+ END PROCESS;
+
+stage: ENTITY work.node_dr_1st_stage
+ PORT MAP (
+ -- mm interface
+ mm_clock => mm_clk,
+ mm_reset => mm_rst,
+ mm_test_generator_mosi => reg_test_generator_mosi,
+ mm_test_generator_miso => reg_test_generator_miso,
+ mm_dr_1st_stage_mosi => reg_dr_1st_stage_mosi,
+ mm_dr_1st_stage_miso => reg_dr_1st_stage_miso,
+ dsp_clk => dp_clk,
+ stb_1ms => stb_1ms,
+ stb_1s => stb_1s,
+ test_point => testio(c_unb1_board_testio.tst_lo+2 DOWNTO c_unb1_board_testio.tst_lo),
+ -- input
+ adc_bi => adc_bi,
+ adc_clk => adc_clk,
+ adc_scl => ADC_SCL,
+ adc_sda => ADC_SDA,
+ -- output
+ data_out => data_out_to_mesh);
+--
+-- FN-BN mesh Uncomment when updated
+--
+--mesh: ENTITY mesh_lib.mesh_nonbonded
+-- GENERIC MAP (
+-- g_word_size => 48,
+-- g_tx => TRUE,
+-- g_rx => FALSE )
+-- PORT MAP (
+-- mm_clock => mm_clk,
+-- mm_reset => mm_rst,
+-- mm_mesh_tx_mosi => reg_mesh_mosi,
+-- mm_mesh_tx_miso => reg_mesh_miso,
+-- mm_mesh_rx_mosi => c_mem_mosi_rst,
+-- mm_mesh_rx_miso => OPEN,
+-- mm_tr_mosi => reg_tr_nonbonded_mosi,
+-- mm_tr_miso => reg_tr_nonbonded_miso,
+-- test_point => testio(c_unb1_board_testio.tst_lo+3),
+-- dsp_reset => dp_rst,
+-- dsp_clock => dp_clk,
+-- data_in => data_out_to_mesh,
+-- tr_clock => SB_CLK,
+-- cal_rec_clock => cal_clk,
+-- tx_dataout => fn_bn_tx,
+-- rx_datain => fn_bn_rx
+-- );
+ --PROCESS (FN_BN_0_RX, FN_BN_1_RX, FN_BN_2_RX, FN_BN_3_RX, fn_bn_tx)
+ PROCESS(fn_bn_tx)
+ BEGIN
+ FOR i IN 0 TO 2 LOOP
+ FN_BN_0_TX(i) <= fn_bn_tx(0+i);
+ FN_BN_1_TX(i) <= fn_bn_tx(3+i);
+ FN_BN_2_TX(i) <= fn_bn_tx(6+i);
+ FN_BN_3_TX(i) <= fn_bn_tx(9+i);
+ fn_bn_rx(0+i) <= '0';
+ fn_bn_rx(3+i) <= '0';
+ fn_bn_rx(6+i) <= '0';
+ fn_bn_rx(9+i) <= '0';
+-- fn_bn_rx(0+i) <= FN_BN_0_RX(i);
+-- fn_bn_rx(3+i) <= FN_BN_1_RX(i);
+-- fn_bn_rx(6+i) <= FN_BN_2_RX(i);
+-- fn_bn_rx(9+i) <= FN_BN_3_RX(i);
+ END LOOP;
+-- FN_BN_0_TX(3) <= '0';
+-- FN_BN_1_TX(3) <= '0';
+-- FN_BN_2_TX(3) <= '0';
+-- FN_BN_3_TX(3) <= '0';
+ END PROCESS;
+
+ --
+ -- Generate 1 cycle pps and ms pulses
+ -- pps led can be used for a front panel activity LED
+ --
+pps_generator: common_oa_lib.pps_gen
+ GENERIC MAP (
+ frequency => g_ext_clk_freq / 10**6 )
+ PORT MAP (
+ clock => dp_clk,
+ pps_in => dp_pps,
+ sync_enable => '1',
+ sync_delay => "0000",
+ us_out => open,
+ ms_out => stb_1ms,
+ pps_out => stb_1s,
+ pps_led => led_pps);
+
+end architecture;
diff --git a/applications/dig_receiver/designs/dig_receiver_bn/src/vhdl/dig_receiver_mm.vhd b/applications/dig_receiver/designs/dig_receiver_bn/src/vhdl/dig_receiver_mm.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..99cf35acdc18542ccddac1fb05688e529b248b9b
--- /dev/null
+++ b/applications/dig_receiver/designs/dig_receiver_bn/src/vhdl/dig_receiver_mm.vhd
@@ -0,0 +1,381 @@
+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.tb_common_mem_pkg.ALL;
+USE common_lib.common_field_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+
+ENTITY dig_receiver_mm IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE;
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0
+ );
+ PORT (
+ reset_n : IN STD_LOGIC;
+ pll_reset : IN STD_LOGIC:= '0';
+ xo_clk : IN STD_LOGIC;
+ tse_clk : OUT STD_LOGIC;-- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethern
+ -- the_altpll_0
+ mm_clk : OUT STD_LOGIC;-- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
+ cal_clk : OUT STD_LOGIC;-- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
+ dp_clk : OUT STD_LOGIC;-- PLL clk[2] = 200 MHz DSP processing clock
+ mm_locked : OUT STD_LOGIC;-- PLL locked
+ --
+ pout_wdi : OUT STD_LOGIC;
+ pout_debug_wave : OUT STD_LOGIC_vector(31 DOWNTO 0);
+ reg_wdi_mosi : OUT t_mem_mosi;
+ reg_wdi_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_unb_system_info_mosi : OUT t_mem_mosi;
+ reg_unb_system_info_miso : IN t_mem_miso := c_mem_miso_rst;
+ rom_unb_system_info_mosi : OUT t_mem_mosi;
+ rom_unb_system_info_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_unb_sens_mosi : OUT t_mem_mosi;
+ reg_unb_sens_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_ppsh_mosi : OUT t_mem_mosi;
+ reg_ppsh_miso : IN t_mem_miso := c_mem_miso_rst;
+ -- eth1g
+ eth1g_mm_rst : OUT STD_LOGIC;
+ eth1g_reg_interrupt : IN STD_LOGIC;
+ eth1g_ram_mosi : OUT t_mem_mosi;
+ eth1g_ram_miso : IN t_mem_miso := c_mem_miso_rst;
+ eth1g_reg_mosi : OUT t_mem_mosi;
+ eth1g_reg_miso : IN t_mem_miso := c_mem_miso_rst;
+ eth1g_tse_mosi : OUT t_mem_mosi;
+ eth1g_tse_miso : IN t_mem_miso := c_mem_miso_rst;
+ -- EPCS read/write
+ reg_dpmm_data_mosi : OUT t_mem_mosi;
+ reg_dpmm_data_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_dpmm_ctrl_mosi : OUT t_mem_mosi;
+ reg_dpmm_ctrl_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_mmdp_data_mosi : OUT t_mem_mosi;
+ reg_mmdp_data_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_mmdp_ctrl_mosi : OUT t_mem_mosi;
+ reg_mmdp_ctrl_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_epcs_mosi : OUT t_mem_mosi;
+ reg_epcs_miso : IN t_mem_miso := c_mem_miso_rst;
+ -- remote update
+ reg_remu_mosi : OUT t_mem_mosi;
+ reg_remu_miso : IN t_mem_miso := c_mem_miso_rst;
+ --
+ reg_tr_nonbonded_mosi : OUT t_mem_mosi;
+ reg_tr_nonbonded_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_tr_xaui_mosi : OUT t_mem_mosi;
+ reg_tr_xaui_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_adc_lvds_mosi : OUT t_mem_mosi;
+ reg_adc_lvds_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_test_generator_mosi : OUT t_mem_mosi;
+ reg_test_generator_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_dr_1st_stage_mosi : OUT t_mem_mosi;
+ reg_dr_1st_stage_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_dr_2nd_stage_mosi : OUT t_mem_mosi;
+ reg_dr_2nd_stage_miso : IN t_mem_miso := c_mem_miso_rst;
+
+ reg_mesh_mosi : OUT t_mem_mosi;
+ reg_mesh_miso : IN t_mem_miso := c_mem_miso_rst;
+
+ eth10g_mac_mosi_arr : OUT t_mem_mosi_arr(0 TO 2);
+ eth10g_mac_miso_arr : IN t_mem_miso_arr(0 TO 2) := (OTHERS => c_mem_miso_rst);
+ eth10g_udp_mosi_arr : OUT t_mem_mosi_arr(0 TO 2);
+ eth10g_udp_miso_arr : IN t_mem_miso_arr(0 TO 2) := (OTHERS => c_mem_miso_rst)
+);
+END ENTITY dig_receiver_mm;
+
+ARCHITECTURE a_str OF dig_receiver_mm IS
+
+BEGIN
+
+u_sopc : ENTITY work.sopc_dig_receiver_bn
+PORT MAP (
+ -- 1) global signals:
+ clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
+ reset_n => reset_n,
+ mm_clk => mm_clk, -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
+ cal_clk => cal_clk, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
+ tse_clk => tse_clk, -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethern
+ dp_clk => dp_clk, -- PLL clok[3] = 200 MHz altpll_0_c3_out => dsp_clk,
+
+ -- the_altpll_0
+ locked_from_the_altpll_0 => mm_locked,
+ phasedone_from_the_altpll_0 => OPEN,
+ areset_to_the_altpll_0 => pll_reset,
+ -- the_avs_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_unb_sens
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_pio_pps
+ coe_clk_export_from_the_pio_pps => OPEN,
+ coe_reset_export_from_the_pio_pps => OPEN,
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1), -- 1 bit address width so must use (0)
+ coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
+ coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
+ coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_pio_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_reg_system_info => OPEN,
+ coe_reset_export_from_the_reg_system_info => OPEN,
+ coe_address_export_from_the_reg_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_reg_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_reg_system_info => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_reg_system_info => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_rom_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_pio_wdi
+ out_port_from_the_pio_wdi => pout_wdi,
+ -- the_reg_dpmm_data EPCS read
+ coe_clk_export_from_the_reg_dpmm_data => OPEN,
+ coe_reset_export_from_the_reg_dpmm_data => OPEN,
+ coe_address_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.address(0),
+ coe_read_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.rd,
+ coe_readdata_export_to_the_reg_dpmm_data => reg_dpmm_data_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wr,
+ coe_writedata_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_dpmm_ctrl
+ coe_clk_export_from_the_reg_dpmm_ctrl => OPEN,
+ coe_reset_export_from_the_reg_dpmm_ctrl => OPEN,
+ coe_address_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.address(0),
+ coe_read_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.rd,
+ coe_readdata_export_to_the_reg_dpmm_ctrl => reg_dpmm_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wr,
+ coe_writedata_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_mmdp_data EPCS read
+ coe_clk_export_from_the_reg_mmdp_data => OPEN,
+ coe_reset_export_from_the_reg_mmdp_data => OPEN,
+ coe_address_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.address(0),
+ coe_read_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.rd,
+ coe_readdata_export_to_the_reg_mmdp_data => reg_mmdp_data_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wr,
+ coe_writedata_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_mmdp_ctrl
+ coe_clk_export_from_the_reg_mmdp_ctrl => OPEN,
+ coe_reset_export_from_the_reg_mmdp_ctrl => OPEN,
+ coe_address_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.address(0),
+ coe_read_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.rd,
+ coe_readdata_export_to_the_reg_mmdp_ctrl => reg_mmdp_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wr,
+ coe_writedata_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- EPCS status/control
+ coe_address_export_from_the_reg_epcs => reg_epcs_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_epcs_adr_w-1 DOWNTO 0),
+ coe_clk_export_from_the_reg_epcs => OPEN,
+ coe_read_export_from_the_reg_epcs => reg_epcs_mosi.rd,
+ coe_readdata_export_to_the_reg_epcs => reg_epcs_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_reset_export_from_the_reg_epcs => OPEN,
+ coe_write_export_from_the_reg_epcs => reg_epcs_mosi.wr,
+ coe_writedata_export_from_the_reg_epcs => reg_epcs_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- Remote Update
+ coe_address_export_from_the_reg_remu => reg_remu_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_remu_adr_w-1 DOWNTO 0),
+ coe_clk_export_from_the_reg_remu => OPEN,
+ coe_read_export_from_the_reg_remu => reg_remu_mosi.rd,
+ coe_readdata_export_to_the_reg_remu => reg_remu_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_reset_export_from_the_reg_remu => OPEN,
+ coe_write_export_from_the_reg_remu => reg_remu_mosi.wr,
+ coe_writedata_export_from_the_reg_remu => reg_remu_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+-- -- the_reg_ppsh
+-- coe_address_export_from_the_reg_ppsh => reg_ppsh_mosi.address(c_reg_ppsh_adr_w-1 DOWNTO 0),
+-- coe_clk_export_from_the_reg_ppsh => OPEN,
+-- coe_read_export_from_the_reg_ppsh => reg_ppsh_mosi.rd,
+-- coe_readdata_export_to_the_reg_ppsh => reg_ppsh_miso.rddata(c_word_w-1 DOWNTO 0),
+-- coe_reset_export_from_the_reg_ppsh => OPEN,
+-- coe_write_export_from_the_reg_ppsh => reg_ppsh_mosi.wr,
+-- coe_writedata_export_from_the_reg_ppsh => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ -- the_reg_adc_lvds
+ coe_address_export_from_the_reg_adc_lvds => reg_adc_lvds_mosi.address(4 DOWNTO 0),
+ coe_clk_export_from_the_reg_adc_lvds => OPEN,
+ coe_read_export_from_the_reg_adc_lvds => reg_adc_lvds_mosi.rd,
+ coe_readdata_export_to_the_reg_adc_lvds => reg_adc_lvds_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_reset_export_from_the_reg_adc_lvds => OPEN,
+ coe_write_export_from_the_reg_adc_lvds => reg_adc_lvds_mosi.wr,
+ coe_writedata_export_from_the_reg_adc_lvds => reg_adc_lvds_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_test_generator
+ coe_address_export_from_the_reg_test_generator => reg_test_generator_mosi.address(4 DOWNTO 0),
+ coe_clk_export_from_the_reg_test_generator => OPEN,
+ coe_read_export_from_the_reg_test_generator => reg_test_generator_mosi.rd,
+ coe_readdata_export_to_the_reg_test_generator => reg_test_generator_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_reset_export_from_the_reg_test_generator => OPEN,
+ coe_write_export_from_the_reg_test_generator => reg_test_generator_mosi.wr,
+ coe_writedata_export_from_the_reg_test_generator=> reg_test_generator_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_dr_1st_stage
+ coe_address_export_from_the_reg_dr_1st_stage => reg_dr_1st_stage_mosi.address(4 DOWNTO 0),
+ coe_clk_export_from_the_reg_dr_1st_stage => OPEN,
+ coe_read_export_from_the_reg_dr_1st_stage => reg_dr_1st_stage_mosi.rd,
+ coe_readdata_export_to_the_reg_dr_1st_stage => reg_dr_1st_stage_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_reset_export_from_the_reg_dr_1st_stage => OPEN,
+ coe_write_export_from_the_reg_dr_1st_stage => reg_dr_1st_stage_mosi.wr,
+ coe_writedata_export_from_the_reg_dr_1st_stage => reg_dr_1st_stage_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_dr_2nd_stage
+ coe_address_export_from_the_reg_dr_2nd_stage => reg_dr_2nd_stage_mosi.address(5 DOWNTO 0),
+ coe_clk_export_from_the_reg_dr_2nd_stage => OPEN,
+ coe_read_export_from_the_reg_dr_2nd_stage => reg_dr_2nd_stage_mosi.rd,
+ coe_readdata_export_to_the_reg_dr_2nd_stage => reg_dr_2nd_stage_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_reset_export_from_the_reg_dr_2nd_stage => OPEN,
+ coe_write_export_from_the_reg_dr_2nd_stage => reg_dr_2nd_stage_mosi.wr,
+ coe_writedata_export_from_the_reg_dr_2nd_stage => reg_dr_2nd_stage_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_mesh_tx
+ coe_address_export_from_the_reg_mesh => reg_mesh_mosi.address(4 DOWNTO 0),
+ coe_clk_export_from_the_reg_mesh => OPEN,
+ coe_read_export_from_the_reg_mesh => reg_mesh_mosi.rd,
+ coe_readdata_export_to_the_reg_mesh => reg_mesh_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_reset_export_from_the_reg_mesh => OPEN,
+ coe_write_export_from_the_reg_mesh => reg_mesh_mosi.wr,
+ coe_writedata_export_from_the_reg_mesh => reg_mesh_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_tr_nonbonded
+ coe_address_export_from_the_reg_tr_nonbonded => reg_tr_nonbonded_mosi.address(4 DOWNTO 0),
+ coe_clk_export_from_the_reg_tr_nonbonded => OPEN,
+ coe_read_export_from_the_reg_tr_nonbonded => reg_tr_nonbonded_mosi.rd,
+ coe_readdata_export_to_the_reg_tr_nonbonded => reg_tr_nonbonded_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_reset_export_from_the_reg_tr_nonbonded => OPEN,
+ coe_write_export_from_the_reg_tr_nonbonded => reg_tr_nonbonded_mosi.wr,
+ coe_writedata_export_from_the_reg_tr_nonbonded => reg_tr_nonbonded_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ -- the_reg_tr_xaui
+ coe_clk_export_from_the_reg_tr_xaui => OPEN,
+ coe_reset_export_from_the_reg_tr_xaui => OPEN, -- use mm reset from tpg
+ coe_address_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.address(8 DOWNTO 0), -- [8:0]
+ coe_write_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.wr,
+ coe_writedata_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ coe_read_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.rd,
+ coe_readdata_export_to_the_reg_tr_xaui => reg_tr_xaui_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_waitrequest_export_to_the_reg_tr_xaui => reg_tr_xaui_miso.waitrequest,
+ -- the_eth_10ginst_0
+ coe_clk_export_from_the_eth_10ginst_0 => OPEN,
+ coe_reset_export_from_the_eth_10ginst_0 => OPEN, -- use mm reset from tpg
+ coe_address_export_from_the_eth_10ginst_0 => eth10g_mac_mosi_arr(0).address(8 DOWNTO 0), -- [8:0]
+ coe_write_export_from_the_eth_10ginst_0 => eth10g_mac_mosi_arr(0).wr,
+ coe_writedata_export_from_the_eth_10ginst_0 => eth10g_mac_mosi_arr(0).wrdata(c_word_w-1 DOWNTO 0),
+ coe_read_export_from_the_eth_10ginst_0 => eth10g_mac_mosi_arr(0).rd,
+ coe_readdata_export_to_the_eth_10ginst_0 => eth10g_mac_miso_arr(0).rddata(c_word_w-1 DOWNTO 0),
+ coe_waitrequest_export_to_the_eth_10ginst_0 => eth10g_mac_miso_arr(0).waitrequest,
+
+ -- the_eth_10ginst_1
+ coe_clk_export_from_the_eth_10ginst_1 => OPEN,
+ coe_reset_export_from_the_eth_10ginst_1 => OPEN, -- use mm reset from tpg
+ coe_address_export_from_the_eth_10ginst_1 => eth10g_mac_mosi_arr(1).address(8 DOWNTO 0), -- [8:0]
+ coe_write_export_from_the_eth_10ginst_1 => eth10g_mac_mosi_arr(1).wr,
+ coe_writedata_export_from_the_eth_10ginst_1 => eth10g_mac_mosi_arr(1).wrdata(c_word_w-1 DOWNTO 0),
+ coe_read_export_from_the_eth_10ginst_1 => eth10g_mac_mosi_arr(1).rd,
+ coe_readdata_export_to_the_eth_10ginst_1 => eth10g_mac_miso_arr(1).rddata(c_word_w-1 DOWNTO 0),
+ coe_waitrequest_export_to_the_eth_10ginst_1 => eth10g_mac_miso_arr(1).waitrequest,
+
+ -- the_eth_10ginst_2
+ coe_clk_export_from_the_eth_10ginst_2 => OPEN,
+ coe_reset_export_from_the_eth_10ginst_2 => OPEN, -- use mm reset from tpg
+ coe_address_export_from_the_eth_10ginst_2 => eth10g_mac_mosi_arr(2).address(8 DOWNTO 0), -- [8:0]
+ coe_write_export_from_the_eth_10ginst_2 => eth10g_mac_mosi_arr(2).wr,
+ coe_writedata_export_from_the_eth_10ginst_2 => eth10g_mac_mosi_arr(2).wrdata(c_word_w-1 DOWNTO 0),
+ coe_read_export_from_the_eth_10ginst_2 => eth10g_mac_mosi_arr(2).rd,
+ coe_readdata_export_to_the_eth_10ginst_2 => eth10g_mac_miso_arr(2).rddata(c_word_w-1 DOWNTO 0),
+ coe_waitrequest_export_to_the_eth_10ginst_2 => eth10g_mac_miso_arr(2).waitrequest,
+
+ -- the_udp_packetizer_st_0
+ coe_clk_export_from_the_udp_packetizer_st_0 => OPEN,
+ coe_reset_export_from_the_udp_packetizer_st_0 => OPEN, -- use mm reset from tpg
+ coe_address_export_from_the_udp_packetizer_st_0 => eth10g_udp_mosi_arr(0).address(4 DOWNTO 0), -- [2:0]
+ coe_write_export_from_the_udp_packetizer_st_0 => eth10g_udp_mosi_arr(0).wr,
+ coe_writedata_export_from_the_udp_packetizer_st_0 => eth10g_udp_mosi_arr(0).wrdata(c_word_w-1 DOWNTO 0),
+ coe_read_export_from_the_udp_packetizer_st_0 => eth10g_udp_mosi_arr(0).rd,
+ coe_readdata_export_to_the_udp_packetizer_st_0 => eth10g_udp_miso_arr(0).rddata(c_word_w-1 DOWNTO 0),
+
+ -- the_udp_packetizer_st_1
+ coe_clk_export_from_the_udp_packetizer_st_1 => OPEN,
+ coe_reset_export_from_the_udp_packetizer_st_1 => OPEN, -- use mm reset from tpg
+ coe_address_export_from_the_udp_packetizer_st_1 => eth10g_udp_mosi_arr(1).address(4 DOWNTO 0), -- [2:0]
+ coe_write_export_from_the_udp_packetizer_st_1 => eth10g_udp_mosi_arr(1).wr,
+ coe_writedata_export_from_the_udp_packetizer_st_1 => eth10g_udp_mosi_arr(1).wrdata(c_word_w-1 DOWNTO 0),
+ coe_read_export_from_the_udp_packetizer_st_1 => eth10g_udp_mosi_arr(1).rd,
+ coe_readdata_export_to_the_udp_packetizer_st_1 => eth10g_udp_miso_arr(1).rddata(c_word_w-1 DOWNTO 0),
+
+ -- the_udp_packetizer_st_2
+ coe_clk_export_from_the_udp_packetizer_st_2 => OPEN,
+ coe_reset_export_from_the_udp_packetizer_st_2 => OPEN, -- use mm reset from tpg
+ coe_address_export_from_the_udp_packetizer_st_2 => eth10g_udp_mosi_arr(2).address(4 DOWNTO 0), -- [2:0]
+ coe_write_export_from_the_udp_packetizer_st_2 => eth10g_udp_mosi_arr(2).wr,
+ coe_writedata_export_from_the_udp_packetizer_st_2 => eth10g_udp_mosi_arr(2).wrdata(c_word_w-1 DOWNTO 0),
+ coe_read_export_from_the_udp_packetizer_st_2 => eth10g_udp_mosi_arr(2).rd,
+ coe_readdata_export_to_the_udp_packetizer_st_2 => eth10g_udp_miso_arr(2).rddata(c_word_w-1 DOWNTO 0),
+
+ -- the_pio_debug_wave
+ out_port_from_the_pio_debug_wave => pout_debug_wave
+ );
+
+END ARCHITECTURE;
diff --git a/applications/dig_receiver/designs/dig_receiver_bn/src/vhdl/node_dr_1st_stage.vhd b/applications/dig_receiver/designs/dig_receiver_bn/src/vhdl/node_dr_1st_stage.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0cf3d46b862f5b8b139776019fc8229a4de6ac66
--- /dev/null
+++ b/applications/dig_receiver/designs/dig_receiver_bn/src/vhdl/node_dr_1st_stage.vhd
@@ -0,0 +1,155 @@
+------------------------------------------------------------------------------
+--
+-- Design to test Digital Receiver 1st stage (BN)
+--
+-- Created 23-04-2010 by GC
+-- $Author:
+-- Description
+-- Application for Digital Receiver
+-- Includes a (very simple) LVDS receiver
+-- a test pattern generator
+-- first stage (backnode) of the Digita Receiver application
+--
+------------------------------------------------------------------------------
+--
+-- Copyright (C) 2011
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+--
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+-- INAF (Istituto Nazionale di Radioastronomia)
+-- Osservatorio Astrofisico di Arcetri
+-- Largo E. Fermi 5 - 50125 Firenze - Italy
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+-- $Log:
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+USE IEEE.NUMERIC_STD.ALL;
+LIBRARY common_lib, dp_lib;
+LIBRARY test_generator_lib,digital_receiver_lib;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+--USE unb_common_lib.unb_common_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+
+ENTITY node_dr_1st_stage IS
+ PORT (
+ -- mm interface
+ mm_clock : IN STD_LOGIC;
+ mm_reset : IN STD_LOGIC;
+ mm_test_generator_mosi : IN t_mem_mosi;
+ mm_test_generator_miso : OUT t_mem_miso;
+ mm_dr_1st_stage_mosi : IN t_mem_mosi;
+ mm_dr_1st_stage_miso : OUT t_mem_miso;
+ dsp_clk : IN STD_LOGIC;
+ stb_1ms : IN STD_LOGIC;
+ stb_1s : IN STD_LOGIC;
+ test_point : OUT std_logic_vector(2 DOWNTO 0);
+ -- input
+ adc_bi : IN t_slv_8_arr(0 to 3);
+ adc_clk : IN std_logic_vector(0 TO 3);
+ adc_scl : OUT std_logic_vector(0 TO 3);
+ adc_sda : INOUT std_logic_vector(0 TO 3);
+ -- output
+ data_out : OUT t_dp_sosi_arr(0 to 3)
+ );
+END entity node_dr_1st_stage;
+
+architecture str of node_dr_1st_stage is
+
+SIGNAL adc_data : signed(63 DOWNTO 0);
+SIGNAL stage_input : signed(63 DOWNTO 0);
+SIGNAL stage_output : SIGNED(63 DOWNTO 0);
+SIGNAL pps_delayed : STD_LOGIC;
+SIGNAL test_point_1st_stage : std_logic_vector(3 DOWNTO 0);
+
+CONSTANT c_module_delay : INTEGER := 37; -- just to give a value, for now
+
+BEGIN
+adc: ENTITY work.adc_lvds
+ PORT MAP (
+ adc_bi => adc_bi,
+ adc_clk => adc_clk,
+ adc_scl => adc_scl,
+ adc_sda => adc_sda,
+ dsp_clk => dsp_clk,
+ data_out => adc_data
+ );
+
+testgen: ENTITY test_generator_lib.test_generator_mm
+ PORT MAP (
+ mm_clock => mm_clock,
+ mm_reset => mm_reset,
+ mm_mosi => mm_test_generator_mosi,
+ mm_miso => mm_test_generator_miso,
+
+ test_point => test_point(0),
+ dsp_clock => dsp_clk,
+ stb_1s => stb_1s,
+ stb_1ms => stb_1ms,
+
+ data_in => adc_data,
+ data_out => stage_input
+ );
+
+stage: ENTITY work.mms_dr_1st_stage
+ PORT MAP (
+ mm_clock => mm_clock,
+ mm_reset => mm_reset,
+ mm_mosi => mm_dr_1st_stage_mosi,
+ mm_miso => mm_dr_1st_stage_miso,
+
+ test_point => test_point_1st_stage,
+ dsp_clock => dsp_clk,
+-- stb_1s => stb_1s,
+ stb_1ms => stb_1ms,
+
+ data_in => stage_input,
+ data_out => stage_output
+ );
+
+--
+-- delay PPS by amunt fo internal delay in module
+--
+del_pps: ENTITY digrec_lib.pulse_delay_n
+ GENERIC MAP (
+ delay => c_module_delay )
+ PORT MAP (
+ clock => dsp_clk,
+ input => stb_1ms,
+ output => pps_delayed );
+
+ PROCESS(stage_output)
+ BEGIN
+ FOR i IN 0 TO 3 LOOP
+ data_out(i).data <= (OTHERS => '0');
+ data_out(i).data(47 DOWNTO 0) <=
+ std_logic_vector(stage_output(i)(1)(1)) & "0000" &
+ std_logic_vector(stage_output(i)(1)(0)) & "0000" &
+ std_logic_vector(stage_output(i)(0)(1)) & "0000" &
+ std_logic_vector(stage_output(i)(0)(0)) & "0000";
+ data_out(i).valid <= '1';
+ data_out(i).sop <= pps_delayed;
+ END LOOP;
+ END PROCESS;
+
+ test_point(1) <= test_point_1st_stage(0);
+ test_point(2) <= test_point_1st_stage(1);
+
+end architecture;
diff --git a/applications/dig_receiver/designs/dig_receiver_bn/src/vhdl/sopc_dig_receiver_bn.sopc b/applications/dig_receiver/designs/dig_receiver_bn/src/vhdl/sopc_dig_receiver_bn.sopc
new file mode 100644
index 0000000000000000000000000000000000000000..6e1b2ca3c839d7cd2b9ff7acc4903856c902594f
--- /dev/null
+++ b/applications/dig_receiver/designs/dig_receiver_bn/src/vhdl/sopc_dig_receiver_bn.sopc
@@ -0,0 +1,1767 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="sopc_digital_receiver">
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element altpll_0
+ {
+ datum _sortIndex
+ {
+ value = "1";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element jtag_uart_0.avalon_jtag_slave
+ {
+ datum baseAddress
+ {
+ value = "546320";
+ type = "long";
+ }
+ }
+ element avs_eth_0
+ {
+ datum _sortIndex
+ {
+ value = "9";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element altpll_0.c0
+ {
+ datum _clockDomain
+ {
+ value = "mm_clk";
+ type = "String";
+ }
+ }
+ element altpll_0.c1
+ {
+ datum _clockDomain
+ {
+ value = "cal_clk";
+ type = "String";
+ }
+ }
+ element altpll_0.c2
+ {
+ datum _clockDomain
+ {
+ value = "tse_clk_0";
+ type = "String";
+ }
+ }
+ element clk_0
+ {
+ datum _sortIndex
+ {
+ value = "5";
+ type = "int";
+ }
+ }
+ element cpu_0
+ {
+ datum _sortIndex
+ {
+ value = "4";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{output_language=VHDL, output_directory=/home/comore/UniBoard_FP7/UniBoard/trunk/Firmware/designs/dr_1st_chip_stage/build/synth/quartus}";
+ type = "String";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element dp_clk
+ {
+ datum _sortIndex
+ {
+ value = "10";
+ type = "int";
+ }
+ }
+ element eth_10ginst_0
+ {
+ datum _sortIndex
+ {
+ value = "23";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element eth_10ginst_1
+ {
+ datum _sortIndex
+ {
+ value = "24";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element eth_10ginst_2
+ {
+ datum _sortIndex
+ {
+ value = "25";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element cpu_0.jtag_debug_module
+ {
+ datum baseAddress
+ {
+ value = "542720";
+ type = "long";
+ }
+ }
+ element jtag_uart_0
+ {
+ datum _sortIndex
+ {
+ value = "3";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_epcs.mem
+ {
+ datum baseAddress
+ {
+ value = "546240";
+ type = "long";
+ }
+ }
+ element reg_dr_1st_stage.mem
+ {
+ datum baseAddress
+ {
+ value = "544896";
+ type = "long";
+ }
+ }
+ element pio_system_info.mem
+ {
+ datum baseAddress
+ {
+ value = "545280";
+ type = "long";
+ }
+ }
+ element reg_test_generator.mem
+ {
+ datum baseAddress
+ {
+ value = "544768";
+ type = "long";
+ }
+ }
+ element reg_dpmm_ctrl.mem
+ {
+ datum baseAddress
+ {
+ value = "546344";
+ type = "long";
+ }
+ }
+ element eth_10ginst_0.mem
+ {
+ datum baseAddress
+ {
+ value = "0";
+ type = "long";
+ }
+ }
+ element reg_adc_lvds.mem
+ {
+ datum baseAddress
+ {
+ value = "545536";
+ type = "long";
+ }
+ }
+ element eth_10ginst_1.mem
+ {
+ datum baseAddress
+ {
+ value = "262144";
+ type = "long";
+ }
+ }
+ element reg_tr_nonbonded.mem
+ {
+ datum baseAddress
+ {
+ value = "545152";
+ type = "long";
+ }
+ }
+ element reg_dpmm_data.mem
+ {
+ datum baseAddress
+ {
+ value = "546352";
+ type = "long";
+ }
+ }
+ element reg_tr_xaui.mem
+ {
+ datum baseAddress
+ {
+ value = "524288";
+ type = "long";
+ }
+ }
+ element pio_pps.mem
+ {
+ datum baseAddress
+ {
+ value = "546328";
+ type = "long";
+ }
+ }
+ element reg_mesh.mem
+ {
+ datum baseAddress
+ {
+ value = "545024";
+ type = "long";
+ }
+ }
+ element udp_packetizer_st_1.mem
+ {
+ datum baseAddress
+ {
+ value = "545792";
+ type = "long";
+ }
+ }
+ element reg_mmdp_data.mem
+ {
+ datum baseAddress
+ {
+ value = "546368";
+ type = "long";
+ }
+ }
+ element rom_system_info.mem
+ {
+ datum baseAddress
+ {
+ value = "546176";
+ type = "long";
+ }
+ }
+ element eth_10ginst_2.mem
+ {
+ datum baseAddress
+ {
+ value = "393216";
+ type = "long";
+ }
+ }
+ element reg_unb_sens.mem
+ {
+ datum baseAddress
+ {
+ value = "546144";
+ type = "long";
+ }
+ }
+ element reg_dr_2nd_stage.mem
+ {
+ datum baseAddress
+ {
+ value = "545408";
+ type = "long";
+ }
+ }
+ element reg_wdi.mem
+ {
+ datum baseAddress
+ {
+ value = "546336";
+ type = "long";
+ }
+ }
+ element reg_mmdp_ctrl.mem
+ {
+ datum baseAddress
+ {
+ value = "546360";
+ type = "long";
+ }
+ }
+ element reg_remu.mem
+ {
+ datum baseAddress
+ {
+ value = "546208";
+ type = "long";
+ }
+ }
+ element udp_packetizer_st_0.mem
+ {
+ datum baseAddress
+ {
+ value = "545664";
+ type = "long";
+ }
+ }
+ element udp_packetizer_st_2.mem
+ {
+ datum baseAddress
+ {
+ value = "545920";
+ type = "long";
+ }
+ }
+ element avs_eth_0.mms_ram
+ {
+ datum baseAddress
+ {
+ value = "536576";
+ type = "long";
+ }
+ }
+ element avs_eth_0.mms_reg
+ {
+ datum baseAddress
+ {
+ value = "546048";
+ type = "long";
+ }
+ }
+ element avs_eth_0.mms_tse
+ {
+ datum baseAddress
+ {
+ value = "532480";
+ type = "long";
+ }
+ }
+ element onchip_memory2_0
+ {
+ datum _sortIndex
+ {
+ value = "2";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element pio_debug_wave
+ {
+ datum _sortIndex
+ {
+ value = "8";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element pio_pps
+ {
+ datum _sortIndex
+ {
+ value = "15";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element pio_system_info
+ {
+ datum _sortIndex
+ {
+ value = "14";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element pio_wdi
+ {
+ datum _sortIndex
+ {
+ value = "7";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element altpll_0.pll_slave
+ {
+ datum _lockedAddress
+ {
+ value = "0";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "546272";
+ type = "long";
+ }
+ }
+ element reg_adc_lvds
+ {
+ datum _sortIndex
+ {
+ value = "26";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_dpmm_ctrl
+ {
+ datum _sortIndex
+ {
+ value = "19";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_dpmm_data
+ {
+ datum _sortIndex
+ {
+ value = "20";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_dr_1st_stage
+ {
+ datum _sortIndex
+ {
+ value = "28";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_dr_2nd_stage
+ {
+ datum _sortIndex
+ {
+ value = "29";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_epcs
+ {
+ datum _sortIndex
+ {
+ value = "18";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_mesh
+ {
+ datum _sortIndex
+ {
+ value = "30";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_mmdp_ctrl
+ {
+ datum _sortIndex
+ {
+ value = "21";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_mmdp_data
+ {
+ datum _sortIndex
+ {
+ value = "22";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_remu
+ {
+ datum _sortIndex
+ {
+ value = "17";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_test_generator
+ {
+ datum _sortIndex
+ {
+ value = "27";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_tr_nonbonded
+ {
+ datum _sortIndex
+ {
+ value = "31";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_tr_xaui
+ {
+ datum _sortIndex
+ {
+ value = "11";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_unb_sens
+ {
+ datum _sortIndex
+ {
+ value = "12";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_wdi
+ {
+ datum _sortIndex
+ {
+ value = "16";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element rom_system_info
+ {
+ datum _sortIndex
+ {
+ value = "13";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element onchip_memory2_0.s1
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "131072";
+ type = "long";
+ }
+ }
+ element pio_wdi.s1
+ {
+ datum baseAddress
+ {
+ value = "546304";
+ type = "long";
+ }
+ }
+ element pio_debug_wave.s1
+ {
+ datum baseAddress
+ {
+ value = "546288";
+ type = "long";
+ }
+ }
+ element timer_0.s1
+ {
+ datum baseAddress
+ {
+ value = "546112";
+ type = "long";
+ }
+ }
+ element sopc_1st_chip_stage
+ {
+ }
+ element timer_0
+ {
+ datum _sortIndex
+ {
+ value = "6";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element tse_clk
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+ element udp_packetizer_st_0
+ {
+ datum _sortIndex
+ {
+ value = "32";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element udp_packetizer_st_1
+ {
+ datum _sortIndex
+ {
+ value = "33";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element udp_packetizer_st_2
+ {
+ datum _sortIndex
+ {
+ value = "34";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="EP4SGX230KF40C2" />
+ <parameter name="deviceFamily" value="STRATIXIV" />
+ <parameter name="deviceSpeedGrade" value="" />
+ <parameter name="fabricMode" value="SOPC" />
+ <parameter name="generateLegacySim" value="true" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="true" />
+ <parameter name="hdlLanguage" value="VHDL" />
+ <parameter name="maxAdditionalLatency" value="0" />
+ <parameter name="projectName" value="dig_receiver_bn.qpf" />
+ <parameter name="sopcBorderPoints" value="true" />
+ <parameter name="systemHash" value="-76830441742" />
+ <parameter name="timeStamp" value="1445028349883" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <module kind="clock_source" version="11.1" enabled="1" name="clk_0">
+ <parameter name="clockFrequency" value="25000000" />
+ <parameter name="clockFrequencyKnown" value="true" />
+ <parameter name="inputClockFrequency" value="0" />
+ <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <module kind="altera_nios2" version="11.1" enabled="1" name="cpu_0">
+ <parameter name="userDefinedSettings" value="" />
+ <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
+ <parameter name="setting_showUnpublishedSettings" value="false" />
+ <parameter name="setting_showInternalSettings" value="false" />
+ <parameter name="setting_shadowRegisterSets" value="0" />
+ <parameter name="setting_preciseSlaveAccessErrorException" value="false" />
+ <parameter name="setting_preciseIllegalMemAccessException" value="false" />
+ <parameter name="setting_preciseDivisionErrorException" value="false" />
+ <parameter name="setting_performanceCounter" value="false" />
+ <parameter name="setting_perfCounterWidth" value="_32" />
+ <parameter name="setting_interruptControllerType" value="Internal" />
+ <parameter name="setting_illegalMemAccessDetection" value="false" />
+ <parameter name="setting_illegalInstructionsTrap" value="false" />
+ <parameter name="setting_fullWaveformSignals" value="false" />
+ <parameter name="setting_extraExceptionInfo" value="false" />
+ <parameter name="setting_exportPCB" value="false" />
+ <parameter name="setting_debugSimGen" value="false" />
+ <parameter name="setting_clearXBitsLDNonBypass" value="true" />
+ <parameter name="setting_branchPredictionType" value="Automatic" />
+ <parameter name="setting_bit31BypassDCache" value="true" />
+ <parameter name="setting_bigEndian" value="false" />
+ <parameter name="setting_bhtPtrSz" value="_8" />
+ <parameter name="setting_bhtIndexPcOnly" value="false" />
+ <parameter name="setting_avalonDebugPortPresent" value="false" />
+ <parameter name="setting_alwaysEncrypt" value="true" />
+ <parameter name="setting_allowFullAddressRange" value="false" />
+ <parameter name="setting_activateTrace" value="true" />
+ <parameter name="setting_activateTestEndChecker" value="false" />
+ <parameter name="setting_activateMonitors" value="true" />
+ <parameter name="setting_activateModelChecker" value="false" />
+ <parameter name="setting_HDLSimCachesCleared" value="true" />
+ <parameter name="setting_HBreakTest" value="false" />
+ <parameter name="resetSlave" value="onchip_memory2_0.s1" />
+ <parameter name="resetOffset" value="0" />
+ <parameter name="muldiv_multiplierType" value="NoneSmall" />
+ <parameter name="muldiv_divider" value="false" />
+ <parameter name="mpu_useLimit" value="false" />
+ <parameter name="mpu_numOfInstRegion" value="8" />
+ <parameter name="mpu_numOfDataRegion" value="8" />
+ <parameter name="mpu_minInstRegionSize" value="_12" />
+ <parameter name="mpu_minDataRegionSize" value="_12" />
+ <parameter name="mpu_enabled" value="false" />
+ <parameter name="mmu_uitlbNumEntries" value="_4" />
+ <parameter name="mmu_udtlbNumEntries" value="_6" />
+ <parameter name="mmu_tlbPtrSz" value="_7" />
+ <parameter name="mmu_tlbNumWays" value="_16" />
+ <parameter name="mmu_processIDNumBits" value="_8" />
+ <parameter name="mmu_enabled" value="false" />
+ <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
+ <parameter name="mmu_TLBMissExcSlave" value="" />
+ <parameter name="mmu_TLBMissExcOffset" value="0" />
+ <parameter name="manuallyAssignCpuID" value="false" />
+ <parameter name="internalIrqMaskSystemInfo" value="7" />
+ <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='cpu_0.jtag_debug_module' start='0x84800' end='0x85000' /></address-map>]]></parameter>
+ <parameter name="instAddrWidth" value="20" />
+ <parameter name="impl" value="Small" />
+ <parameter name="icache_size" value="_4096" />
+ <parameter name="icache_ramBlockType" value="Automatic" />
+ <parameter name="icache_numTCIM" value="_0" />
+ <parameter name="icache_burstType" value="None" />
+ <parameter name="exceptionSlave" value="onchip_memory2_0.s1" />
+ <parameter name="exceptionOffset" value="32" />
+ <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 1 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 1 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 1 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+ <parameter name="deviceFamilyName" value="Stratix IV" />
+ <parameter name="debug_triggerArming" value="true" />
+ <parameter name="debug_level" value="Level1" />
+ <parameter name="debug_jtagInstanceID" value="0" />
+ <parameter name="debug_embeddedPLL" value="true" />
+ <parameter name="debug_debugReqSignals" value="false" />
+ <parameter name="debug_assignJtagInstanceID" value="false" />
+ <parameter name="debug_OCIOnchipTrace" value="_128" />
+ <parameter name="dcache_size" value="_2048" />
+ <parameter name="dcache_ramBlockType" value="Automatic" />
+ <parameter name="dcache_omitDataMaster" value="false" />
+ <parameter name="dcache_numTCDM" value="_0" />
+ <parameter name="dcache_lineSize" value="_32" />
+ <parameter name="dcache_bursts" value="false" />
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='eth_10ginst_0.mem' start='0x0' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='eth_10ginst_1.mem' start='0x40000' end='0x60000' /><slave name='eth_10ginst_2.mem' start='0x60000' end='0x80000' /><slave name='reg_tr_xaui.mem' start='0x80000' end='0x82000' /><slave name='avs_eth_0.mms_tse' start='0x82000' end='0x83000' /><slave name='avs_eth_0.mms_ram' start='0x83000' end='0x84000' /><slave name='cpu_0.jtag_debug_module' start='0x84800' end='0x85000' /><slave name='reg_test_generator.mem' start='0x85000' end='0x85080' /><slave name='reg_dr_1st_stage.mem' start='0x85080' end='0x85100' /><slave name='reg_mesh.mem' start='0x85100' end='0x85180' /><slave name='reg_tr_nonbonded.mem' start='0x85180' end='0x85200' /><slave name='pio_system_info.mem' start='0x85200' end='0x85280' /><slave name='reg_dr_2nd_stage.mem' start='0x85280' end='0x85300' /><slave name='reg_adc_lvds.mem' start='0x85300' end='0x85380' /><slave name='udp_packetizer_st_0.mem' start='0x85380' end='0x85400' /><slave name='udp_packetizer_st_1.mem' start='0x85400' end='0x85480' /><slave name='udp_packetizer_st_2.mem' start='0x85480' end='0x85500' /><slave name='avs_eth_0.mms_reg' start='0x85500' end='0x85540' /><slave name='timer_0.s1' start='0x85540' end='0x85560' /><slave name='reg_unb_sens.mem' start='0x85560' end='0x85580' /><slave name='rom_system_info.mem' start='0x85580' end='0x855A0' /><slave name='reg_remu.mem' start='0x855A0' end='0x855C0' /><slave name='reg_epcs.mem' start='0x855C0' end='0x855E0' /><slave name='altpll_0.pll_slave' start='0x855E0' end='0x855F0' /><slave name='pio_debug_wave.s1' start='0x855F0' end='0x85600' /><slave name='pio_wdi.s1' start='0x85600' end='0x85610' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x85610' end='0x85618' /><slave name='pio_pps.mem' start='0x85618' end='0x85620' /><slave name='reg_wdi.mem' start='0x85620' end='0x85628' /><slave name='reg_dpmm_ctrl.mem' start='0x85628' end='0x85630' /><slave name='reg_dpmm_data.mem' start='0x85630' end='0x85638' /><slave name='reg_mmdp_ctrl.mem' start='0x85638' end='0x85640' /><slave name='reg_mmdp_data.mem' start='0x85640' end='0x85648' /></address-map>]]></parameter>
+ <parameter name="dataAddrWidth" value="20" />
+ <parameter name="customInstSlavesSystemInfo" value="<info/>" />
+ <parameter name="cpuReset" value="false" />
+ <parameter name="cpuID" value="0" />
+ <parameter name="clockFrequency" value="125000000" />
+ <parameter name="breakSlave">cpu_0.jtag_debug_module</parameter>
+ <parameter name="breakOffset" value="32" />
+ </module>
+ <module
+ kind="altera_avalon_onchip_memory2"
+ version="11.1"
+ enabled="1"
+ name="onchip_memory2_0">
+ <parameter name="allowInSystemMemoryContentEditor" value="false" />
+ <parameter name="autoInitializationFileName" value="onchip_memory2_0" />
+ <parameter name="blockType" value="M144K" />
+ <parameter name="dataWidth" value="32" />
+ <parameter name="deviceFamily" value="Stratix IV" />
+ <parameter name="dualPort" value="false" />
+ <parameter name="initMemContent" value="true" />
+ <parameter name="initializationFileName" value="onchip_memory2_0" />
+ <parameter name="instanceID" value="NONE" />
+ <parameter name="memorySize" value="131072" />
+ <parameter name="readDuringWriteMode" value="DONT_CARE" />
+ <parameter name="simAllowMRAMContentsFile" value="false" />
+ <parameter name="simMemInitOnlyFilename" value="0" />
+ <parameter name="singleClockOperation" value="false" />
+ <parameter name="slave1Latency" value="1" />
+ <parameter name="slave2Latency" value="1" />
+ <parameter name="useNonDefaultInitFile" value="false" />
+ <parameter name="useShallowMemBlocks" value="false" />
+ <parameter name="writable" value="true" />
+ </module>
+ <module
+ kind="altera_avalon_jtag_uart"
+ version="11.1"
+ enabled="1"
+ name="jtag_uart_0">
+ <parameter name="allowMultipleConnections" value="false" />
+ <parameter name="hubInstanceID" value="0" />
+ <parameter name="readBufferDepth" value="64" />
+ <parameter name="readIRQThreshold" value="8" />
+ <parameter name="simInputCharacterStream"><![CDATA[a
+q]]></parameter>
+ <parameter name="simInteractiveOptions">INTERACTIVE_ASCII_OUTPUT</parameter>
+ <parameter name="useRegistersForReadBuffer" value="false" />
+ <parameter name="useRegistersForWriteBuffer" value="false" />
+ <parameter name="useRelativePathForSimFile" value="false" />
+ <parameter name="writeBufferDepth" value="64" />
+ <parameter name="writeIRQThreshold" value="8" />
+ </module>
+ <module kind="altpll" version="11.1" enabled="1" name="altpll_0">
+ <parameter name="HIDDEN_CUSTOM_ELABORATION">altpll_avalon_elaboration</parameter>
+ <parameter name="HIDDEN_CUSTOM_POST_EDIT">altpll_avalon_post_edit</parameter>
+ <parameter name="INTENDED_DEVICE_FAMILY" value="Stratix IV" />
+ <parameter name="WIDTH_CLOCK" value="10" />
+ <parameter name="WIDTH_PHASECOUNTERSELECT" value="" />
+ <parameter name="PRIMARY_CLOCK" value="" />
+ <parameter name="INCLK0_INPUT_FREQUENCY" value="40000" />
+ <parameter name="INCLK1_INPUT_FREQUENCY" value="" />
+ <parameter name="OPERATION_MODE" value="NORMAL" />
+ <parameter name="PLL_TYPE" value="AUTO" />
+ <parameter name="QUALIFY_CONF_DONE" value="" />
+ <parameter name="COMPENSATE_CLOCK" value="CLK0" />
+ <parameter name="SCAN_CHAIN" value="" />
+ <parameter name="GATE_LOCK_SIGNAL" value="" />
+ <parameter name="GATE_LOCK_COUNTER" value="" />
+ <parameter name="LOCK_HIGH" value="" />
+ <parameter name="LOCK_LOW" value="" />
+ <parameter name="VALID_LOCK_MULTIPLIER" value="" />
+ <parameter name="INVALID_LOCK_MULTIPLIER" value="" />
+ <parameter name="SWITCH_OVER_ON_LOSSCLK" value="" />
+ <parameter name="SWITCH_OVER_ON_GATED_LOCK" value="" />
+ <parameter name="ENABLE_SWITCH_OVER_COUNTER" value="" />
+ <parameter name="SKIP_VCO" value="" />
+ <parameter name="SWITCH_OVER_COUNTER" value="" />
+ <parameter name="SWITCH_OVER_TYPE" value="" />
+ <parameter name="FEEDBACK_SOURCE" value="" />
+ <parameter name="BANDWIDTH" value="" />
+ <parameter name="BANDWIDTH_TYPE" value="AUTO" />
+ <parameter name="SPREAD_FREQUENCY" value="" />
+ <parameter name="DOWN_SPREAD" value="" />
+ <parameter name="SELF_RESET_ON_GATED_LOSS_LOCK" value="" />
+ <parameter name="SELF_RESET_ON_LOSS_LOCK" value="" />
+ <parameter name="CLK0_MULTIPLY_BY" value="5" />
+ <parameter name="CLK1_MULTIPLY_BY" value="8" />
+ <parameter name="CLK2_MULTIPLY_BY" value="5" />
+ <parameter name="CLK3_MULTIPLY_BY" value="8" />
+ <parameter name="CLK4_MULTIPLY_BY" value="" />
+ <parameter name="CLK5_MULTIPLY_BY" value="" />
+ <parameter name="CLK6_MULTIPLY_BY" value="" />
+ <parameter name="CLK7_MULTIPLY_BY" value="" />
+ <parameter name="CLK8_MULTIPLY_BY" value="" />
+ <parameter name="CLK9_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK0_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK1_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK2_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK3_MULTIPLY_BY" value="" />
+ <parameter name="CLK0_DIVIDE_BY" value="1" />
+ <parameter name="CLK1_DIVIDE_BY" value="5" />
+ <parameter name="CLK2_DIVIDE_BY" value="1" />
+ <parameter name="CLK3_DIVIDE_BY" value="1" />
+ <parameter name="CLK4_DIVIDE_BY" value="" />
+ <parameter name="CLK5_DIVIDE_BY" value="" />
+ <parameter name="CLK6_DIVIDE_BY" value="" />
+ <parameter name="CLK7_DIVIDE_BY" value="" />
+ <parameter name="CLK8_DIVIDE_BY" value="" />
+ <parameter name="CLK9_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK0_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK1_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK2_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK3_DIVIDE_BY" value="" />
+ <parameter name="CLK0_PHASE_SHIFT" value="0" />
+ <parameter name="CLK1_PHASE_SHIFT" value="0" />
+ <parameter name="CLK2_PHASE_SHIFT" value="0" />
+ <parameter name="CLK3_PHASE_SHIFT" value="0" />
+ <parameter name="CLK4_PHASE_SHIFT" value="" />
+ <parameter name="CLK5_PHASE_SHIFT" value="" />
+ <parameter name="CLK6_PHASE_SHIFT" value="" />
+ <parameter name="CLK7_PHASE_SHIFT" value="" />
+ <parameter name="CLK8_PHASE_SHIFT" value="" />
+ <parameter name="CLK9_PHASE_SHIFT" value="" />
+ <parameter name="EXTCLK0_PHASE_SHIFT" value="" />
+ <parameter name="EXTCLK1_PHASE_SHIFT" value="" />
+ <parameter name="EXTCLK2_PHASE_SHIFT" value="" />
+ <parameter name="EXTCLK3_PHASE_SHIFT" value="" />
+ <parameter name="CLK0_DUTY_CYCLE" value="50" />
+ <parameter name="CLK1_DUTY_CYCLE" value="50" />
+ <parameter name="CLK2_DUTY_CYCLE" value="50" />
+ <parameter name="CLK3_DUTY_CYCLE" value="50" />
+ <parameter name="CLK4_DUTY_CYCLE" value="" />
+ <parameter name="CLK5_DUTY_CYCLE" value="" />
+ <parameter name="CLK6_DUTY_CYCLE" value="" />
+ <parameter name="CLK7_DUTY_CYCLE" value="" />
+ <parameter name="CLK8_DUTY_CYCLE" value="" />
+ <parameter name="CLK9_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK0_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK1_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK2_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK3_DUTY_CYCLE" value="" />
+ <parameter name="PORT_clkena0" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena1" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena2" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena3" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena4" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena5" value="PORT_UNUSED" />
+ <parameter name="PORT_extclkena0" value="" />
+ <parameter name="PORT_extclkena1" value="" />
+ <parameter name="PORT_extclkena2" value="" />
+ <parameter name="PORT_extclkena3" value="" />
+ <parameter name="PORT_extclk0" value="" />
+ <parameter name="PORT_extclk1" value="" />
+ <parameter name="PORT_extclk2" value="" />
+ <parameter name="PORT_extclk3" value="" />
+ <parameter name="PORT_CLKBAD0" value="PORT_UNUSED" />
+ <parameter name="PORT_CLKBAD1" value="PORT_UNUSED" />
+ <parameter name="PORT_clk0" value="PORT_USED" />
+ <parameter name="PORT_clk1" value="PORT_USED" />
+ <parameter name="PORT_clk2" value="PORT_USED" />
+ <parameter name="PORT_clk3" value="PORT_USED" />
+ <parameter name="PORT_clk4" value="PORT_UNUSED" />
+ <parameter name="PORT_clk5" value="PORT_UNUSED" />
+ <parameter name="PORT_clk6" value="PORT_UNUSED" />
+ <parameter name="PORT_clk7" value="PORT_UNUSED" />
+ <parameter name="PORT_clk8" value="PORT_UNUSED" />
+ <parameter name="PORT_clk9" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANDATA" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANDATAOUT" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANDONE" value="PORT_UNUSED" />
+ <parameter name="PORT_SCLKOUT1" value="" />
+ <parameter name="PORT_SCLKOUT0" value="" />
+ <parameter name="PORT_ACTIVECLOCK" value="PORT_UNUSED" />
+ <parameter name="PORT_CLKLOSS" value="PORT_UNUSED" />
+ <parameter name="PORT_INCLK1" value="PORT_UNUSED" />
+ <parameter name="PORT_INCLK0" value="PORT_USED" />
+ <parameter name="PORT_FBIN" value="PORT_UNUSED" />
+ <parameter name="PORT_PLLENA" value="PORT_UNUSED" />
+ <parameter name="PORT_CLKSWITCH" value="PORT_UNUSED" />
+ <parameter name="PORT_ARESET" value="PORT_UNUSED" />
+ <parameter name="PORT_PFDENA" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANCLK" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANACLR" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANREAD" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANWRITE" value="PORT_UNUSED" />
+ <parameter name="PORT_ENABLE0" value="" />
+ <parameter name="PORT_ENABLE1" value="" />
+ <parameter name="PORT_LOCKED" value="PORT_USED" />
+ <parameter name="PORT_CONFIGUPDATE" value="PORT_UNUSED" />
+ <parameter name="PORT_FBOUT" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASEDONE" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASESTEP" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASEUPDOWN" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANCLKENA" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASECOUNTERSELECT" value="PORT_UNUSED" />
+ <parameter name="PORT_VCOOVERRANGE" value="" />
+ <parameter name="PORT_VCOUNDERRANGE" value="" />
+ <parameter name="DPA_MULTIPLY_BY" value="" />
+ <parameter name="DPA_DIVIDE_BY" value="" />
+ <parameter name="DPA_DIVIDER" value="" />
+ <parameter name="VCO_MULTIPLY_BY" value="" />
+ <parameter name="VCO_DIVIDE_BY" value="" />
+ <parameter name="SCLKOUT0_PHASE_SHIFT" value="" />
+ <parameter name="SCLKOUT1_PHASE_SHIFT" value="" />
+ <parameter name="VCO_FREQUENCY_CONTROL" value="" />
+ <parameter name="VCO_PHASE_SHIFT_STEP" value="" />
+ <parameter name="USING_FBMIMICBIDIR_PORT" value="OFF" />
+ <parameter name="SCAN_CHAIN_MIF_FILE" value="" />
+ <parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
+ <parameter name="HIDDEN_CONSTANTS">CT#CLK2_DIVIDE_BY 1 CT#PORT_clk9 PORT_UNUSED CT#PORT_clk8 PORT_UNUSED CT#PORT_clk7 PORT_UNUSED CT#PORT_clk6 PORT_UNUSED CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_USED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 1 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT 0 CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 10 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 8 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 40000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_FBOUT PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 5 CT#INTENDED_DEVICE_FAMILY {Stratix IV} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 5 CT#CLK3_MULTIPLY_BY 8 CT#USING_FBMIMICBIDIR_PORT OFF CT#PORT_LOCKED PORT_USED</parameter>
+ <parameter name="HIDDEN_PRIVATES">PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 25.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#OUTPUT_FREQ_UNIT3 MHz PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK3 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#LVDS_PHASE_SHIFT_UNIT3 deg PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#OUTPUT_FREQ_MODE3 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ3 200.00000000 PT#OUTPUT_FREQ2 125.00000000 PT#OUTPUT_FREQ1 40.00000000 PT#OUTPUT_FREQ0 125.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT3 0.00000000 PT#PHASE_SHIFT2 0.00000000 PT#DIV_FACTOR3 1 PT#PHASE_SHIFT1 0.00000000 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE3 200.000000 PT#EFF_OUTPUT_FREQ_VALUE2 125.000000 PT#EFF_OUTPUT_FREQ_VALUE1 40.000000 PT#EFF_OUTPUT_FREQ_VALUE0 125.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK3 1 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT3 deg PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR3 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE3 50.00000000 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {Stratix IV} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1256297171721465.mif PT#ACTIVECLK_CHECK 0</parameter>
+ <parameter name="HIDDEN_USED_PORTS">UP#locked used UP#c3 used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used</parameter>
+ <parameter name="HIDDEN_IS_NUMERIC">IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK3_DIVIDE_BY 1 IN#CLK1_MULTIPLY_BY 1 IN#CLK3_DUTY_CYCLE 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR3 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#CLK3_MULTIPLY_BY 1 IN#MULT_FACTOR3 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1</parameter>
+ <parameter name="HIDDEN_MF_PORTS">MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1</parameter>
+ <parameter name="HIDDEN_IF_PORTS">IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#c3 {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}</parameter>
+ <parameter name="HIDDEN_IS_FIRST_EDIT" value="0" />
+ <parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE" value="25000000" />
+ <parameter name="AUTO_DEVICE_FAMILY" value="Stratix IV" />
+ </module>
+ <module
+ kind="altera_avalon_pio"
+ version="11.1"
+ enabled="1"
+ name="pio_debug_wave">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="125000000" />
+ <parameter name="direction" value="Output" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="32" />
+ </module>
+ <module kind="altera_avalon_timer" version="11.1" enabled="1" name="timer_0">
+ <parameter name="alwaysRun" value="true" />
+ <parameter name="counterSize" value="32" />
+ <parameter name="fixedPeriod" value="true" />
+ <parameter name="period" value="1" />
+ <parameter name="periodUnits" value="MSEC" />
+ <parameter name="resetOutput" value="false" />
+ <parameter name="snapshot" value="false" />
+ <parameter name="systemFrequency" value="125000000" />
+ <parameter name="timeoutPulseOutput" value="false" />
+ <parameter name="timerPreset">SIMPLE_PERIODIC_INTERRUPT</parameter>
+ </module>
+ <module kind="altera_avalon_pio" version="11.1" enabled="1" name="pio_wdi">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="125000000" />
+ <parameter name="direction" value="Output" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="1" />
+ </module>
+ <module kind="avs_eth_coe" version="1.0" enabled="1" name="avs_eth_0">
+ <parameter name="AUTO_MM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_test_generator">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_dr_1st_stage">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_mesh">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_tr_nonbonded">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module kind="clock_source" version="11.1" enabled="1" name="dp_clk">
+ <parameter name="clockFrequency" value="200000000" />
+ <parameter name="clockFrequencyKnown" value="true" />
+ <parameter name="inputClockFrequency" value="0" />
+ <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <module kind="clock_source" version="11.1" enabled="1" name="tse_clk">
+ <parameter name="clockFrequency" value="50000000" />
+ <parameter name="clockFrequencyKnown" value="true" />
+ <parameter name="inputClockFrequency" value="0" />
+ <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <module
+ kind="avs_common_mm_readlatency0"
+ version="1.0"
+ enabled="1"
+ name="eth_10ginst_0">
+ <parameter name="g_adr_w" value="15" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module
+ kind="avs_common_mm_readlatency0"
+ version="1.0"
+ enabled="1"
+ name="reg_tr_xaui">
+ <parameter name="g_adr_w" value="11" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_unb_sens">
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="rom_system_info">
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="pio_system_info">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="pio_pps">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_wdi">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_remu">
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_epcs">
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_dpmm_ctrl">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_dpmm_data">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_mmdp_ctrl">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_mmdp_data">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_dr_2nd_stage">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module
+ kind="avs_common_mm_readlatency0"
+ version="1.0"
+ enabled="1"
+ name="eth_10ginst_1">
+ <parameter name="g_adr_w" value="15" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module
+ kind="avs_common_mm_readlatency0"
+ version="1.0"
+ enabled="1"
+ name="eth_10ginst_2">
+ <parameter name="g_adr_w" value="15" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_adc_lvds">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="udp_packetizer_st_0">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="udp_packetizer_st_1">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="udp_packetizer_st_2">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.instruction_master"
+ end="cpu_0.jtag_debug_module">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00084800" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="cpu_0.jtag_debug_module">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00084800" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.instruction_master"
+ end="onchip_memory2_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00020000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="onchip_memory2_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00020000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="jtag_uart_0.avalon_jtag_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00085610" />
+ </connection>
+ <connection
+ kind="interrupt"
+ version="11.1"
+ start="cpu_0.d_irq"
+ end="jtag_uart_0.irq">
+ <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="altpll_0.pll_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x000855e0" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="cpu_0.clk" />
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="jtag_uart_0.clk" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="altpll_0.inclk_interface" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="pio_debug_wave.clk" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="pio_debug_wave.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x000855f0" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="timer_0.clk" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="timer_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00085540" />
+ </connection>
+ <connection kind="interrupt" version="11.1" start="cpu_0.d_irq" end="timer_0.irq">
+ <parameter name="irqNumber" value="1" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="pio_wdi.clk" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="pio_wdi.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00085600" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="onchip_memory2_0.clk1" />
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="avs_eth_0.mm" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="avs_eth_0.mms_tse">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00082000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="avs_eth_0.mms_reg">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00085500" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="avs_eth_0.mms_ram">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00083000" />
+ </connection>
+ <connection
+ kind="interrupt"
+ version="11.1"
+ start="cpu_0.d_irq"
+ end="avs_eth_0.interrupt">
+ <parameter name="irqNumber" value="2" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_test_generator.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_test_generator.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00085000" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_dr_1st_stage.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_dr_1st_stage.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00085080" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="reg_mesh.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_mesh.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00085100" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_tr_nonbonded.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_tr_nonbonded.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00085180" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="tse_clk.clk"
+ end="eth_10ginst_0.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="eth_10ginst_0.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0000" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="tse_clk.clk"
+ end="reg_tr_xaui.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_tr_xaui.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00080000" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="tse_clk.clk"
+ end="reg_unb_sens.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_unb_sens.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00085560" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="tse_clk.clk"
+ end="rom_system_info.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="rom_system_info.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00085580" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="tse_clk.clk"
+ end="pio_system_info.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="pio_system_info.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00085200" />
+ </connection>
+ <connection kind="clock" version="11.1" start="tse_clk.clk" end="pio_pps.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="pio_pps.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00085618" />
+ </connection>
+ <connection kind="clock" version="11.1" start="tse_clk.clk" end="reg_wdi.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_wdi.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00085620" />
+ </connection>
+ <connection kind="clock" version="11.1" start="tse_clk.clk" end="reg_remu.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_remu.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x000855a0" />
+ </connection>
+ <connection kind="clock" version="11.1" start="tse_clk.clk" end="reg_epcs.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_epcs.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x000855c0" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="tse_clk.clk"
+ end="reg_dpmm_ctrl.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_dpmm_ctrl.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00085628" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="tse_clk.clk"
+ end="reg_dpmm_data.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_dpmm_data.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00085630" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="tse_clk.clk"
+ end="reg_mmdp_ctrl.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_mmdp_ctrl.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00085638" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="tse_clk.clk"
+ end="reg_mmdp_data.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_mmdp_data.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00085640" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="tse_clk.clk"
+ end="reg_dr_2nd_stage.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_dr_2nd_stage.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00085280" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="tse_clk.clk"
+ end="eth_10ginst_1.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="eth_10ginst_1.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00040000" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="tse_clk.clk"
+ end="eth_10ginst_2.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="eth_10ginst_2.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00060000" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="tse_clk.clk"
+ end="reg_adc_lvds.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_adc_lvds.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00085300" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="tse_clk.clk"
+ end="udp_packetizer_st_0.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="udp_packetizer_st_0.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00085380" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="tse_clk.clk"
+ end="udp_packetizer_st_1.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="udp_packetizer_st_1.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00085400" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="tse_clk.clk"
+ end="udp_packetizer_st_2.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="udp_packetizer_st_2.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00085480" />
+ </connection>
+</system>