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RTSD
HDL
Commits
c000bce3
Commit
c000bce3
authored
2 years ago
by
Eric Kooistra
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Now dp_complex_add also pipelines all sosi fields, no need for external bypass.
parent
16921d35
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1 merge request
!309
Resolve L2SDP-903
Changes
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applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_remote.vhd
+13
-24
13 additions, 24 deletions
...s/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_remote.vhd
with
13 additions
and
24 deletions
applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_remote.vhd
+
13
−
24
View file @
c000bce3
...
...
@@ -67,18 +67,16 @@ ARCHITECTURE str OF sdp_beamformer_remote IS
CONSTANT
c_data_w
:
NATURAL
:
=
c_nof_complex
*
c_sdp_W_beamlet_sum
;
CONSTANT
c_block_size
:
NATURAL
:
=
c_sdp_S_sub_bf
*
c_sdp_N_pol_bf
;
CONSTANT
c_fifo_size
:
NATURAL
:
=
2
**
ceil_log2
((
c_block_size
*
9
)
/
16
);
-- 9/16 = 36/64, 1 block of 64 bit words rounded to the next power of 2 = 1024.
CONSTANT
c_complex_adder_latency
:
NATURAL
:
=
ceil_log2
(
c_dual
);
SIGNAL
dispatch_sosi_arr
:
t_dp_sosi_arr
(
c_dual
-1
DOWNTO
0
)
:
=
(
OTHERS
=>
c_dp_sosi_rst
);
-- 1 for local, 1 for remote.
SIGNAL
dp_fifo_sosi
:
t_dp_sosi
:
=
c_dp_sosi_rst
;
SIGNAL
dp_fifo_siso
:
t_dp_siso
:
=
c_dp_siso_rdy
;
SIGNAL
beamlets_data_sosi_arr
:
t_dp_sosi_arr
(
c_dual
-1
DOWNTO
0
)
:
=
(
OTHERS
=>
c_dp_sosi_rst
);
SIGNAL
beamlets_sosi_arr
:
t_dp_sosi_arr
(
c_dual
-1
DOWNTO
0
)
:
=
(
OTHERS
=>
c_dp_sosi_rst
);
SIGNAL
pipelined_beamlets_sosi
:
t_dp_sosi
:
=
c_dp_sosi_rst
;
SIGNAL
i_bf_sum_sosi
:
t_dp_sosi
:
=
c_dp_sosi_rst
;
SIGNAL
bf_sum_data_sosi
:
t_dp_sosi
:
=
c_dp_sosi_rst
;
BEGIN
BEGIN
-- repacking beamlets re/im to data field.
p_wire_local_bf_sosi
:
PROCESS
(
local_bf_sosi
)
...
...
@@ -182,22 +180,9 @@ BEGIN
beamlets_sosi_arr
(
1
)
.
im
<=
RESIZE_DP_DSP_DATA
(
beamlets_data_sosi_arr
(
1
)
.
data
(
c_data_w
-1
DOWNTO
c_sdp_W_beamlet_sum
));
END
PROCESS
;
---------------------------------------------------------------
-- DP PIPELINE IN_SOSI FIELDS
---------------------------------------------------------------
u_pipeline
:
ENTITY
dp_lib
.
dp_pipeline
GENERIC
MAP
(
g_pipeline
=>
c_complex_adder_latency
)
PORT
MAP
(
rst
=>
dp_rst
,
clk
=>
dp_clk
,
snk_in
=>
beamlets_sosi_arr
(
0
),
src_out
=>
pipelined_beamlets_sosi
);
---------------------------------------------------------------
-- ADD
-- ADD
local + remote
---------------------------------------------------------------
u_dp_complex_add
:
ENTITY
dp_lib
.
dp_complex_add
GENERIC
MAP
(
...
...
@@ -212,18 +197,22 @@ BEGIN
src_out
=>
i_bf_sum_sosi
);
---------------------------------------------------------------
--
Repack 36b to 64b
--
Local output
---------------------------------------------------------------
-- repacking bf_sum re/im to data field and combine with pipelined_beamlets_sosi.
p_wire_bf_sum_sosi
:
PROCESS
(
pipelined_beamlets_sosi
,
i_bf_sum_sosi
)
bf_sum_sosi
<=
i_bf_sum_sosi
;
---------------------------------------------------------------
-- Ring output: Repack 36b to 64b
---------------------------------------------------------------
-- repacking bf_sum re/im to data field
p_wire_bf_sum_sosi
:
PROCESS
(
i_bf_sum_sosi
)
BEGIN
bf_sum_data_sosi
<=
pipelined_beamlets_sosi
;
-- To preserve sosi control signals as dp_complex_add removes them.
bf_sum_sosi
<=
pipelined_beamlets_sosi
;
-- To preserve sosi control signals as dp_complex_add removes them.
bf_sum_data_sosi
<=
i_bf_sum_sosi
;
bf_sum_data_sosi
.
data
(
c_sdp_W_beamlet_sum
-1
DOWNTO
0
)
<=
i_bf_sum_sosi
.
re
(
c_sdp_W_beamlet_sum
-1
DOWNTO
0
);
bf_sum_data_sosi
.
data
(
c_data_w
-1
DOWNTO
c_sdp_W_beamlet_sum
)
<=
i_bf_sum_sosi
.
im
(
c_sdp_W_beamlet_sum
-1
DOWNTO
0
);
bf_sum_sosi
.
re
<=
RESIZE_DP_DSP_DATA
(
i_bf_sum_sosi
.
re
(
c_sdp_W_beamlet_sum
-1
DOWNTO
0
));
bf_sum_sosi
.
im
<=
RESIZE_DP_DSP_DATA
(
i_bf_sum_sosi
.
im
(
c_sdp_W_beamlet_sum
-1
DOWNTO
0
));
END
PROCESS
;
u_dp_repack_data_local
:
ENTITY
dp_lib
.
dp_repack_data
...
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