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Commit be5c8941 authored by Eric Kooistra's avatar Eric Kooistra
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Merge branch 'L2SDP-463' into 'master' 

updated yaml file for unb2c_minimal and unb2c_boad

Closes L2SDP-463

See merge request desp/hdl!139
parents 34254fac 008e90f3
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1 merge request!139updated yaml file for unb2c_minimal and unb2c_boad
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boards/uniboard2c/designs/unb2c_minimal/unb2c_minimal.fpga.yaml
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− 35
View file @ be5c8941
...@@ -4,44 +4,56 @@ schema_type : fpga ...@@ -4,44 +4,56 @@ schema_type : fpga
hdl_library_name: unb2c_minimal hdl_library_name: unb2c_minimal
fpga_name : unb2c_minimal fpga_name : unb2c_minimal
fpga_description: "unb2c_minimal system" fpga_description: "FPGA design unb2c_minimal"
peripherals: peripherals:
- peripheral_name: unb2c_board/unb2c #############################################################################
slave_port_names: # Factory / minimal (from ctrl_unb2c_board.vhd)
- rom_system_info #############################################################################
- pio_system_info - peripheral_name: unb2c_board/system_info
- pio_wdi lock_base_address: 0x10000
- reg_wdi mm_port_names:
- reg_fpga_temp_sens - ROM_SYSTEM_INFO
- reg_fpga_voltage_sens - PIO_SYSTEM_INFO
- ram_scrap
parameter_overrides: - peripheral_name: unb2c_board/wdi
- { name : g_sim, value: FALSE } mm_port_names:
- { name : g_clk_freq, value: 125E6 } - REG_WDI
- { name : g_temp_high, value: 85 }
- peripheral_name: unb2c_board/unb2_fpga_sens
lock_base_address: 0x0 mm_port_names:
lock_base_address: 0x4000 - REG_FPGA_TEMP_SENS
- REG_FPGA_VOLTAGE_SENS
- peripheral_name: eth/eth1g
slave_port_names: - peripheral_name: unb2c_board/ram_scrap
- avs_eth_0_tse mm_port_names:
- avs_eth_0_reg - RAM_SCRAP
- avs_eth_0_ram
- peripheral_name: eth/eth
mm_port_names:
- AVS_ETH_0_TSE
- AVS_ETH_0_REG
- AVS_ETH_0_RAM
- peripheral_name: ppsh/ppsh - peripheral_name: ppsh/ppsh
slave_port_names: mm_port_names:
- pio_pps - PIO_PPS
- peripheral_name: epcs/epcs - peripheral_name: epcs/epcs
slave_port_names: mm_port_names:
- reg_epcs - REG_EPCS
- reg_dpmm_ctrl
- reg_dpmm_data - peripheral_name: dp/dpmm
- reg_mmdp_ctrl mm_port_names:
- reg_mmdp_data - REG_DPMM_CTRL
parameter_overrides: - REG_DPMM_DATA
- { name : g_sim_flash_model, value: FALSE }
- peripheral_name: dp/mmdp
mm_port_names:
- REG_MMDP_CTRL
- REG_MMDP_DATA
- peripheral_name: remu/remu - peripheral_name: remu/remu
slave_port_names: mm_port_names:
- reg_remu - REG_REMU
boards/uniboard2c/libraries/unb2c_board/unb2c_board.peripheral.yaml
+ 158
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View file @ be5c8941
---
schema_name: args schema_name: args
schema_version: 1.0 schema_version: 1.0
schema_type: peripheral schema_type: peripheral
hdl_library_name : unb2c_board hdl_library_name: unb2c_board # ctrl_unb2c_board.vhd
hdl_library_description: " This is the description for the unb2c_board package " hdl_library_description: "Peripherals in unb2c_board."
# <peripheral_group>_<peripheral_name>_<slave_name>_<slave_type>
peripherals: peripherals:
- peripheral_name: ram_scrap # pi_ram_scrap.py
- peripheral_name: unb2c peripheral_description: ""
parameters: mm_ports:
- { name: g_sim, value: FALSE } # MM port for common_ram_r_w.vhd
- { name: g_clk_freq, value: c_unb2c_board_mm_clk_freq_125M } - mm_port_name: RAM_SCRAP
- { name: g_temp_high, value: 85 } mm_port_type: RAM
mm_port_description: "One memory mapped block RAM for MM access test purposes."
slave_ports:
# rom_system_info
- slave_name : rom_system
slave_type : REG
fields: fields:
- - field_name : info - - field_name: rw_data
access_mode : RO field_description: "Void data"
number_of_fields: 512
address_offset: 0x0 address_offset: 0x0
number_of_fields: 8192 access_mode: RW
field_description: |
"address place for rom_system_info" - peripheral_name: system_info # pi_system_info.py
slave_description: " rom_info " peripheral_description: ""
mm_ports:
# reg_system_info # MM port for mms_unb2c_board_system_info.vhd / common_rom.vhd
- slave_name : system - mm_port_name: ROM_SYSTEM_INFO # for c_rom_version = 1 in ctrl_unb2c_board.vhd
slave_type : REG #- mm_port_name: ROM_SYSTEM_INFO_V2 # for c_rom_version = 2 in ctrl_unb2c_board.vhd
mm_port_type: RAM
mm_port_description: "Memory that stores the MM map system info of the mmap file."
fields: fields:
- - field_name : info - - field_name: ro_data
access_mode : RO field_description: "FPGA info memory map data"
number_of_fields: 32768 # c_rom_addr_w in mms_unb2c_board_system_info
address_offset: 0x0 address_offset: 0x0
number_of_fields: 32 mm_width: 32
field_description: | user_width: 8
"address place for reg_system_info" radix: char8
slave_description: " reg_info " access_mode: RO
# actual hdl name: unb2c_board_wdi_reg # MM port for mms_unb2c_board_system_info.vhd / unb2c_board_system_info_reg.vhd
- slave_name : ctrl - mm_port_name: PIO_SYSTEM_INFO
slave_type : REG mm_port_type: REG
mm_port_description: "FPGA design name, design note, version and location index info."
fields: fields:
- - field_name : nios_reset # All registers in one array
width : 32 #- - field_name: info
access_mode : WO # field_description: "FPGA info register, see pi_system_info.py for field details."
address_offset : 0x0 # access_mode: RO
number_of_fields: 4 # address_offset: 0x0
field_description: " Reset done by nios " # number_of_fields: 32
slave_description: "Reset register, for nios "
# actual hdl name: unb2c_board_wdi_reg # Each field specified
- slave_name : wdi - - field_name: info
slave_type : REG field_description: "Info"
address_offset: 0x0
bit_offset: 0
mm_width: 32
access_mode: RO
- "info": # field_group
- field_name: gn_index
field_description: "Global node index, unb2 FPGA id = gn_index % 4, unb2 backplane id = gn_index // 4"
address_offset: 0x0
bit_offset: 0
mm_width: 8
access_mode: RO
- field_name: hw_version
field_description: "UniBoard2 hardware (HW) version."
address_offset: 0x0
bit_offset: 8
mm_width: 2
access_mode: RO
- field_name: cs_sim
field_description: "0 when running on HW, 1 when running in simulation."
address_offset: 0x0
bit_offset: 10
mm_width: 1
access_mode: RO
- field_name: fw_version_major
field_description: "FPGA Firmware (FW) version major number, not used use version stamp instead."
address_offset: 0x0
bit_offset: 16
mm_width: 4
access_mode: RO
- field_name: fw_version_minor
field_description: "FPGA Firmware (FW) version minor number, not used use version stamp instead."
address_offset: 0x0
bit_offset: 20
mm_width: 4
access_mode: RO
- field_name: rom_version
field_description: "Version of the mmap schema in ROM_SYSTEM_INFO."
address_offset: 0x0
bit_offset: 24
mm_width: 3
access_mode: RO
- field_name: technology
field_description: "FPGA technology"
address_offset: 0x0
bit_offset: 27
mm_width: 5
access_mode: RO
- - field_name: use_phy
field_description: "PHY interfaces that are active in the FPGA, not used."
address_offset: 0x4
mm_width: 8
access_mode: RO
- - field_name: design_name
field_description: "FPGA FW design name string."
number_of_fields: 52
address_offset: 0x8
mm_width: 32
user_width: 8
radix: char8
access_mode: RO
- - field_name: stamp_date
field_description: "FPGA FW compile date string."
access_mode: RO
address_offset: 0x3C
number_of_fields: 1
- - field_name: stamp_time
field_description: "FPGA FW compile time string."
number_of_fields: 1
address_offset: 0x40
access_mode: RO
- - field_name: stamp_commit
field_description: "FPGA FW commit hash string."
number_of_fields: 3
address_offset: 0x44
access_mode: RO
- - field_name: design_note
field_description: "FPGA FW design note string."
number_of_fields: 52
address_offset: 0x50
mm_width: 32
user_width: 8
radix: char8
access_mode: RO
- peripheral_name: wdi # pi_wdi.py
peripheral_description: ""
mm_ports:
# MM port for unb2c_board_wdi_reg.vhd
- mm_port_name: REG_WDI
mm_port_type: REG
mm_port_description: "Reset register, if the right value is provided the factory image will be reloaded in the FPGA."
fields: fields:
- - field_name : reset_word - - field_name: wdi_override
access_mode : WO field_description: "Write value 0xB007FAC7 = 'Boot factory' to disable the watchdog interrupt (WDI), to cause an FPGA image reload."
address_offset: 0x0 address_offset: 0x0
field_description: " Only the value 0xB007FAC7 'Boot factory' will result in a reset " access_mode: WO
slave_description: "Reset register, if the right value is provided the factory image will be reloaded "
- slave_name : fpga_temp - peripheral_name: unb2_fpga_sens
slave_type : REG peripheral_description: ""
mm_ports:
# MM ports for mms_unb2c_fpga_sens.vhd / unb2c_fpga_sens_reg.vhd
- mm_port_name: REG_FPGA_TEMP_SENS # pi_unb_fpga_sens.py
mm_port_type: REG
mm_port_description: |
"FPGA temperature = (AxC)/1024 - B (where A=708; B=273; C=adc value), see page 10 in
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_alttemp_sense.pdf"
fields: fields:
- - field_name : temp - - field_name: temp
width : 32 field_description: "Raw data"
access_mode : RO
address_offset: 0x00
number_of_fields: 1 number_of_fields: 1
field_description: "" address_offset: 0x0
slave_description: " " access_mode: RO
- slave_name : fpga_voltage
slave_type : REG - mm_port_name: REG_FPGA_VOLTAGE_SENS # pi_unb_fpga_voltagesens.py
fields: mm_port_type: REG
- - field_name : voltage mm_port_description: "Not used, FPGA voltages are monitored via DC-DC converter power supply volages"
width : 32
access_mode : RO
address_offset: 0x00
number_of_fields: 6
field_description: ""
slave_description: " "
- slave_name : scrap_ram
slave_type : RAM
fields: fields:
- - field_name: data - - field_name: voltages
width : 32 field_description: "Not used"
access_mode: RW number_of_fields: 6
address_offset: 0x00 address_offset: 0x0
number_of_fields: 128 access_mode: RO
field_description: " "
slave_description: " "
peripheral_description: |
""
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