updated yaml file for unb2c_minimal and unb2c_boad

boards/uniboard2c/designs/unb2c_minimal/unb2c_minimal.fpga.yaml

@@ -4,44 +4,56 @@ schema_type   : fpga
 
 hdl_library_name: unb2c_minimal
 fpga_name       : unb2c_minimal
-fpga_description: "unb2c_minimal system"
+fpga_description: "FPGA design unb2c_minimal"
 
 peripherals:
-  - peripheral_name: unb2c_board/unb2c
-    slave_port_names:
-      - rom_system_info
-      - pio_system_info
-      - pio_wdi
-      - reg_wdi
-      - reg_fpga_temp_sens
-      - reg_fpga_voltage_sens
-      - ram_scrap
-    parameter_overrides:
-      - { name : g_sim,       value: FALSE }
-      - { name : g_clk_freq,  value: 125E6 }
-      - { name : g_temp_high, value: 85 }
-
-    lock_base_address: 0x0
-    lock_base_address: 0x4000
-
-  - peripheral_name: eth/eth1g
-    slave_port_names:
-      - avs_eth_0_tse
-      - avs_eth_0_reg
-      - avs_eth_0_ram
+  #############################################################################
+  # Factory / minimal (from ctrl_unb2c_board.vhd)
+  #############################################################################
+  - peripheral_name: unb2c_board/system_info
+    lock_base_address: 0x10000
+    mm_port_names:
+      - ROM_SYSTEM_INFO
+      - PIO_SYSTEM_INFO
+
+  - peripheral_name: unb2c_board/wdi
+    mm_port_names:
+      - REG_WDI
+
+  - peripheral_name: unb2c_board/unb2_fpga_sens
+    mm_port_names:
+      - REG_FPGA_TEMP_SENS
+      - REG_FPGA_VOLTAGE_SENS
+
+  - peripheral_name: unb2c_board/ram_scrap
+    mm_port_names:
+      - RAM_SCRAP
+
+  - peripheral_name: eth/eth
+    mm_port_names:
+      - AVS_ETH_0_TSE
+      - AVS_ETH_0_REG
+      - AVS_ETH_0_RAM
+      
   - peripheral_name: ppsh/ppsh
-    slave_port_names:
-      - pio_pps
+    mm_port_names:
+      - PIO_PPS
+      
   - peripheral_name: epcs/epcs
-    slave_port_names:
-      - reg_epcs
-      - reg_dpmm_ctrl
-      - reg_dpmm_data
-      - reg_mmdp_ctrl
-      - reg_mmdp_data
-    parameter_overrides:
-      - { name : g_sim_flash_model, value: FALSE }
+    mm_port_names:
+      - REG_EPCS
+
+  - peripheral_name: dp/dpmm
+    mm_port_names:
+      - REG_DPMM_CTRL
+      - REG_DPMM_DATA
+
+  - peripheral_name: dp/mmdp
+    mm_port_names:
+      - REG_MMDP_CTRL
+      - REG_MMDP_DATA
+
   - peripheral_name: remu/remu
-    slave_port_names:
-      - reg_remu
+    mm_port_names:
+      - REG_REMU
  

boards/uniboard2c/libraries/unb2c_board/unb2c_board.peripheral.yaml

----
 schema_name: args
 schema_version: 1.0
 schema_type: peripheral
 
-hdl_library_name       : unb2c_board
-hdl_library_description: " This is the description for the unb2c_board package "
-
-# <peripheral_group>_<peripheral_name>_<slave_name>_<slave_type>
+hdl_library_name: unb2c_board  # ctrl_unb2c_board.vhd
+hdl_library_description: "Peripherals in unb2c_board."
 
 peripherals:
-
-  - peripheral_name: unb2c
-    parameters:
-      - { name: g_sim,       value: FALSE }
-      - { name: g_clk_freq,  value: c_unb2c_board_mm_clk_freq_125M }
-      - { name: g_temp_high, value: 85 }
-
-    slave_ports:
-        # rom_system_info
-      - slave_name   : rom_system
-        slave_type   : REG
+  - peripheral_name: ram_scrap  # pi_ram_scrap.py
+    peripheral_description: ""
+    mm_ports:
+      # MM port for common_ram_r_w.vhd
+      - mm_port_name: RAM_SCRAP
+        mm_port_type: RAM
+        mm_port_description: "One memory mapped block RAM for MM access test purposes."
         fields:
-          - - field_name    : info
-              access_mode   : RO
+          - - field_name: rw_data 
+              field_description: "Void data"
+              number_of_fields: 512
               address_offset: 0x0
-              number_of_fields: 8192
-              field_description: |
-                  "address place for rom_system_info"
-        slave_description: " rom_info  "
-
-        # reg_system_info
-      - slave_name   : system
-        slave_type   : REG
+              access_mode: RW
+              
+  - peripheral_name: system_info  # pi_system_info.py
+    peripheral_description: ""
+    mm_ports:
+      # MM port for mms_unb2c_board_system_info.vhd / common_rom.vhd
+      - mm_port_name: ROM_SYSTEM_INFO     # for c_rom_version = 1 in ctrl_unb2c_board.vhd
+      #- mm_port_name: ROM_SYSTEM_INFO_V2  # for c_rom_version = 2 in ctrl_unb2c_board.vhd
+        mm_port_type: RAM
+        mm_port_description: "Memory that stores the MM map system info of the mmap file."
         fields:
-          - - field_name    : info
-              access_mode   : RO
+          - - field_name: ro_data
+              field_description: "FPGA info memory map data"
+              number_of_fields: 32768   # c_rom_addr_w in mms_unb2c_board_system_info
               address_offset: 0x0
-              number_of_fields: 32
-              field_description: |
-                  "address place for reg_system_info"
-        slave_description: " reg_info "
+              mm_width: 32
+              user_width: 8
+              radix: char8
+              access_mode: RO
 
-      # actual hdl name: unb2c_board_wdi_reg
-      - slave_name   : ctrl
-        slave_type   : REG
+      # MM port for mms_unb2c_board_system_info.vhd / unb2c_board_system_info_reg.vhd
+      - mm_port_name: PIO_SYSTEM_INFO
+        mm_port_type: REG
+        mm_port_description: "FPGA design name, design note, version and location index info."
         fields:
-          - - field_name      : nios_reset
-              width           : 32
-              access_mode     : WO
-              address_offset  : 0x0
-              number_of_fields: 4
-              field_description: " Reset done by nios "
-
-        slave_description:  "Reset register, for nios "
+          # All registers in one array
+          #- - field_name: info
+          #    field_description: "FPGA info register, see pi_system_info.py for field details."
+          #    access_mode: RO
+          #    address_offset: 0x0
+          #    number_of_fields: 32
 
-      # actual hdl name: unb2c_board_wdi_reg
-      - slave_name   : wdi
-        slave_type   : REG
+          # Each field specified
+          - - field_name: info
+              field_description: "Info"
+              address_offset: 0x0
+              bit_offset: 0
+              mm_width: 32
+              access_mode: RO
+          - "info": # field_group
+            - field_name: gn_index
+              field_description: "Global node index, unb2 FPGA id = gn_index % 4, unb2 backplane id = gn_index // 4"
+              address_offset: 0x0
+              bit_offset: 0
+              mm_width: 8
+              access_mode: RO
+            - field_name: hw_version
+              field_description: "UniBoard2 hardware (HW) version."
+              address_offset: 0x0
+              bit_offset: 8
+              mm_width: 2
+              access_mode: RO
+            - field_name: cs_sim
+              field_description: "0 when running on HW, 1 when running in simulation."
+              address_offset: 0x0
+              bit_offset: 10
+              mm_width: 1
+              access_mode: RO
+            - field_name: fw_version_major
+              field_description: "FPGA Firmware (FW) version major number, not used use version stamp instead."
+              address_offset: 0x0
+              bit_offset: 16
+              mm_width: 4
+              access_mode: RO
+            - field_name: fw_version_minor
+              field_description: "FPGA Firmware (FW) version minor number, not used use version stamp instead."
+              address_offset: 0x0
+              bit_offset: 20
+              mm_width: 4
+              access_mode: RO
+            - field_name: rom_version
+              field_description: "Version of the mmap schema in ROM_SYSTEM_INFO."
+              address_offset: 0x0
+              bit_offset: 24
+              mm_width: 3
+              access_mode: RO
+            - field_name: technology
+              field_description: "FPGA technology"
+              address_offset: 0x0
+              bit_offset: 27
+              mm_width: 5
+              access_mode: RO
+          - - field_name: use_phy
+              field_description: "PHY interfaces that are active in the FPGA, not used."
+              address_offset: 0x4
+              mm_width: 8
+              access_mode: RO
+          - - field_name: design_name
+              field_description: "FPGA FW design name string."
+              number_of_fields: 52
+              address_offset: 0x8
+              mm_width: 32
+              user_width: 8
+              radix: char8
+              access_mode: RO
+          - - field_name: stamp_date
+              field_description: "FPGA FW compile date string."
+              access_mode: RO
+              address_offset: 0x3C
+              number_of_fields: 1
+          - - field_name: stamp_time
+              field_description: "FPGA FW compile time string."
+              number_of_fields: 1
+              address_offset: 0x40
+              access_mode: RO
+          - - field_name: stamp_commit
+              field_description: "FPGA FW commit hash string."
+              number_of_fields: 3
+              address_offset: 0x44
+              access_mode: RO
+          - - field_name: design_note
+              field_description: "FPGA FW design note string."
+              number_of_fields: 52
+              address_offset: 0x50
+              mm_width: 32
+              user_width: 8
+              radix: char8
+              access_mode: RO
+              
+  - peripheral_name: wdi  # pi_wdi.py
+    peripheral_description: ""
+    mm_ports:
+      # MM port for unb2c_board_wdi_reg.vhd
+      - mm_port_name: REG_WDI
+        mm_port_type: REG
+        mm_port_description: "Reset register, if the right value is provided the factory image will be reloaded in the FPGA."
         fields:
-          - - field_name    : reset_word
-              access_mode   : WO
+          - - field_name: wdi_override
+              field_description: "Write value 0xB007FAC7 = 'Boot factory' to disable the watchdog interrupt (WDI), to cause an FPGA image reload."
               address_offset: 0x0
-              field_description: " Only the value 0xB007FAC7 'Boot factory' will result in a reset "
-
-        slave_description:  "Reset register, if the right value is provided the factory image will be reloaded "
+              access_mode: WO
 
-      - slave_name   : fpga_temp
-        slave_type   : REG
+  - peripheral_name: unb2_fpga_sens
+    peripheral_description: ""
+    mm_ports:
+      # MM ports for mms_unb2c_fpga_sens.vhd / unb2c_fpga_sens_reg.vhd
+      - mm_port_name: REG_FPGA_TEMP_SENS   # pi_unb_fpga_sens.py
+        mm_port_type: REG
+        mm_port_description: |
+             "FPGA temperature = (AxC)/1024 - B (where A=708; B=273; C=adc value), see page 10 in
+              https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_alttemp_sense.pdf"
         fields:
-          - - field_name    : temp
-              width         : 32
-              access_mode   : RO
-              address_offset: 0x00
+          - - field_name: temp
+              field_description: "Raw data"
               number_of_fields: 1
-              field_description: ""
-        slave_description:  " "
-      - slave_name   : fpga_voltage
-        slave_type   : REG
-        fields:    
-          - - field_name    : voltage
-              width         : 32
-              access_mode   : RO
-              address_offset: 0x00
-              number_of_fields: 6
-              field_description: ""
-        slave_description:  " "
-
-      - slave_name   : scrap_ram
-        slave_type   : RAM
+              address_offset: 0x0
+              access_mode: RO
+              
+      - mm_port_name: REG_FPGA_VOLTAGE_SENS  # pi_unb_fpga_voltagesens.py
+        mm_port_type: REG
+        mm_port_description: "Not used, FPGA voltages are monitored via DC-DC converter power supply volages"
         fields:
-          - - field_name: data 
-              width     : 32
-              access_mode: RW
-              address_offset: 0x00
-              number_of_fields: 128
-              field_description: " "
-        slave_description: " "
+          - - field_name: voltages
+              field_description: "Not used"
+              number_of_fields: 6
+              address_offset: 0x0
+              access_mode: RO
 
-    peripheral_description: |
-        ""