diff --git a/libraries/technology/ddr/tech_ddr_mem_model.vhd b/libraries/technology/ddr/tech_ddr_mem_model.vhd new file mode 100644 index 0000000000000000000000000000000000000000..2426d147537f8ade18af6c3443dd1c51f3b254bb --- /dev/null +++ b/libraries/technology/ddr/tech_ddr_mem_model.vhd @@ -0,0 +1,104 @@ +-------------------------------------------------------------------------------- +-- +-- Copyright (C) 2014 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +-------------------------------------------------------------------------------- + +-- Purpose: DDR3 memory model for simulation. +-- Description: +-- The DDR3 memory model is not FPGA specific, but it was created by the example design for ip_stratixiv_ddr3_uphy_4g_800_master. +-- Therefore the ip_stratixiv_ddr3_uphy_4g_800_master_lib is needed if the model is used. + +-- Declare IP libraries to ensure default binding in simulation. +LIBRARY ip_stratixiv_ddr3_mem_model_lib; + + +LIBRARY IEEE, common_lib; +USE IEEE.STD_LOGIC_1164.ALL; +USE common_lib.common_pkg.ALL; +USE work.tech_ddr_pkg.ALL; +USE work.tech_ddr_mem_model_component_pkg.ALL; + +ENTITY tech_ddr_memory_model IS + GENERIC ( + g_tech_ddr : t_c_tech_ddr + ); + PORT ( + -- PHY interface + mem_in : IN t_tech_ddr_phy_ou; + mem_io : INOUT t_tech_ddr_phy_io + ); +END tech_ddr_memory_model; + + +ARCHITECTURE str OF tech_ddr_memory_model IS + + +BEGIN + + gen_ip_stratixiv_ddr_memory_model : IF g_tech_ddr.name="DDR3" GENERATE + u_ip_stratixiv_ddr_memory_model : alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en + GENERIC MAP ( + MEM_IF_CLK_EN_WIDTH => g_tech_ddr.cke_w, + MEM_IF_CK_WIDTH => g_tech_ddr.ck_w, + MEM_IF_BANKADDR_WIDTH => g_tech_ddr.ba_w, + MEM_IF_ADDR_WIDTH => g_tech_ddr.a_w, + MEM_IF_ROW_ADDR_WIDTH => g_tech_ddr.a_row_w, + MEM_IF_COL_ADDR_WIDTH => g_tech_ddr.a_col_w, + MEM_IF_CS_WIDTH => g_tech_ddr.cs_w, + MEM_IF_CONTROL_WIDTH => 1, -- cas_n, ras_n, we_n + MEM_IF_ODT_WIDTH => g_tech_ddr.odt_w, + DEVICE_DEPTH => 1, + DEVICE_WIDTH => 1, + MEM_IF_CS_PER_RANK => 1, + MEM_IF_DQS_WIDTH => g_tech_ddr.dqs_w, + MEM_IF_DQ_WIDTH => g_tech_ddr.dq_w, + MEM_MIRROR_ADDRESSING_DEC => 0, + MEM_TRTP => 8, + MEM_TRCD => 8, + MEM_DQS_TO_CLK_CAPTURE_DELAY => 100, + MEM_CLK_TO_DQS_CAPTURE_DELAY => 100000, + MEM_REGDIMM_ENABLED => 0, + MEM_INIT_EN => 0, + MEM_INIT_FILE => "", + MEM_GUARANTEED_WRITE_INIT => 0, + DAT_DATA_WIDTH => 32, + MEM_VERBOSE => 1 + ) + PORT MAP ( + mem_a => mem_in.a(g_tech_ddr.a_w-1 DOWNTO 0), -- MEM_IF_ADDR_WIDTH + mem_ba => mem_in.ba(g_tech_ddr.ba_w-1 DOWNTO 0), -- MEM_IF_BANKADDR_WIDTH + mem_ck => mem_in.ck(g_tech_ddr.ck_w-1 DOWNTO 0), -- MEM_IF_CK_WIDTH + mem_ck_n => mem_in.ck_n(g_tech_ddr.ck_w-1 DOWNTO 0), -- MEM_IF_CK_WIDTH + mem_cke => mem_in.cke(g_tech_ddr.cke_w-1 DOWNTO 0), -- MEM_IF_CLK_EN_WIDTH + mem_cs_n => mem_in.cs_n(g_tech_ddr.cs_w-1 DOWNTO 0), -- MEM_IF_CS_WIDTH + mem_ras_n => slv(mem_in.ras_n), -- MEM_IF_CONTROL_WIDTH + mem_cas_n => slv(mem_in.cas_n), -- MEM_IF_CONTROL_WIDTH + mem_we_n => slv(mem_in.we_n), -- MEM_IF_CONTROL_WIDTH + mem_reset_n => mem_in.reset_n, + mem_dm => mem_in.dm(g_tech_ddr.dqs_w-1 DOWNTO 0), -- MEM_IF_DQS_WIDTH + mem_dq => mem_io.dq(g_tech_ddr.dq_w-1 DOWNTO 0), -- MEM_IF_DQ_WIDTH + mem_dqs => mem_io.dqs(g_tech_ddr.dqs_w-1 DOWNTO 0), -- MEM_IF_DQS_WIDTH + mem_dqs_n => mem_io.dqs(g_tech_ddr.dqs_w-1 DOWNTO 0), -- MEM_IF_DQS_WIDTH + mem_odt => mem_in.odt(g_tech_ddr.odt_w-1 DOWNTO 0) -- MEM_IF_ODT_WIDTH + ); + END GENERATE; + +END str; + diff --git a/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd b/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd new file mode 100644 index 0000000000000000000000000000000000000000..e61e0e142e7098bcc99e482e6b11bfc60252fe95 --- /dev/null +++ b/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd @@ -0,0 +1,87 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2014 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +------------------------------------------------------------------------------- + +-- Purpose: IP components declarations for various devices that get wrapped by the tech components + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +PACKAGE tech_ddr_mem_model_component_pkg IS + + ------------------------------------------------------------------------------ + -- ip_stratixiv + ------------------------------------------------------------------------------ + + -- Manually derived VHDL entity from Verilog module alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en.sv in: + -- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master_example_design/simulation/vhdl/submodules/ + + COMPONENT alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en IS + GENERIC ( + MEM_IF_CLK_EN_WIDTH : INTEGER := 1; + MEM_IF_CK_WIDTH : INTEGER := 1; + MEM_IF_BANKADDR_WIDTH : INTEGER := 3; + MEM_IF_ADDR_WIDTH : INTEGER := 15; + MEM_IF_ROW_ADDR_WIDTH : INTEGER := 15; + MEM_IF_COL_ADDR_WIDTH : INTEGER := 10; + MEM_IF_CS_WIDTH : INTEGER := 1; + MEM_IF_CONTROL_WIDTH : INTEGER := 1; + MEM_IF_ODT_WIDTH : INTEGER := 1; + DEVICE_DEPTH : INTEGER := 1; + DEVICE_WIDTH : INTEGER := 1; + MEM_IF_CS_PER_RANK : INTEGER := 1; + MEM_IF_DQS_WIDTH : INTEGER := 1; + MEM_IF_DQ_WIDTH : INTEGER := 8; + MEM_MIRROR_ADDRESSING_DEC : INTEGER := 0; + MEM_TRTP : INTEGER := 8; + MEM_TRCD : INTEGER := 8; + MEM_DQS_TO_CLK_CAPTURE_DELAY : INTEGER := 100; + MEM_CLK_TO_DQS_CAPTURE_DELAY : INTEGER := 100000; + MEM_REGDIMM_ENABLED : INTEGER := 0; + MEM_INIT_EN : INTEGER := 0; + MEM_INIT_FILE : STRING := ""; + MEM_GUARANTEED_WRITE_INIT : INTEGER := 0; + DAT_DATA_WIDTH : INTEGER := 32; + MEM_VERBOSE : INTEGER := 1 + ); + PORT ( + mem_a : IN STD_LOGIC_VECTOR(MEM_IF_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS=>'X'); + mem_ba : IN STD_LOGIC_VECTOR(MEM_IF_BANKADDR_WIDTH-1 DOWNTO 0):= (OTHERS=>'X'); + mem_ck : IN STD_LOGIC_VECTOR(MEM_IF_CK_WIDTH-1 DOWNTO 0) := (OTHERS=>'X'); + mem_ck_n : IN STD_LOGIC_VECTOR(MEM_IF_CK_WIDTH-1 DOWNTO 0) := (OTHERS=>'X'); + mem_cke : IN STD_LOGIC_VECTOR(MEM_IF_CLK_EN_WIDTH-1 DOWNTO 0) := (OTHERS=>'X'); + mem_cs_n : IN STD_LOGIC_VECTOR(MEM_IF_CS_WIDTH-1 DOWNTO 0) := (OTHERS=>'X'); + mem_ras_n : IN STD_LOGIC_VECTOR(MEM_IF_CONTROL_WIDTH-1 DOWNTO 0) := (OTHERS=>'X'); + mem_cas_n : IN STD_LOGIC_VECTOR(MEM_IF_CONTROL_WIDTH-1 DOWNTO 0) := (OTHERS=>'X'); + mem_we_n : IN STD_LOGIC_VECTOR(MEM_IF_CONTROL_WIDTH-1 DOWNTO 0) := (OTHERS=>'X'); + mem_reset_n: IN STD_LOGIC := 'X'; + mem_dm : IN STD_LOGIC_VECTOR(MEM_IF_DQS_WIDTH-1 DOWNTO 0) := (OTHERS=>'X'); + mem_dq : INOUT STD_LOGIC_VECTOR(MEM_IF_DQ_WIDTH-1 DOWNTO 0) := (OTHERS=>'X'); + mem_dqs : INOUT STD_LOGIC_VECTOR(MEM_IF_DQS_WIDTH-1 DOWNTO 0) := (OTHERS=>'X'); + mem_dqs_n : INOUT STD_LOGIC_VECTOR(MEM_IF_DQS_WIDTH-1 DOWNTO 0) := (OTHERS=>'X'); + mem_odt : IN STD_LOGIC_VECTOR(MEM_IF_ODT_WIDTH-1 DOWNTO 0) := (OTHERS=>'X') + ); + END COMPONENT alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en; + +END tech_ddr_mem_model_component_pkg; + +PACKAGE BODY tech_ddr_mem_model_component_pkg IS +END tech_ddr_mem_model_component_pkg;