Skip to content
Snippets Groups Projects
Commit bb69952f authored by Eric Kooistra's avatar Eric Kooistra
Browse files

Rename g_ddr into g_tech_ddr

parent 3faa952b
No related branches found
No related tags found
No related merge requests found
Expand all Hide whitespace changes
Inline Side-by-side
libraries/technology/ddr3/tech_ddr3.vhd
+ 2
− 2
View file @ bb69952f
...@@ -29,7 +29,7 @@ USE tech_ddr_lib.tech_ddr_pkg.ALL; ...@@ -29,7 +29,7 @@ USE tech_ddr_lib.tech_ddr_pkg.ALL;
ENTITY tech_ddr3 IS ENTITY tech_ddr3 IS
GENERIC ( GENERIC (
g_technology : NATURAL := c_tech_select_default; g_technology : NATURAL := c_tech_select_default;
g_ddr : t_c_tech_ddr g_tech_ddr : t_c_tech_ddr
); );
PORT ( PORT (
-- PLL reference clock -- PLL reference clock
...@@ -61,7 +61,7 @@ BEGIN ...@@ -61,7 +61,7 @@ BEGIN
gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
u0 : ENTITY work.tech_ddr3_stratixiv u0 : ENTITY work.tech_ddr3_stratixiv
GENERIC MAP (g_ddr) GENERIC MAP (g_tech_ddr)
PORT MAP (ctlr_ref_clk, ctlr_ref_rst, PORT MAP (ctlr_ref_clk, ctlr_ref_rst,
ctlr_gen_clk, ctlr_gen_rst, ctlr_gen_clk_2x, ctlr_gen_rst_2x, ctlr_gen_clk, ctlr_gen_rst, ctlr_gen_clk_2x, ctlr_gen_rst_2x,
ctlr_init_done, ctlr_init_done,
......
libraries/technology/ddr3/tech_ddr3_stratixiv.vhd
+ 93
− 93
View file @ bb69952f
This diff is collapsed.
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment