From bb69952f93d4ce5c605ce64152ac04143448fb56 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Thu, 18 Dec 2014 13:47:27 +0000
Subject: [PATCH] Rename g_ddr into g_tech_ddr
---
libraries/technology/ddr3/tech_ddr3.vhd | 4 +-
.../technology/ddr3/tech_ddr3_stratixiv.vhd | 186 +++++++++---------
2 files changed, 95 insertions(+), 95 deletions(-)
diff --git a/libraries/technology/ddr3/tech_ddr3.vhd b/libraries/technology/ddr3/tech_ddr3.vhd
index fa8dd8a7ee..09a3b5ab52 100644
--- a/libraries/technology/ddr3/tech_ddr3.vhd
+++ b/libraries/technology/ddr3/tech_ddr3.vhd
@@ -29,7 +29,7 @@ USE tech_ddr_lib.tech_ddr_pkg.ALL;
ENTITY tech_ddr3 IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
- g_ddr : t_c_tech_ddr
+ g_tech_ddr : t_c_tech_ddr
);
PORT (
-- PLL reference clock
@@ -61,7 +61,7 @@ BEGIN
gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
u0 : ENTITY work.tech_ddr3_stratixiv
- GENERIC MAP (g_ddr)
+ GENERIC MAP (g_tech_ddr)
PORT MAP (ctlr_ref_clk, ctlr_ref_rst,
ctlr_gen_clk, ctlr_gen_rst, ctlr_gen_clk_2x, ctlr_gen_rst_2x,
ctlr_init_done,
diff --git a/libraries/technology/ddr3/tech_ddr3_stratixiv.vhd b/libraries/technology/ddr3/tech_ddr3_stratixiv.vhd
index 2444e87fe1..40220af65e 100644
--- a/libraries/technology/ddr3/tech_ddr3_stratixiv.vhd
+++ b/libraries/technology/ddr3/tech_ddr3_stratixiv.vhd
@@ -32,7 +32,7 @@ USE work.tech_ddr3_component_pkg.ALL;
ENTITY tech_ddr3_stratixiv IS
GENERIC (
- g_ddr : t_c_tech_ddr
+ g_tech_ddr : t_c_tech_ddr
);
PORT (
-- PLL reference clock
@@ -65,105 +65,105 @@ ARCHITECTURE str OF tech_ddr3_stratixiv IS
BEGIN
- gen_master : IF g_ddr.master=TRUE GENERATE
+ gen_ip_stratixiv_ddr3_uphy_4g_800_master : IF func_tech_ddr_module_size(g_tech_ddr)=4 AND g_tech_ddr.mts=800 AND g_tech_ddr.master=TRUE GENERATE
u_ip_stratixiv_ddr3_uphy_4g_800_master : ip_stratixiv_ddr3_uphy_4g_800_master
PORT MAP (
- pll_ref_clk => ctlr_ref_clk, -- pll_ref_clk.clk
- global_reset_n => ctlr_ref_rst, -- global_reset.reset_n
- soft_reset_n => '0', -- soft_reset.reset_n
- afi_clk => ctlr_gen_clk, -- afi_clk.clk
- afi_half_clk => OPEN, -- afi_half_clk.clk
- afi_reset_n => ctlr_gen_rst, -- afi_reset.reset_n
- mem_a => phy_ou.a(g_ddr.a_w-1 DOWNTO 0), -- memory.mem_a
- mem_ba => phy_ou.ba(g_ddr.ba_w-1 DOWNTO 0), -- .mem_ba
- mem_ck => phy_io.clk(g_ddr.clk_w-1 DOWNTO 0), -- .mem_ck
- mem_ck_n => phy_io.clk_n(g_ddr.clk_w-1 DOWNTO 0), -- .mem_ck_n
- mem_cke => phy_ou.cke(g_ddr.clk_w-1 DOWNTO 0), -- .mem_cke
- mem_cs_n => phy_ou.cs_n(g_ddr.cs_w-1 DOWNTO 0), -- .mem_cs_n
- mem_dm => phy_ou.dm(g_ddr.dm_w-1 DOWNTO 0), -- .mem_dm
- mem_ras_n => phy_ou.ras_n, -- .mem_ras_n
- mem_cas_n => phy_ou.cas_n, -- .mem_cas_n
- mem_we_n => phy_ou.we_n, -- .mem_we_n
- mem_reset_n => phy_ou.reset_n, -- .mem_reset_n
- mem_dq => phy_io.dq(g_ddr.dq_w-1 DOWNTO 0), -- .mem_dq
- mem_dqs => phy_io.dqs(g_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs
- mem_dqs_n => phy_io.dqs_n(g_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs_n
- mem_odt => phy_ou.odt(g_ddr.cs_w-1 DOWNTO 0), -- .mem_odt
- avl_ready => ctrl_miso.waitrequest_n, -- avl.waitrequest_n
- avl_burstbegin => ctrl_mosi.burstbegin, -- .beginbursttransfer
- avl_addr => ctrl_mosi.address(g_ddr.address_w-1 DOWNTO 0), -- .address
- avl_rdata_valid => ctrl_miso.rdval, -- .readdatavalid
- avl_rdata => ctrl_miso.rddata(g_ddr.data_w-1 DOWNTO 0), -- .readdata
- avl_wdata => ctrl_mosi.wrdata(g_ddr.data_w-1 DOWNTO 0), -- .writedata
- avl_be => (OTHERS=>'1'), -- .byteenable
- avl_read_req => ctrl_mosi.rd, -- .read
- avl_write_req => ctrl_mosi.wr, -- .write
- avl_size => ctrl_mosi.burstsize(g_ddr.maxburstsize_w-1 DOWNTO 0), -- .burstcount
- local_init_done => ctlr_init_done, -- status.local_init_done
- local_cal_success => OPEN, -- .local_cal_success
- local_cal_fail => OPEN, -- .local_cal_fail
- oct_rdn => phy_in.oct_rdn, -- oct.rdn
- oct_rup => phy_in.oct_rup, -- .rup
- seriesterminationcontrol => phy_ou.seriesterminationcontrol(g_ddr.terminationcontrol_w-1 DOWNTO 0), -- oct_sharing.seriesterminationcontrol
- parallelterminationcontrol => phy_ou.parallelterminationcontrol(g_ddr.terminationcontrol_w-1 DOWNTO 0), -- .parallelterminationcontrol
- pll_mem_clk => i_ctlr_gen_clk_2x, -- pll_sharing.pll_mem_clk
- pll_write_clk => OPEN, -- .pll_write_clk
- pll_write_clk_pre_phy_clk => OPEN, -- .pll_write_clk_pre_phy_clk
- pll_addr_cmd_clk => OPEN, -- .pll_addr_cmd_clk
- pll_locked => OPEN, -- .pll_locked
- pll_avl_clk => OPEN, -- .pll_avl_clk
- pll_config_clk => OPEN, -- .pll_config_clk
- dll_delayctrl => OPEN -- dll_sharing.dll_delayctrl
+ pll_ref_clk => ctlr_ref_clk, -- pll_ref_clk.clk
+ global_reset_n => ctlr_ref_rst, -- global_reset.reset_n
+ soft_reset_n => '0', -- soft_reset.reset_n
+ afi_clk => ctlr_gen_clk, -- afi_clk.clk
+ afi_half_clk => OPEN, -- afi_half_clk.clk
+ afi_reset_n => ctlr_gen_rst, -- afi_reset.reset_n
+ mem_a => phy_ou.a(g_tech_ddr.a_w-1 DOWNTO 0), -- memory.mem_a
+ mem_ba => phy_ou.ba(g_tech_ddr.ba_w-1 DOWNTO 0), -- .mem_ba
+ mem_ck => phy_io.clk(g_tech_ddr.clk_w-1 DOWNTO 0), -- .mem_ck
+ mem_ck_n => phy_io.clk_n(g_tech_ddr.clk_w-1 DOWNTO 0), -- .mem_ck_n
+ mem_cke => phy_ou.cke(g_tech_ddr.clk_w-1 DOWNTO 0), -- .mem_cke
+ mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w-1 DOWNTO 0), -- .mem_cs_n
+ mem_dm => phy_ou.dm(g_tech_ddr.dm_w-1 DOWNTO 0), -- .mem_dm
+ mem_ras_n => phy_ou.ras_n, -- .mem_ras_n
+ mem_cas_n => phy_ou.cas_n, -- .mem_cas_n
+ mem_we_n => phy_ou.we_n, -- .mem_we_n
+ mem_reset_n => phy_ou.reset_n, -- .mem_reset_n
+ mem_dq => phy_io.dq(g_tech_ddr.dq_w-1 DOWNTO 0), -- .mem_dq
+ mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs
+ mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs_n
+ mem_odt => phy_ou.odt(g_tech_ddr.cs_w-1 DOWNTO 0), -- .mem_odt
+ avl_ready => ctrl_miso.waitrequest_n, -- avl.waitrequest_n
+ avl_burstbegin => ctrl_mosi.burstbegin, -- .beginbursttransfer
+ avl_addr => ctrl_mosi.address(g_tech_ddr.address_w-1 DOWNTO 0), -- .address
+ avl_rdata_valid => ctrl_miso.rdval, -- .readdatavalid
+ avl_rdata => ctrl_miso.rddata(g_tech_ddr.data_w-1 DOWNTO 0), -- .readdata
+ avl_wdata => ctrl_mosi.wrdata(g_tech_ddr.data_w-1 DOWNTO 0), -- .writedata
+ avl_be => (OTHERS=>'1'), -- .byteenable
+ avl_read_req => ctrl_mosi.rd, -- .read
+ avl_write_req => ctrl_mosi.wr, -- .write
+ avl_size => ctrl_mosi.burstsize(g_tech_ddr.maxburstsize_w-1 DOWNTO 0), -- .burstcount
+ local_init_done => ctlr_init_done, -- status.local_init_done
+ local_cal_success => OPEN, -- .local_cal_success
+ local_cal_fail => OPEN, -- .local_cal_fail
+ oct_rdn => phy_in.oct_rdn, -- oct.rdn
+ oct_rup => phy_in.oct_rup, -- .rup
+ seriesterminationcontrol => phy_ou.seriesterminationcontrol(g_tech_ddr.terminationcontrol_w-1 DOWNTO 0), -- oct_sharing.seriesterminationcontrol
+ parallelterminationcontrol => phy_ou.parallelterminationcontrol(g_tech_ddr.terminationcontrol_w-1 DOWNTO 0), -- .parallelterminationcontrol
+ pll_mem_clk => i_ctlr_gen_clk_2x, -- pll_sharing.pll_mem_clk
+ pll_write_clk => OPEN, -- .pll_write_clk
+ pll_write_clk_pre_phy_clk => OPEN, -- .pll_write_clk_pre_phy_clk
+ pll_addr_cmd_clk => OPEN, -- .pll_addr_cmd_clk
+ pll_locked => OPEN, -- .pll_locked
+ pll_avl_clk => OPEN, -- .pll_avl_clk
+ pll_config_clk => OPEN, -- .pll_config_clk
+ dll_delayctrl => OPEN -- dll_sharing.dll_delayctrl
);
END GENERATE;
- gen_slave : IF g_ddr.master=FALSE GENERATE
+ gen_ip_stratixiv_ddr3_uphy_4g_800_slave : IF func_tech_ddr_module_size(g_tech_ddr)=4 AND g_tech_ddr.mts=800 AND g_tech_ddr.master=FALSE GENERATE
u_ip_stratixiv_ddr3_uphy_4g_800_slave : ip_stratixiv_ddr3_uphy_4g_800_slave
PORT MAP (
- pll_ref_clk => ctlr_ref_clk, -- pll_ref_clk.clk
- global_reset_n => ctlr_ref_rst, -- global_reset.reset_n
- soft_reset_n => '0', -- soft_reset.reset_n
- afi_clk => ctlr_gen_clk, -- afi_clk.clk
- afi_half_clk => OPEN, -- afi_half_clk.clk
- afi_reset_n => ctlr_gen_rst, -- afi_reset.reset_n
- mem_a => phy_ou.a(g_ddr.a_w-1 DOWNTO 0), -- memory.mem_a
- mem_ba => phy_ou.ba(g_ddr.ba_w-1 DOWNTO 0), -- .mem_ba
- mem_ck => phy_io.clk(g_ddr.clk_w-1 DOWNTO 0), -- .mem_ck
- mem_ck_n => phy_io.clk_n(g_ddr.clk_w-1 DOWNTO 0), -- .mem_ck_n
- mem_cke => phy_ou.cke(g_ddr.clk_w-1 DOWNTO 0), -- .mem_cke
- mem_cs_n => phy_ou.cs_n(g_ddr.cs_w-1 DOWNTO 0), -- .mem_cs_n
- mem_dm => phy_ou.dm(g_ddr.dm_w-1 DOWNTO 0), -- .mem_dm
- mem_ras_n => phy_ou.ras_n, -- .mem_ras_n
- mem_cas_n => phy_ou.cas_n, -- .mem_cas_n
- mem_we_n => phy_ou.we_n, -- .mem_we_n
- mem_reset_n => phy_ou.reset_n, -- .mem_reset_n
- mem_dq => phy_io.dq(g_ddr.dq_w-1 DOWNTO 0), -- .mem_dq
- mem_dqs => phy_io.dqs(g_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs
- mem_dqs_n => phy_io.dqs_n(g_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs_n
- mem_odt => phy_ou.odt(g_ddr.cs_w-1 DOWNTO 0), -- .mem_odt
- avl_ready => ctrl_miso.waitrequest_n, -- avl.waitrequest_n
- avl_burstbegin => ctrl_mosi.burstbegin, -- .beginbursttransfer
- avl_addr => ctrl_mosi.address(g_ddr.address_w-1 DOWNTO 0), -- .address
- avl_rdata_valid => ctrl_miso.rdval, -- .readdatavalid
- avl_rdata => ctrl_miso.rddata(g_ddr.data_w-1 DOWNTO 0), -- .readdata
- avl_wdata => ctrl_mosi.wrdata(g_ddr.data_w-1 DOWNTO 0), -- .writedata
- avl_be => (OTHERS=>'1'), -- .byteenable
- avl_read_req => ctrl_mosi.rd, -- .read
- avl_write_req => ctrl_mosi.wr, -- .write
- avl_size => ctrl_mosi.burstsize(g_ddr.maxburstsize_w-1 DOWNTO 0), -- .burstcount
- local_init_done => ctlr_init_done, -- status.local_init_done
- local_cal_success => OPEN, -- .local_cal_success
- local_cal_fail => OPEN, -- .local_cal_fail
- seriesterminationcontrol => phy_in.seriesterminationcontrol(g_ddr.terminationcontrol_w-1 DOWNTO 0), -- oct_sharing.seriesterminationcontrol
- parallelterminationcontrol => phy_in.parallelterminationcontrol(g_ddr.terminationcontrol_w-1 DOWNTO 0), -- .parallelterminationcontrol
- pll_mem_clk => i_ctlr_gen_clk_2x, -- pll_sharing.pll_mem_clk
- pll_write_clk => OPEN, -- .pll_write_clk
- pll_write_clk_pre_phy_clk => OPEN, -- .pll_write_clk_pre_phy_clk
- pll_addr_cmd_clk => OPEN, -- .pll_addr_cmd_clk
- pll_locked => OPEN, -- .pll_locked
- pll_avl_clk => OPEN, -- .pll_avl_clk
- pll_config_clk => OPEN, -- .pll_config_clk
- dll_delayctrl => OPEN -- dll_sharing.dll_delayctrl
+ pll_ref_clk => ctlr_ref_clk, -- pll_ref_clk.clk
+ global_reset_n => ctlr_ref_rst, -- global_reset.reset_n
+ soft_reset_n => '0', -- soft_reset.reset_n
+ afi_clk => ctlr_gen_clk, -- afi_clk.clk
+ afi_half_clk => OPEN, -- afi_half_clk.clk
+ afi_reset_n => ctlr_gen_rst, -- afi_reset.reset_n
+ mem_a => phy_ou.a(g_tech_ddr.a_w-1 DOWNTO 0), -- memory.mem_a
+ mem_ba => phy_ou.ba(g_tech_ddr.ba_w-1 DOWNTO 0), -- .mem_ba
+ mem_ck => phy_io.clk(g_tech_ddr.clk_w-1 DOWNTO 0), -- .mem_ck
+ mem_ck_n => phy_io.clk_n(g_tech_ddr.clk_w-1 DOWNTO 0), -- .mem_ck_n
+ mem_cke => phy_ou.cke(g_tech_ddr.clk_w-1 DOWNTO 0), -- .mem_cke
+ mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w-1 DOWNTO 0), -- .mem_cs_n
+ mem_dm => phy_ou.dm(g_tech_ddr.dm_w-1 DOWNTO 0), -- .mem_dm
+ mem_ras_n => phy_ou.ras_n, -- .mem_ras_n
+ mem_cas_n => phy_ou.cas_n, -- .mem_cas_n
+ mem_we_n => phy_ou.we_n, -- .mem_we_n
+ mem_reset_n => phy_ou.reset_n, -- .mem_reset_n
+ mem_dq => phy_io.dq(g_tech_ddr.dq_w-1 DOWNTO 0), -- .mem_dq
+ mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs
+ mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs_n
+ mem_odt => phy_ou.odt(g_tech_ddr.cs_w-1 DOWNTO 0), -- .mem_odt
+ avl_ready => ctrl_miso.waitrequest_n, -- avl.waitrequest_n
+ avl_burstbegin => ctrl_mosi.burstbegin, -- .beginbursttransfer
+ avl_addr => ctrl_mosi.address(g_tech_ddr.address_w-1 DOWNTO 0), -- .address
+ avl_rdata_valid => ctrl_miso.rdval, -- .readdatavalid
+ avl_rdata => ctrl_miso.rddata(g_tech_ddr.data_w-1 DOWNTO 0), -- .readdata
+ avl_wdata => ctrl_mosi.wrdata(g_tech_ddr.data_w-1 DOWNTO 0), -- .writedata
+ avl_be => (OTHERS=>'1'), -- .byteenable
+ avl_read_req => ctrl_mosi.rd, -- .read
+ avl_write_req => ctrl_mosi.wr, -- .write
+ avl_size => ctrl_mosi.burstsize(g_tech_ddr.maxburstsize_w-1 DOWNTO 0), -- .burstcount
+ local_init_done => ctlr_init_done, -- status.local_init_done
+ local_cal_success => OPEN, -- .local_cal_success
+ local_cal_fail => OPEN, -- .local_cal_fail
+ seriesterminationcontrol => phy_in.seriesterminationcontrol(g_tech_ddr.terminationcontrol_w-1 DOWNTO 0), -- oct_sharing.seriesterminationcontrol
+ parallelterminationcontrol => phy_in.parallelterminationcontrol(g_tech_ddr.terminationcontrol_w-1 DOWNTO 0), -- .parallelterminationcontrol
+ pll_mem_clk => i_ctlr_gen_clk_2x, -- pll_sharing.pll_mem_clk
+ pll_write_clk => OPEN, -- .pll_write_clk
+ pll_write_clk_pre_phy_clk => OPEN, -- .pll_write_clk_pre_phy_clk
+ pll_addr_cmd_clk => OPEN, -- .pll_addr_cmd_clk
+ pll_locked => OPEN, -- .pll_locked
+ pll_avl_clk => OPEN, -- .pll_avl_clk
+ pll_config_clk => OPEN, -- .pll_config_clk
+ dll_delayctrl => OPEN -- dll_sharing.dll_delayctrl
);
END GENERATE;
--
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