Use g_technology = c_tech_arria10_e1sg for unb2b.

boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd

@@ -411,7 +411,7 @@ BEGIN
       eth1g_eth0_tse_mosi.rd <= '0';
       WAIT FOR 400 ns;
       WAIT UNTIL rising_edge(mm_clk);
-      proc_tech_tse_setup(c_tech_arria10_e1sg, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, mm_clk, eth1g_eth0_tse_miso, eth1g_eth0_tse_mosi);
+      proc_tech_tse_setup(g_technology, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, mm_clk, eth1g_eth0_tse_miso, eth1g_eth0_tse_mosi);
 
       -- Enable RX
       proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_sim_eth_control_rx_en, mm_clk, eth1g_eth0_reg_miso, sim_eth1g_eth0_reg_mosi);  -- control rx en

boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd

@@ -41,7 +41,7 @@ ENTITY ctrl_unb2b_board IS
     ----------------------------------------------------------------------------
     -- General
     ----------------------------------------------------------------------------
-    g_technology     : NATURAL := c_tech_arria10;
+    g_technology     : NATURAL := c_tech_arria10_e1sg;
     g_sim            : BOOLEAN := FALSE;
     g_sim_level      : NATURAL := 1;  -- 0 = use IP; 1 = use fast serdes model;
     g_sim_mm_clk_period : TIME := 10 ns;   -- use e.g. c_mmf_mm_clk_period for MM bus file IO model, use e.g. 10 ns for MM access with TSE MAC IP

boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd

@@ -29,7 +29,7 @@ USE technology_lib.technology_pkg.ALL;
 ENTITY mms_unb2b_board_system_info IS
   GENERIC (
     g_sim         : BOOLEAN := FALSE;
-    g_technology  : NATURAL := c_tech_arria10;
+    g_technology  : NATURAL := c_tech_arria10_e1sg;
     g_design_name : STRING;
     g_fw_version  : t_unb2b_board_fw_version := c_unb2b_board_fw_version;  -- firmware version x.y
     g_stamp_date  : NATURAL := 0;

boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd

@@ -33,7 +33,7 @@ USE technology_lib.technology_pkg.ALL;
 ENTITY mms_unb2b_fpga_sens IS
   GENERIC (
     g_sim             : BOOLEAN := FALSE;
-    g_technology      : NATURAL := c_tech_arria10;
+    g_technology      : NATURAL := c_tech_arria10_e1sg;
     g_temp_high       : NATURAL := 85
   );
   PORT (

boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd

@@ -35,7 +35,7 @@ USE technology_lib.technology_pkg.ALL;
 
 ENTITY unb2b_board_clk125_pll IS
   GENERIC (
-    g_technology : NATURAL := c_tech_arria10;
+    g_technology : NATURAL := c_tech_arria10_e1sg;
     g_use_clkbuf : BOOLEAN := TRUE;
     g_use_fpll   : BOOLEAN := FALSE
   );

boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd

@@ -92,7 +92,7 @@ USE technology_lib.technology_pkg.ALL;
 
 ENTITY unb2b_board_clk200_pll IS
   GENERIC (
-    g_technology          : NATURAL := c_tech_arria10;
+    g_technology          : NATURAL := c_tech_arria10_e1sg;
     g_use_clkbuf          : BOOLEAN := TRUE;
     g_use_fpll            : BOOLEAN := FALSE;
     g_operation_mode      : STRING  := "NORMAL";  -- "NORMAL", "NO_COMPENSATION", or "SOURCE_SYNCHRONOUS" --> requires PLL_COMPENSATE assignment to an input pin to compensate for (stratixiv)

boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd

@@ -35,7 +35,7 @@ USE technology_lib.technology_pkg.ALL;
 
 ENTITY unb2b_board_clk25_pll IS
   GENERIC (
-    g_technology : NATURAL := c_tech_arria10
+    g_technology : NATURAL := c_tech_arria10_e1sg
   );
   PORT (
     arst        : IN  STD_LOGIC := '0';

boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd

@@ -36,7 +36,7 @@ ENTITY unb2b_board_system_info IS
     g_fw_version : t_unb2b_board_fw_version := c_unb2b_board_fw_version;  -- firmware version x.y (4b.4b)
     g_aux        : t_c_unb2b_board_aux := c_unb2b_board_aux;              -- aux contains the hardware version
     g_rom_version: NATURAL := 1;
-    g_technology : NATURAL := c_tech_arria10
+    g_technology : NATURAL := c_tech_arria10_e1sg
   );
   PORT (
     clk         : IN  STD_LOGIC;

boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2b_board_10gbe.vhd

@@ -32,7 +32,7 @@ ENTITY unb2b_board_10gbe IS
   GENERIC (
     g_sim                    : BOOLEAN := FALSE;
     g_sim_level              : NATURAL := 1; -- 0 = use IP; 1 = use fast serdes model
-    g_technology             : NATURAL := c_tech_arria10;
+    g_technology             : NATURAL := c_tech_arria10_e1sg;
     g_nof_macs               : NATURAL;
     g_direction              : STRING := "TX_RX";  -- "TX_RX", "TX_ONLY", "RX_ONLY"
     g_tx_fifo_fill           : NATURAL := 10;    -- Release tx packet only when sufficiently data is available, 

boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd

@@ -41,7 +41,7 @@ ENTITY ctrl_unb2c_board IS
     ----------------------------------------------------------------------------
     -- General
     ----------------------------------------------------------------------------
-    g_technology   : NATURAL := c_tech_arria10;
+    g_technology   : NATURAL := c_tech_arria10_e2sg;
     g_sim          : BOOLEAN := FALSE;
     g_sim_level    : NATURAL := 1;  -- 0 = use IP; 1 = use fast serdes model;
     g_sim_mm_clk_period : TIME := 10 ns; -- use e.g. c_mmf_mm_clk_period for MM bus file IO model, use e.g. 10 ns for MM access with TSE MAC IP