diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
index 2f1b37763ab87fe92d8dcccc35243e9248245f2f..d0e7424ddb952190aa640815238a0bfcd085aef3 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
@@ -411,7 +411,7 @@ BEGIN
eth1g_eth0_tse_mosi.rd <= '0';
WAIT FOR 400 ns;
WAIT UNTIL rising_edge(mm_clk);
- proc_tech_tse_setup(c_tech_arria10_e1sg, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, mm_clk, eth1g_eth0_tse_miso, eth1g_eth0_tse_mosi);
+ proc_tech_tse_setup(g_technology, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, mm_clk, eth1g_eth0_tse_miso, eth1g_eth0_tse_mosi);
-- Enable RX
proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_sim_eth_control_rx_en, mm_clk, eth1g_eth0_reg_miso, sim_eth1g_eth0_reg_mosi); -- control rx en
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
index 11f71912060c66fd2d324bd4a0530a103d6b1738..b829f35bcc6b52b8ccdb4cd7b1d89cae9eb43143 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
@@ -41,7 +41,7 @@ ENTITY ctrl_unb2b_board IS
----------------------------------------------------------------------------
-- General
----------------------------------------------------------------------------
- g_technology : NATURAL := c_tech_arria10;
+ g_technology : NATURAL := c_tech_arria10_e1sg;
g_sim : BOOLEAN := FALSE;
g_sim_level : NATURAL := 1; -- 0 = use IP; 1 = use fast serdes model;
g_sim_mm_clk_period : TIME := 10 ns; -- use e.g. c_mmf_mm_clk_period for MM bus file IO model, use e.g. 10 ns for MM access with TSE MAC IP
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd
index 580a5dda6129c73761ce6b602a4555e0f747ddcd..aad5e0f1d0ce3d94013115555ec31b4e7c3175d0 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd
@@ -29,7 +29,7 @@ USE technology_lib.technology_pkg.ALL;
ENTITY mms_unb2b_board_system_info IS
GENERIC (
g_sim : BOOLEAN := FALSE;
- g_technology : NATURAL := c_tech_arria10;
+ g_technology : NATURAL := c_tech_arria10_e1sg;
g_design_name : STRING;
g_fw_version : t_unb2b_board_fw_version := c_unb2b_board_fw_version; -- firmware version x.y
g_stamp_date : NATURAL := 0;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd
index 9db4496059eaa928afed5c9f0d20ed492f30fdaf..fc97dba36a9b041459404b96d4aca29f10df167f 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd
@@ -33,7 +33,7 @@ USE technology_lib.technology_pkg.ALL;
ENTITY mms_unb2b_fpga_sens IS
GENERIC (
g_sim : BOOLEAN := FALSE;
- g_technology : NATURAL := c_tech_arria10;
+ g_technology : NATURAL := c_tech_arria10_e1sg;
g_temp_high : NATURAL := 85
);
PORT (
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd
index 9d228fbe3103f5a3b7951bf8a57ea0d344b62af1..4629190d3d4baaafca210598011568ea471aecff 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd
@@ -35,7 +35,7 @@ USE technology_lib.technology_pkg.ALL;
ENTITY unb2b_board_clk125_pll IS
GENERIC (
- g_technology : NATURAL := c_tech_arria10;
+ g_technology : NATURAL := c_tech_arria10_e1sg;
g_use_clkbuf : BOOLEAN := TRUE;
g_use_fpll : BOOLEAN := FALSE
);
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd
index ebc2bb83203883da147e19b9c8df2b2242e65aae..d64018149c18c115490f6575e6cf19e44f6c3221 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd
@@ -92,7 +92,7 @@ USE technology_lib.technology_pkg.ALL;
ENTITY unb2b_board_clk200_pll IS
GENERIC (
- g_technology : NATURAL := c_tech_arria10;
+ g_technology : NATURAL := c_tech_arria10_e1sg;
g_use_clkbuf : BOOLEAN := TRUE;
g_use_fpll : BOOLEAN := FALSE;
g_operation_mode : STRING := "NORMAL"; -- "NORMAL", "NO_COMPENSATION", or "SOURCE_SYNCHRONOUS" --> requires PLL_COMPENSATE assignment to an input pin to compensate for (stratixiv)
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd
index df7d873de9da1b25bf32953dcc02889ab09a2061..ea6beafdc7810281e433a37091937ac3d7432edc 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd
@@ -35,7 +35,7 @@ USE technology_lib.technology_pkg.ALL;
ENTITY unb2b_board_clk25_pll IS
GENERIC (
- g_technology : NATURAL := c_tech_arria10
+ g_technology : NATURAL := c_tech_arria10_e1sg
);
PORT (
arst : IN STD_LOGIC := '0';
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd
index 5f1062f2c1bcd07856191703bd8d4f974a977f01..eb33d3318ce0aced800e4dbd4d1b9210e7233e45 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd
@@ -36,7 +36,7 @@ ENTITY unb2b_board_system_info IS
g_fw_version : t_unb2b_board_fw_version := c_unb2b_board_fw_version; -- firmware version x.y (4b.4b)
g_aux : t_c_unb2b_board_aux := c_unb2b_board_aux; -- aux contains the hardware version
g_rom_version: NATURAL := 1;
- g_technology : NATURAL := c_tech_arria10
+ g_technology : NATURAL := c_tech_arria10_e1sg
);
PORT (
clk : IN STD_LOGIC;
diff --git a/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2b_board_10gbe.vhd b/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2b_board_10gbe.vhd
index f643576f3c16c7b5249a247694ebfbc082ca8036..ea691ef68f04d58fcf088916eaa7350c1997166e 100644
--- a/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2b_board_10gbe.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2b_board_10gbe.vhd
@@ -32,7 +32,7 @@ ENTITY unb2b_board_10gbe IS
GENERIC (
g_sim : BOOLEAN := FALSE;
g_sim_level : NATURAL := 1; -- 0 = use IP; 1 = use fast serdes model
- g_technology : NATURAL := c_tech_arria10;
+ g_technology : NATURAL := c_tech_arria10_e1sg;
g_nof_macs : NATURAL;
g_direction : STRING := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
g_tx_fifo_fill : NATURAL := 10; -- Release tx packet only when sufficiently data is available,
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
index ccf97cf6edcd7345fea47e80d8c0b5727798a64b..00560ddb4066b0d731cb160ae08eef419a5f0046 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
@@ -41,7 +41,7 @@ ENTITY ctrl_unb2c_board IS
----------------------------------------------------------------------------
-- General
----------------------------------------------------------------------------
- g_technology : NATURAL := c_tech_arria10;
+ g_technology : NATURAL := c_tech_arria10_e2sg;
g_sim : BOOLEAN := FALSE;
g_sim_level : NATURAL := 1; -- 0 = use IP; 1 = use fast serdes model;
g_sim_mm_clk_period : TIME := 10 ns; -- use e.g. c_mmf_mm_clk_period for MM bus file IO model, use e.g. 10 ns for MM access with TSE MAC IP