diff --git a/libraries/base/diag/diag.peripheral.yaml b/libraries/base/diag/diag.peripheral.yaml index 600f1bdf5e0b905f86ea6de6d2c6143b6e074d16..cd8c4446505f7292f7dd729c9b4fa0329b500561 100644 --- a/libraries/base/diag/diag.peripheral.yaml +++ b/libraries/base/diag/diag.peripheral.yaml @@ -27,44 +27,44 @@ peripherals: - - field_name : Samples_per_packet width : 16 - address_offset: 0x1 + address_offset: 0x4 reset_value : 256 field_description: | "This REG specifies the number samples in a packet" - - field_name : Blocks_per_sync width : 16 - address_offset: 0x2 + address_offset: 0x8 reset_value : 781250 field_description: | "This REG specifies the number of packets in a sync period" - - field_name : Gapsize width : 16 - address_offset: 0x3 + address_offset: 0xc reset_value : 80 field_description: | "This REG specifies the gap in number of clock cycles between two consecutive packets" - - field_name : Mem_low_address width : 8 - address_offset: 0x4 + address_offset: 0x10 field_description: | "This REG specifies the starting address for reading from the waveform memory" - - field_name : Mem_high_address width : 8 - address_offset: 0x5 + address_offset: 0x14 field_description: | "This REG specifies the last address to be read when from the waveform memory" - - field_name : BSN_init_low - address_offset: 0x6 + address_offset: 0x18 field_description: | "This REG specifies the lower(LSB) 32 bits [31:0] of the initialization BSN" - - field_name : BSN_init_high - address_offset: 0x7 + address_offset: 0x1c field_description: | "This REG specifies the higher(MSB) 32 bits [63:32] of the initialization BSN" @@ -102,26 +102,26 @@ peripherals: - - field_name : Word_cnt access_mode : RO - address_offset: 0x1 + address_offset: 0x4 field_description: | "Word_cnt indicates the number of word currently (ST) written in the buffer. Cleared on (ST) re-write of buffer." - - field_name : Valid_cnt_arm_ena - address_offset: 0x2 + address_offset: 0x8 field_description: | "Valid_cnt contains the number of valid cycles since the last sync pulse. Cleared on every sync pulse. Arm_enable: Write to this REG to arm the system. After the system is armed the next syn pulse will trigger the acquisition of data." - - field_name : Reg_sync_delay - address_offset: 0x3 + address_offset: 0xc field_description: | "Reg_sync_delay contains the number of valid cycles to delay/wait after an armed-syncpulse, before the data is written to the databuffer." - - field_name : Version access_mode : RO - address_offset: 0x7 + address_offset: 0x1c field_description: | "Version contains the version number of the databuffer peripheral." slave_description: ""