Revert "fixed mms_dp_gain_serial_arr latency"

This reverts commit cc66d7f3

applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd

@@ -120,10 +120,7 @@ BEGIN
     g_gain_w          => c_sdp_W_bf_weight,
     g_in_dat_w        => c_sdp_W_subband,
     g_out_dat_w       => c_gain_out_dat_w,
-    g_gains_file_name => g_gains_file_name,
-    -- extra input latency to ease timing.
-    g_pipeline_real_mult_input    => 2, 
-    g_pipeline_complex_mult_input => 2 
+    g_gains_file_name => g_gains_file_name
   )
   PORT MAP (
     -- System

applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd

@@ -120,10 +120,7 @@ BEGIN
     g_gain_w          => c_sdp_W_sub_weight,
     g_in_dat_w        => c_sdp_W_subband,
     g_out_dat_w       => c_gain_out_dat_w,
-    g_gains_file_name => g_gains_file_name,
-    -- extra input latency to ease timing.
-    g_pipeline_real_mult_input    => 2, 
-    g_pipeline_complex_mult_input => 2 
+    g_gains_file_name => g_gains_file_name
   )
   PORT MAP (
     -- System

libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd

@@ -100,7 +100,7 @@ ARCHITECTURE str OF mms_dp_gain_serial_arr IS
   --   dat_w     : NATURAL;
   --   nof_dat   : NATURAL;    -- optional, nof dat words <= 2**adr_w
   --   init_sl   : STD_LOGIC;  -- optional, init all dat words to std_logic '0', '1' or 'X'
-  CONSTANT c_mm_ram : t_c_mem := (latency  => 1, 
+  CONSTANT c_mm_ram : t_c_mem := (latency  => 2, -- set latency to 2 to ease timing
                                   adr_w    => ceil_log2(g_nof_gains),
                                   dat_w    => sel_a_b(g_complex_gain, c_nof_complex, 1) * g_gain_w,
                                   nof_dat  => g_nof_gains,