From b8a74ed6e5a6e51da25935ff727f9a2f8521b477 Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Thu, 11 Aug 2022 07:55:15 +0000
Subject: [PATCH] Revert "fixed mms_dp_gain_serial_arr latency"
This reverts commit cc66d7f389df2d6ec92c0acdbf3c876f531d00ac
---
.../lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd | 5 +----
.../lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd | 5 +----
libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd | 2 +-
3 files changed, 3 insertions(+), 9 deletions(-)
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd
index a32d051701..3dec6eb529 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd
@@ -120,10 +120,7 @@ BEGIN
g_gain_w => c_sdp_W_bf_weight,
g_in_dat_w => c_sdp_W_subband,
g_out_dat_w => c_gain_out_dat_w,
- g_gains_file_name => g_gains_file_name,
- -- extra input latency to ease timing.
- g_pipeline_real_mult_input => 2,
- g_pipeline_complex_mult_input => 2
+ g_gains_file_name => g_gains_file_name
)
PORT MAP (
-- System
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd
index e5e7d4f12c..05d222f417 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd
@@ -120,10 +120,7 @@ BEGIN
g_gain_w => c_sdp_W_sub_weight,
g_in_dat_w => c_sdp_W_subband,
g_out_dat_w => c_gain_out_dat_w,
- g_gains_file_name => g_gains_file_name,
- -- extra input latency to ease timing.
- g_pipeline_real_mult_input => 2,
- g_pipeline_complex_mult_input => 2
+ g_gains_file_name => g_gains_file_name
)
PORT MAP (
-- System
diff --git a/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd
index 7e8174fa8f..25551f29f8 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd
@@ -100,7 +100,7 @@ ARCHITECTURE str OF mms_dp_gain_serial_arr IS
-- dat_w : NATURAL;
-- nof_dat : NATURAL; -- optional, nof dat words <= 2**adr_w
-- init_sl : STD_LOGIC; -- optional, init all dat words to std_logic '0', '1' or 'X'
- CONSTANT c_mm_ram : t_c_mem := (latency => 1,
+ CONSTANT c_mm_ram : t_c_mem := (latency => 2, -- set latency to 2 to ease timing
adr_w => ceil_log2(g_nof_gains),
dat_w => sel_a_b(g_complex_gain, c_nof_complex, 1) * g_gain_w,
nof_dat => g_nof_gains,
--
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