-Stopping clocks on tb_end.

applications/arts/designs/arts_unb1_sc1_3dish_1pol/tb/vhdl/tb_arts_unb1_sc1_3dish_1pol.vhd

@@ -81,9 +81,9 @@ BEGIN
   ----------------------------------------------------------------------------
   -- System setup
   ----------------------------------------------------------------------------
-  clk     <= NOT clk AFTER c_clk_period/2;         -- External clock (200 MHz)
-  eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (25 MHz)
-  sa_clk  <= NOT sa_clk  AFTER c_sa_clk_period/2;
+  clk     <= NOT clk     OR tb_end AFTER c_clk_period/2;         -- External clock (200 MHz)
+  eth_clk <= NOT eth_clk OR tb_end AFTER c_eth_clk_period/2; -- Ethernet ref clock (25 MHz)
+  sa_clk  <= NOT sa_clk  OR tb_end AFTER c_sa_clk_period/2;
   
   ------------------------------------------------------------------------------
   -- External PPS