From b85527dcd215a573631fab0a06329a2d047afecf Mon Sep 17 00:00:00 2001
From: Daniel van der Schuur <schuur@astron.nl>
Date: Tue, 28 Feb 2017 10:34:26 +0000
Subject: [PATCH] -Stopping clocks on tb_end.

---
 .../tb/vhdl/tb_arts_unb1_sc1_3dish_1pol.vhd                 | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/applications/arts/designs/arts_unb1_sc1_3dish_1pol/tb/vhdl/tb_arts_unb1_sc1_3dish_1pol.vhd b/applications/arts/designs/arts_unb1_sc1_3dish_1pol/tb/vhdl/tb_arts_unb1_sc1_3dish_1pol.vhd
index ef16c1766f..fa1b0c18e6 100644
--- a/applications/arts/designs/arts_unb1_sc1_3dish_1pol/tb/vhdl/tb_arts_unb1_sc1_3dish_1pol.vhd
+++ b/applications/arts/designs/arts_unb1_sc1_3dish_1pol/tb/vhdl/tb_arts_unb1_sc1_3dish_1pol.vhd
@@ -81,9 +81,9 @@ BEGIN
   ----------------------------------------------------------------------------
   -- System setup
   ----------------------------------------------------------------------------
-  clk     <= NOT clk AFTER c_clk_period/2;         -- External clock (200 MHz)
-  eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (25 MHz)
-  sa_clk  <= NOT sa_clk  AFTER c_sa_clk_period/2;
+  clk     <= NOT clk     OR tb_end AFTER c_clk_period/2;         -- External clock (200 MHz)
+  eth_clk <= NOT eth_clk OR tb_end AFTER c_eth_clk_period/2; -- Ethernet ref clock (25 MHz)
+  sa_clk  <= NOT sa_clk  OR tb_end AFTER c_sa_clk_period/2;
   
   ------------------------------------------------------------------------------
   -- External PPS
-- 
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