Added default input values to be able to use ram_r_w as a rom_r by leaving...

Added default input values to be able to use ram_r_w as a rom_r by leaving these ports not connected.

libraries/technology/ip_arria10/ram/ip_arria10_ram_r_w.vhd

@@ -96,9 +96,9 @@ ENTITY ip_arria10_ram_r_w IS
   );
   PORT (
     clk         : IN STD_LOGIC  := '1';
-    data        : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
-    rdaddress   : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
-    wraddress   : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
+    data        : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0) := (OTHERS=>'0');
+    rdaddress   : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
+    wraddress   : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
     wren        : IN STD_LOGIC  := '0';
     q           : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
   );