RTSD-79, fixed merge conflicts 2

applications/lofar1/RSP/pfb2/src/vhdl/pfb2_unit.vhd

@@ -152,5 +152,3 @@ begin
   out_sosi_arr <= pft_sosi_arr;
 
 end str;
-
-

applications/lofar1/RSP/pfs/src/vhdl/pfs_fir.vhd

@@ -28,4 +28,3 @@ entity pfs_fir is
     res_sync            : out std_logic
   );
 end pfs_fir;
\ No newline at end of file
-

applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf.vhd

@@ -17,4 +17,3 @@ entity pfs_fir_coefsbuf is
     rst         : in std_logic
   );
 end pfs_fir_coefsbuf;
\ No newline at end of file
-

applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf.vhd

@@ -19,4 +19,3 @@ entity pfs_fir_tapsbuf is
     rst           : in  std_logic
   );
 end pfs_fir_tapsbuf;
\ No newline at end of file
-

applications/lofar1/RSP/pfs/src/vhdl/pfs_pkg.vhd

@@ -37,4 +37,3 @@ end pfs_pkg;
 
 package body pfs_pkg is
 end pfs_pkg;
\ No newline at end of file
-

applications/lofar1/RSP/pfs/tb/vhdl/tb_pfs.vhd

@@ -125,4 +125,3 @@ begin
   end process;
 
 end tb;
\ No newline at end of file
-

applications/lofar1/RSP/pft2/src/vhdl/pft_pkg.vhd

@@ -48,4 +48,3 @@ end pft_pkg;
 
 package body pft_pkg is
 end pft_pkg;
\ No newline at end of file
-

applications/lofar1/RSP/pft2/src/vhdl/pft_separate.vhd

@@ -72,9 +72,9 @@ architecture rtl of pft_separate is
   signal rd_cnt            : std_logic_vector(g_fft_sz_w - 1 downto 0);
   signal nxt_rd_cnt        : std_logic_vector(rd_cnt'range);
 
-  signal page_rdy_dly      : std_logic_vector( 0 TO c_tot_delay - 1);
-  signal rdval_dly         : std_logic_vector( 0 TO c_tot_delay - 1);
-  signal rdsync_dly        : std_logic_vector( 0 TO c_tot_delay + 1);
+  signal page_rdy_dly      : std_logic_vector( 0 to c_tot_delay - 1);
+  signal rdval_dly         : std_logic_vector( 0 to c_tot_delay - 1);
+  signal rdsync_dly        : std_logic_vector( 0 to c_tot_delay + 1);
   signal nxt_rdsync_dly    : std_logic_vector(rdsync_dly'range);
   signal rdsync_reg        : std_logic;
   signal nxt_rdsync_reg    : std_logic;

applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_6ch_200MHz.vhd

@@ -70,8 +70,8 @@ entity lofar2_unb2b_adc_6ch_200MHz is
 
     -- 1GbE Control Interface
     ETH_CLK      : in    std_logic;
-    ETH_SGin     : IN    std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-    ETH_SGout    : OUT   std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+    ETH_SGin     : in    std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+    ETH_SGout    : out   std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
 
     -- LEDs
     QSFP_LED     : out   std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);