diff --git a/applications/lofar1/RSP/pfb2/src/vhdl/pfb2_unit.vhd b/applications/lofar1/RSP/pfb2/src/vhdl/pfb2_unit.vhd
index a002861e69e32599fca2c668c2cce59aa4a60d6c..3987733ec4ba59c5e5ab691c6f7254cf5917a2cc 100644
--- a/applications/lofar1/RSP/pfb2/src/vhdl/pfb2_unit.vhd
+++ b/applications/lofar1/RSP/pfb2/src/vhdl/pfb2_unit.vhd
@@ -152,5 +152,3 @@ begin
out_sosi_arr <= pft_sosi_arr;
end str;
-
-
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs.vhd
index e4c4083c81e6a79e30a038a43c04068c9c0b875d..053c933c2415b05c576381897d66b3739a070f4f 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs.vhd
@@ -175,4 +175,4 @@ begin
rst => rst
);
-end str;
+end str;
\ No newline at end of file
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine.vhd
index 977091fac622521d197fce13dc455c1ea2a7e604..d2e2984170c0715246496cd4019f6efeb9c9bb99 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine.vhd
@@ -19,4 +19,4 @@ entity pfs_combine is
clk : in std_logic;
rst : in std_logic
);
-end pfs_combine;
+end pfs_combine;
\ No newline at end of file
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir.vhd
index 2d7e1b58f3b285ca54dde61f550146c36a7e337f..b3877c1b40cb41e5b8825de124c77e44387e6cc6 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir.vhd
@@ -27,5 +27,4 @@ entity pfs_fir is
res_val : out std_logic;
res_sync : out std_logic
);
-end pfs_fir;
-
+end pfs_fir;
\ No newline at end of file
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf.vhd
index 2d2d65c5b5d41f2f8b0b6d2daa2feafa4fe23d78..b132444374ed8aa546dc9cd9adddc0ecefb10e4e 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf.vhd
@@ -16,5 +16,4 @@ entity pfs_fir_coefsbuf is
clk : in std_logic;
rst : in std_logic
);
-end pfs_fir_coefsbuf;
-
+end pfs_fir_coefsbuf;
\ No newline at end of file
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl.vhd
index 589cb8987f0cb0b52b6192ae145e580a6603e7be..2bbd1fa9ebbd6e38a6894f29774cc00cd8081b4e 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl.vhd
@@ -29,4 +29,4 @@ entity pfs_fir_ctrl is
result_val : out std_logic;
result_sync : out std_logic
);
-end pfs_fir_ctrl;
+end pfs_fir_ctrl;
\ No newline at end of file
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac.vhd
index e4e7eaf9b62349896f402c1358b4a2c09ed649b3..f0c46f25c596df863dcd0b786a633a2ab24065ef 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac.vhd
@@ -20,4 +20,4 @@ entity pfs_fir_mac is
rst : in std_logic;
result : out std_logic_vector (g_out_w - 1 downto 0)
);
-end pfs_fir_mac;
+end pfs_fir_mac;
\ No newline at end of file
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf.vhd
index fd4fefee1ef110b2e515305ad81ebff231a2da52..a5bc5988b51a305d98f50ded0bff6a372a24e6d1 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf.vhd
@@ -18,5 +18,4 @@ entity pfs_fir_tapsbuf is
clk : in std_logic;
rst : in std_logic
);
-end pfs_fir_tapsbuf;
-
+end pfs_fir_tapsbuf;
\ No newline at end of file
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_pkg.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_pkg.vhd
index 9c85c2190d85441be1a62f6fd4903a1e0b19bae5..47618c080e97176371ad719601de73bcc4eecf1d 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_pkg.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_pkg.vhd
@@ -36,5 +36,4 @@ end pfs_pkg;
package body pfs_pkg is
-end pfs_pkg;
-
+end pfs_pkg;
\ No newline at end of file
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate.vhd
index df310d7b22712a70a93d76a1646cd77e23584114..d34df26e41f602cd91322ce3580579ffc2bab0fa 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate.vhd
@@ -20,4 +20,4 @@ entity pfs_rotate is
out_val : out std_logic_vector(g_nof_fir - 1 downto 0);
out_sync : out std_logic
);
-end pfs_rotate;
+end pfs_rotate;
\ No newline at end of file
diff --git a/applications/lofar1/RSP/pfs/tb/vhdl/tb_pfs.vhd b/applications/lofar1/RSP/pfs/tb/vhdl/tb_pfs.vhd
index db4bd1c3f0c386b55e7c128fd41bff29353e2409..98ce19adce901ed997b880f366403b6dec84f644 100644
--- a/applications/lofar1/RSP/pfs/tb/vhdl/tb_pfs.vhd
+++ b/applications/lofar1/RSP/pfs/tb/vhdl/tb_pfs.vhd
@@ -124,5 +124,4 @@ begin
wait;
end process;
-end tb;
-
+end tb;
\ No newline at end of file
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd
index aeaeaa20db38a5135c347e27e7efea2e947f1e38..3a055461a299edbddd8c1f016fed6fca5551838b 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd
@@ -142,7 +142,7 @@ begin
--wr_im <= wr_dat(wr_im'RANGE);
s0 <= cnt(cnt'high - 1);
- s1 <= cnt(cnt'high ) when g_bf_name ="bf2 " else '0';
+ s1 <= cnt(cnt'high ) when g_bf_name ="bf2 " else '0';
registers : process (clk, rst)
begin
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd
index 1d4105c1849ce63979b5489310a1b84e11199cbd..a290eb62f85ac9728e42e2d6481e55f79c78c76a 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd
@@ -108,7 +108,7 @@ begin
nxt_pipe_sync <= in_sync & pipe_sync(pipe_sync'high downto 1);
s0 <= cnt(cnt'high - 1);
- s1 <= cnt(cnt'high ) when g_bf_name ="bf2 " else '0';
+ s1 <= cnt(cnt'high ) when g_bf_name ="bf2 " else '0';
out_val <= pipe_val(0);
out_sync <= pipe_sync(0);
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr.vhd
index 490a1fdf10c722d76eef5c56d0e16fa93d2cba45..8d27cb04b0617e305044d655e0201cf83baa5fd3 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr.vhd
@@ -88,4 +88,4 @@ begin
end if;
end process;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_pkg.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_pkg.vhd
index a8a2987315a70c5efd473567f0f3dd27222066da..54c2038cb307c025526a75dc17a7e103b5022aa0 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_pkg.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_pkg.vhd
@@ -47,5 +47,4 @@ end pft_pkg;
package body pft_pkg is
-end pft_pkg;
-
+end pft_pkg;
\ No newline at end of file
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_separate.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_separate.vhd
index 7ae344bb53f4b4573ba4f7e898f1944696f50b92..ac53a9c07e306d04d47fc252cd0408ca5c9b2ee0 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_separate.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_separate.vhd
@@ -72,9 +72,9 @@ architecture rtl of pft_separate is
signal rd_cnt : std_logic_vector(g_fft_sz_w - 1 downto 0);
signal nxt_rd_cnt : std_logic_vector(rd_cnt'range);
- signal page_rdy_dly : std_logic_vector( 0 TO c_tot_delay - 1);
- signal rdval_dly : std_logic_vector( 0 TO c_tot_delay - 1);
- signal rdsync_dly : std_logic_vector( 0 TO c_tot_delay + 1);
+ signal page_rdy_dly : std_logic_vector( 0 to c_tot_delay - 1);
+ signal rdval_dly : std_logic_vector( 0 to c_tot_delay - 1);
+ signal rdsync_dly : std_logic_vector( 0 to c_tot_delay + 1);
signal nxt_rdsync_dly : std_logic_vector(rdsync_dly'range);
signal rdsync_reg : std_logic;
signal nxt_rdsync_reg : std_logic;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_top.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_top.vhd
index f6d0eeb201ee792c957c8ca6152ec348f30e9341..818eebc79c9c30fff3356690358957ff56544686 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_top.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_top.vhd
@@ -25,4 +25,4 @@ entity pft_top is
clk : in std_logic;
rst : in std_logic
);
-end pft_top;
+end pft_top;
\ No newline at end of file
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch.vhd
index ea00f4e242dd7d913f52d88cc1587920f4e18a96..f56d81d503baa87b42eace4d647aab6e07dbcb34 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch.vhd
@@ -126,4 +126,4 @@ begin
);
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd
index fab13ed089cb0f43b9b1a151f30c53f41619a25c..50825da7c8eda14c4a0a6b516b59c6ace8edd154 100644
--- a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd
+++ b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd
@@ -232,7 +232,7 @@ architecture tb of tb_pft2 is
begin
un := to_unsigned(n, w);
for i in 0 to w - 1 loop
- ur(i) := un(w - 1 -i);
+ ur(i) := un(w - 1 - i);
end loop;
return to_integer(ur);
end func_bitrev;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_6ch_200MHz.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_6ch_200MHz.vhd
index 8e465e8fab838373b32564d3d9fc3602ce8c25cb..ebdfbd1490107cbfea9b9ac3a056b6ddef5baeb5 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_6ch_200MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_6ch_200MHz.vhd
@@ -70,8 +70,8 @@ entity lofar2_unb2b_adc_6ch_200MHz is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
index 77049fb74c5834b3603294b8c0d223c1f1927366..29625eb5ebceb314e2c37f745d5c4ab2bd81606d 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
@@ -69,8 +69,8 @@ entity lofar2_unb2b_adc_full is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
index 2d775cab13531cddc1a48e1c2afdfe330a5dbd24..a9551b1d789d01f84ed7f91f398050f2ed299a4a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
@@ -69,8 +69,8 @@ entity lofar2_unb2b_adc_one_node is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
index d607bb85f6468ead63767f9143b60caacc634ccb..7fc1193fb176aabc9d5c974620af9cace7968606 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
@@ -76,8 +76,8 @@ entity lofar2_unb2b_adc is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc_pkg.vhd
index 292e1a443896ebe6da2e243beb3231db0073d4c3..3184b1c48cae9a326aa62522677f5c72256d92ae 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc_pkg.vhd
@@ -59,4 +59,4 @@ package body lofar2_unb2b_adc_pkg is
end;
-end lofar2_unb2b_adc_pkg;
+end lofar2_unb2b_adc_pkg;
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
index d8da46069742460a9b8198855ece285105203bf4..42f9b46a696e1ac74465312010b8b19683a21061 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
@@ -238,4 +238,4 @@ package qsys_lofar2_unb2b_adc_pkg is
rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
);
end component qsys_lofar2_unb2b_adc;
-end qsys_lofar2_unb2b_adc_pkg;
+end qsys_lofar2_unb2b_adc_pkg;
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd
index 9a1ae6dc649eded393d35d8bfa5535100684f307..bfcb1be340499045969b3cd696ac80c6744fcf5e 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd
@@ -69,8 +69,8 @@ entity lofar2_unb2b_beamformer_one_node is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd
index b80576b5ef1118d0ea917cdeffa56d3edadd9a31..b5351eaaa22ef27cdca762adaced86701e27b679 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd
@@ -69,8 +69,8 @@ entity lofar2_unb2b_beamformer_one_node_256MHz is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd
index 3a8dd98e44fb7b7da81af902627e1994e2346ed4..802e5215b7cac4e884701958d65e7161fd0e1e17 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd
@@ -80,8 +80,8 @@ entity lofar2_unb2b_beamformer is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer_pkg.vhd
index 0058df442943cdf64a09f55dda8d79e074575b95..ed72bf2d629c03d2f4e8c3b34051dba57f3b65dc 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer_pkg.vhd
@@ -60,4 +60,4 @@ package body lofar2_unb2b_beamformer_pkg is
end;
-end lofar2_unb2b_beamformer_pkg;
+end lofar2_unb2b_beamformer_pkg;
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/qsys_lofar2_unb2b_beamformer_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/qsys_lofar2_unb2b_beamformer_pkg.vhd
index 390724e6c92e14e4c6cb0686db822fed6b4bdbcd..1130805b9e5122e93826a6d1e041fbc7bf21705b 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/qsys_lofar2_unb2b_beamformer_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/qsys_lofar2_unb2b_beamformer_pkg.vhd
@@ -346,4 +346,4 @@ package qsys_lofar2_unb2b_beamformer_pkg is
rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
);
end component qsys_lofar2_unb2b_beamformer;
-end qsys_lofar2_unb2b_beamformer_pkg;
+end qsys_lofar2_unb2b_beamformer_pkg;
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd
index 582f19a70f26f1ffd1d460759b6c74f5a1754a7f..501b47a642e937c41ea9691db079dbc4df2e9cc0 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd
@@ -509,8 +509,8 @@ begin
-- verify if subband power and beamlet power are the same. This is expected because we only use 1 WG input and the BF weights have unit value.
-- the difference should not be larger than 0.5% (+/- 2^13 for low values)
- assert v_sp_beamlet_power > 0.995 * v_sp_subband_power - 2.0**13 report "index (" & integer'image(v_S) &", " & integer'image(v_B) &"): Subband power = " & real'image(v_sp_subband_power) &" and Beamlet power = " & real'image(v_sp_beamlet_power) &" are not equal " severity ERROR;
- assert v_sp_beamlet_power < 1.005 * v_sp_subband_power + 2.0**13 report "index (" & integer'image(v_S) &", " & integer'image(v_B) &"): Subband power = " & real'image(v_sp_subband_power) &" and Beamlet power = " & real'image(v_sp_beamlet_power) &" are not equal " severity ERROR;
+ assert v_sp_beamlet_power > 0.995 * v_sp_subband_power - 2.0**13 report "index (" & integer'image(v_S) &", " & integer'image(v_B) &"): Subband power = " & real'image(v_sp_subband_power) &" and Beamlet power = " & real'image(v_sp_beamlet_power) &" are not equal " severity ERROR;
+ assert v_sp_beamlet_power < 1.005 * v_sp_subband_power + 2.0**13 report "index (" & integer'image(v_S) &", " & integer'image(v_B) &"): Subband power = " & real'image(v_sp_subband_power) &" and Beamlet power = " & real'image(v_sp_beamlet_power) &" are not equal " severity ERROR;
end if;
end loop;
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/lofar2_unb2b_filterbank_full.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/lofar2_unb2b_filterbank_full.vhd
index 6039ea6de2b94484912bd5c1747e2530f8c6ceef..3e20bc30e6bca72eaccf00b0fb797a27871e4b4e 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/lofar2_unb2b_filterbank_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/lofar2_unb2b_filterbank_full.vhd
@@ -69,8 +69,8 @@ entity lofar2_unb2b_filterbank_full is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/lofar2_unb2b_filterbank_full_256MHz.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/lofar2_unb2b_filterbank_full_256MHz.vhd
index 4ac5d2c77b13fc169dcf2bfa05caa76e6bb65f08..6f03aa77838723dbad6c620778b711b93a890199 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/lofar2_unb2b_filterbank_full_256MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/lofar2_unb2b_filterbank_full_256MHz.vhd
@@ -69,8 +69,8 @@ entity lofar2_unb2b_filterbank_full_256MHz is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd
index d4f06f5ab9e68eab05082005c4b70d6f497e2cf6..8c9831b0df3af6ed620806fce0c7476eb0c3ac11 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd
@@ -81,8 +81,8 @@ entity lofar2_unb2b_filterbank is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank_pkg.vhd
index 8f87e325ef2754b52ab067950eeb93b1cafe52c6..d3908c5da82d370573d92ee5caa9e731cd79d165 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank_pkg.vhd
@@ -60,4 +60,4 @@ package body lofar2_unb2b_filterbank_pkg is
end;
-end lofar2_unb2b_filterbank_pkg;
+end lofar2_unb2b_filterbank_pkg;
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/qsys_lofar2_unb2b_filterbank_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/qsys_lofar2_unb2b_filterbank_pkg.vhd
index c8c654b6d2a8b4ddeb4d423c7a8a733aec073aa9..a6f230e89369c448fae04468fdde7ce93c4063af 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/qsys_lofar2_unb2b_filterbank_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/qsys_lofar2_unb2b_filterbank_pkg.vhd
@@ -314,4 +314,4 @@ package qsys_lofar2_unb2b_filterbank_pkg is
pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'x') -- export
);
end component qsys_lofar2_unb2b_filterbank;
-end qsys_lofar2_unb2b_filterbank_pkg;
+end qsys_lofar2_unb2b_filterbank_pkg;
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/lofar2_unb2b_ring_full.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/lofar2_unb2b_ring_full.vhd
index d321e455b9b20fcd8cb621d0624be2f8d98abc1d..53c030f9f85e852c6e23f3cca7d778ff66bcb5b1 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/lofar2_unb2b_ring_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/lofar2_unb2b_ring_full.vhd
@@ -69,8 +69,8 @@ entity lofar2_unb2b_ring_full is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
@@ -80,9 +80,9 @@ entity lofar2_unb2b_ring_full is
QSFP_0_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
-- ring transceivers
- RinG_0_RX : IN std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ RinG_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
RING_0_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
- RinG_1_RX : IN std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
+ RinG_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
-- LEDs
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/lofar2_unb2b_ring_one.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/lofar2_unb2b_ring_one.vhd
index 384a7c43f66067da4a3a961324deed916baf201a..69515f1c3ef0499e509b894d704c9c14fb950386 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/lofar2_unb2b_ring_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/lofar2_unb2b_ring_one.vhd
@@ -72,8 +72,8 @@ entity lofar2_unb2b_ring_one is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
@@ -83,9 +83,9 @@ entity lofar2_unb2b_ring_one is
QSFP_0_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
-- ring transceivers
- RinG_0_RX : IN std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ RinG_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
RING_0_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
- RinG_1_RX : IN std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
+ RinG_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
-- LEDs
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd
index f0c5ae315c4e4f0e761e0a1ccc7f3713564e5bcd..605abc5918a7fa7e2619bfb099e831b91ce61cae 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd
@@ -81,8 +81,8 @@ entity lofar2_unb2b_ring is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
@@ -91,9 +91,9 @@ entity lofar2_unb2b_ring is
QSFP_0_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
-- ring transceivers
- RinG_0_RX : IN std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ RinG_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
RING_0_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
- RinG_1_RX : IN std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
+ RinG_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
-- LEDs
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring_pkg.vhd
index 63a06f190ed3f12b8f928037a171b99f59217bec..6412b56044c1531fece144b7ad6fda1033a06bbe 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring_pkg.vhd
@@ -55,4 +55,4 @@ package body lofar2_unb2b_ring_pkg is
end;
-end lofar2_unb2b_ring_pkg;
+end lofar2_unb2b_ring_pkg;
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd
index 6a531df96d1765c6ecb4f15d4bea808b13324c09..e25347ffdd85f71a2c15a1d9a221f89dc5be663f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd
@@ -242,4 +242,4 @@ package qsys_lofar2_unb2b_ring_pkg is
rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
);
end component qsys_lofar2_unb2b_ring;
-end qsys_lofar2_unb2b_ring_pkg;
+end qsys_lofar2_unb2b_ring_pkg;
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full.vhd
index a1055756ee8ff227f8b49832a47a0423af5aac8c..2dcfa51e4417afe6a31b0aa3f8a72aec0e71c743 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full.vhd
@@ -69,8 +69,8 @@ entity disturb2_unb2b_sdp_station_full is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
@@ -86,9 +86,9 @@ entity disturb2_unb2b_sdp_station_full is
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
-- ring transceivers
- RinG_0_RX : IN std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ RinG_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
RING_0_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
- RinG_1_RX : IN std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
+ RinG_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
-- back transceivers (note only 6 are used in unb2b)
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg.vhd
index 5a4fa25243d5e4f54122f4e002efd55f691e27b5..602eb5680a99ce8dec6aeb6dd01aa3ade329a12f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg.vhd
@@ -74,8 +74,8 @@ entity disturb2_unb2b_sdp_station_full_wg is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
@@ -92,9 +92,9 @@ entity disturb2_unb2b_sdp_station_full_wg is
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
-- ring transceivers
- RinG_0_RX : IN std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ RinG_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
RING_0_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
- RinG_1_RX : IN std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
+ RinG_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0)
);
end disturb2_unb2b_sdp_station_full_wg;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc.vhd
index 684bd6000544dcf86e22dfeeabd4868f96ba2e05..88e3f0565d5dde353dd983593188d0fac8dcae21 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc.vhd
@@ -69,8 +69,8 @@ entity lofar2_unb2b_sdp_station_adc is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf.vhd
index fb906fb14786bb37e1a939ddea6dbd0fcca3c0f7..aed466964144a593b3eaac09686016ad52c6eb30 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf.vhd
@@ -69,8 +69,8 @@ entity lofar2_unb2b_sdp_station_bf is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd
index a3c5873fc7a56c54a5e86da05aa8602e8cfa12b5..2af60e7192c108df1012bd139a236fb979516d51 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd
@@ -993,8 +993,8 @@ begin
-- g_sp = Y --> w_yy --> beamlet Y = c_exp_beamlet_bst
--
for u in 0 to c_sdp_N_beamsets - 1 loop
- assert pol_beamlet_bst_x_arr(u) > c_stat_lo_factor * c_exp_beamlet_bst report "Wrong beamlet power for X in beamset " & natural'image(u) severity ERROR;
- assert pol_beamlet_bst_x_arr(u) < c_stat_hi_factor * c_exp_beamlet_bst report "Wrong beamlet power for X in beamset " & natural'image(u) severity ERROR;
+ assert pol_beamlet_bst_x_arr(u) > c_stat_lo_factor * c_exp_beamlet_bst report "Wrong beamlet power for x in beamset " & natural'image(u) severity ERROR;
+ assert pol_beamlet_bst_x_arr(u) < c_stat_hi_factor * c_exp_beamlet_bst report "Wrong beamlet power for x in beamset " & natural'image(u) severity ERROR;
assert pol_beamlet_bst_Y_arr(u) > c_stat_lo_factor * c_exp_beamlet_bst report "Wrong beamlet power for Y in beamset " & natural'image(u) severity ERROR;
assert pol_beamlet_bst_Y_arr(u) < c_stat_hi_factor * c_exp_beamlet_bst report "Wrong beamlet power for Y in beamset " & natural'image(u) severity ERROR;
end loop;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub.vhd
index a753496769310acd59721b849df7d918c4146a07..c137ccaf1c017286676f752479a549f750edb3c5 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub.vhd
@@ -69,8 +69,8 @@ entity lofar2_unb2b_sdp_station_fsub is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd
index bef8ee9624c5412966503f4ad5b59fee50bcbd8b..1ea8c68722d33bbfc348b336371e179472032c2f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd
@@ -69,8 +69,8 @@ entity lofar2_unb2b_sdp_station_full is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
@@ -86,9 +86,9 @@ entity lofar2_unb2b_sdp_station_full is
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
-- ring transceivers
- RinG_0_RX : IN std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ RinG_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
RING_0_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
- RinG_1_RX : IN std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
+ RinG_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
-- back transceivers (note only 6 are used in unb2b)
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg.vhd
index 2006e0b2493b27a177df3a19164bdc07f9e3ac64..2f25575b4fadd80ea3c254272ab4d266922603c2 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg.vhd
@@ -69,8 +69,8 @@ entity lofar2_unb2b_sdp_station_full_wg is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
@@ -87,9 +87,9 @@ entity lofar2_unb2b_sdp_station_full_wg is
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
-- ring transceivers
- RinG_0_RX : IN std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ RinG_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
RING_0_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
- RinG_1_RX : IN std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
+ RinG_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0)
);
end lofar2_unb2b_sdp_station_full_wg;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd
index 017b951451200f1becc262deca5c5bb7f8f3d6aa..273254fdcdd1dee6370c5710dd2e5f9c4ed97f26 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd
@@ -69,8 +69,8 @@ entity lofar2_unb2b_sdp_station_xsub_one is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring.vhd
index 31ec29b7552677048d44cca127691ad0eb2b4ebe..682b4637814b35bb9a15f39b6c5d9f62990d67d0 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring.vhd
@@ -69,8 +69,8 @@ entity lofar2_unb2b_sdp_station_xsub_ring is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
@@ -86,9 +86,9 @@ entity lofar2_unb2b_sdp_station_xsub_ring is
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
-- ring transceivers
- RinG_0_RX : IN std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ RinG_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
RING_0_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
- RinG_1_RX : IN std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
+ RinG_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
-- back transceivers (note only 6 are used in unb2b)
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
index 3c1235a7853801b060ce6cf045f299e694584e08..0e51d9af3d96678d537eea05eddc8b2da99c3575 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
@@ -83,8 +83,8 @@ entity lofar2_unb2b_sdp_station is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
@@ -100,9 +100,9 @@ entity lofar2_unb2b_sdp_station is
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
-- ring transceivers
- RinG_0_RX : IN std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ RinG_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
RING_0_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
- RinG_1_RX : IN std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
+ RinG_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
-- back transceivers (Note: numbered from 0)
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd
index 8860c96234911183d0dfcd2591b44d17408a037b..504a287931bde788b8cf3fd402d2fff3c790f04b 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd
@@ -78,4 +78,4 @@ package body lofar2_unb2b_sdp_station_pkg is
end;
-end lofar2_unb2b_sdp_station_pkg;
+end lofar2_unb2b_sdp_station_pkg;
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
index 3c85d590cc5c816b108846b3f5a57955ba3e7fba..97a07112a4f1e6098e16f169823893ee47f2c8cc 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
@@ -577,4 +577,4 @@ package qsys_lofar2_unb2b_sdp_station_pkg is
rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
);
end component qsys_lofar2_unb2b_sdp_station;
-end qsys_lofar2_unb2b_sdp_station_pkg;
+end qsys_lofar2_unb2b_sdp_station_pkg;
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd
index d95e2b16b28654892cae7cc3d97114af5c427ebd..99e0601a724bc6fdf60015352db4808a91220182 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd
@@ -63,8 +63,8 @@ entity lofar2_unb2c_ddrctrl is
-- 1GbE Control Interface
ETH_CLK : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGin : IN std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
@@ -73,7 +73,7 @@ entity lofar2_unb2c_ddrctrl is
--MB_II_REF_CLK : IN STD_LOGIC := '0'; -- Reference clock for MB_II
-- SO-DIMM Memory Bank I
- MB_I_in : IN t_tech_ddr4_phy_in := c_tech_ddr4_phy_in_x;
+ MB_I_in : in t_tech_ddr4_phy_in := c_tech_ddr4_phy_in_x;
MB_I_IO : inout t_tech_ddr4_phy_io;
MB_I_OU : out t_tech_ddr4_phy_ou
@@ -760,4 +760,4 @@ begin
QSFP_LED => QSFP_LED
);
-end str;
+end str;
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/lofar2_unb2c_filterbank_full.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/lofar2_unb2c_filterbank_full.vhd
index ae74c3c55d40c761f3794bc36e7fc505a904dd90..aace61a91f5ec975593878d7bcaa322917bc99b1 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/lofar2_unb2c_filterbank_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/lofar2_unb2c_filterbank_full.vhd
@@ -69,8 +69,8 @@ entity lofar2_unb2c_filterbank_full is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic; --STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
- ETH_SGout : OUT std_logic; --STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ ETH_SGin : in std_logic; --STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ ETH_SGout : out std_logic; --STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/lofar2_unb2c_filterbank_full_256MHz.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/lofar2_unb2c_filterbank_full_256MHz.vhd
index a7c322eb628437c8bea904547710ee4bc0581299..f2ceb9c9bb2322a09c8a5ba92040f55c48e631dd 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/lofar2_unb2c_filterbank_full_256MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/lofar2_unb2c_filterbank_full_256MHz.vhd
@@ -69,8 +69,8 @@ entity lofar2_unb2c_filterbank_full_256MHz is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic; --_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
- ETH_SGout : OUT std_logic; --_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ ETH_SGin : in std_logic; --_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ ETH_SGout : out std_logic; --_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank.vhd
index cc451c9bd42f26177f83491e0a7a46263713a481..2eb5e37049d826224974a0041481020f3b8b0074 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank.vhd
@@ -79,8 +79,8 @@ entity lofar2_unb2c_filterbank is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic; --STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
- ETH_SGout : OUT std_logic; --STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ ETH_SGin : in std_logic; --STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ ETH_SGout : out std_logic; --STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank_pkg.vhd
index ed782862d3984e6a3449f251df9776d4752c6c7f..8fb31e760c3685dcf6b4746f90c50ce1d7974cbb 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank_pkg.vhd
@@ -60,4 +60,4 @@ package body lofar2_unb2c_filterbank_pkg is
end;
-end lofar2_unb2c_filterbank_pkg;
+end lofar2_unb2c_filterbank_pkg;
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/qsys_lofar2_unb2c_filterbank_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/qsys_lofar2_unb2c_filterbank_pkg.vhd
index 8907d2e3d037a53efa6b45db8e6390b0e7ab5b29..d835425fe3e5d712e4b15c8a7fb383311b797510 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/qsys_lofar2_unb2c_filterbank_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/qsys_lofar2_unb2c_filterbank_pkg.vhd
@@ -283,4 +283,4 @@ package qsys_lofar2_unb2c_filterbank_pkg is
rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
);
end component qsys_lofar2_unb2c_filterbank;
-end qsys_lofar2_unb2c_filterbank_pkg;
+end qsys_lofar2_unb2c_filterbank_pkg;
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/lofar2_unb2c_ring_full.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/lofar2_unb2c_ring_full.vhd
index de4a2c9adcbe391abd3e054fe28e73e03d56ced0..7acefe5385547f891feb10515d97031f20e26693 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/lofar2_unb2c_ring_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/lofar2_unb2c_ring_full.vhd
@@ -61,8 +61,8 @@ entity lofar2_unb2c_ring_full is
-- 1GbE Control Interface
ETH_CLK : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGin : IN std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
@@ -72,9 +72,9 @@ entity lofar2_unb2c_ring_full is
QSFP_0_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
-- ring transceivers
- RinG_0_RX : IN std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ RinG_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
RING_0_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
- RinG_1_RX : IN std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
+ RinG_1_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
-- LEDs
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/lofar2_unb2c_ring_one.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/lofar2_unb2c_ring_one.vhd
index baf1916783f1f1ca0b5b4f1ed9042b35b5e29a8c..276f10568b314090889f25e15ca2b439b4924829 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/lofar2_unb2c_ring_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/lofar2_unb2c_ring_one.vhd
@@ -64,8 +64,8 @@ entity lofar2_unb2c_ring_one is
-- 1GbE Control Interface
ETH_CLK : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGin : IN std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
@@ -75,9 +75,9 @@ entity lofar2_unb2c_ring_one is
QSFP_0_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
-- ring transceivers
- RinG_0_RX : IN std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ RinG_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
RING_0_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
- RinG_1_RX : IN std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
+ RinG_1_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
-- LEDs
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring.vhd
index e04b0c5dd6653994fc4f362e95bc903a4ad87c46..ed47f2b098ec4779c84749dd811f3774dc0cba73 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring.vhd
@@ -73,8 +73,8 @@ entity lofar2_unb2c_ring is
-- 1GbE Control Interface
ETH_CLK : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGin : IN std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
@@ -83,9 +83,9 @@ entity lofar2_unb2c_ring is
QSFP_0_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
-- ring transceivers
- RinG_0_RX : IN std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ RinG_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
RING_0_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
- RinG_1_RX : IN std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
+ RinG_1_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
-- LEDs
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring_pkg.vhd
index 8aef3ccd31ba63ae1ba43dd0ee118ab9ceaa7810..4a6cfe862a6536d1fd596191403de9f2e7df2392 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring_pkg.vhd
@@ -56,4 +56,4 @@ package body lofar2_unb2c_ring_pkg is
end;
-end lofar2_unb2c_ring_pkg;
+end lofar2_unb2c_ring_pkg;
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/qsys_lofar2_unb2c_ring_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/qsys_lofar2_unb2c_ring_pkg.vhd
index 030a05126f752d64cd43e0b4ce165390affd0ab3..51e1e18aba8a3c582c523e63fc4c9fb42e63df35 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/qsys_lofar2_unb2c_ring_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/qsys_lofar2_unb2c_ring_pkg.vhd
@@ -228,4 +228,4 @@ package qsys_lofar2_unb2c_ring_pkg is
rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
);
end component qsys_lofar2_unb2c_ring;
-end qsys_lofar2_unb2c_ring_pkg;
+end qsys_lofar2_unb2c_ring_pkg;
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full.vhd
index aac114f9e30edcef02869c4b1fea3d252b6d40bd..f8e441e5dab92b84b54dc2a1c07f76bf8a83c2fe 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full.vhd
@@ -61,8 +61,8 @@ entity disturb2_unb2c_sdp_station_full is
-- 1GbE Control Interface
ETH_CLK : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGin : IN std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
@@ -78,9 +78,9 @@ entity disturb2_unb2c_sdp_station_full is
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
-- ring transceivers
- RinG_0_RX : IN std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ RinG_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
RING_0_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
- RinG_1_RX : IN std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
+ RinG_1_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
-- back transceivers (note only 12 are used in unb2c)
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg.vhd
index 13574e50d18793aaa7563488d288a3ace92d3501..59d8bc66e09657984021f64629e0b28374956811 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg.vhd
@@ -61,8 +61,8 @@ entity disturb2_unb2c_sdp_station_full_wg is
-- 1GbE Control Interface
ETH_CLK : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGin : IN std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
@@ -78,9 +78,9 @@ entity disturb2_unb2c_sdp_station_full_wg is
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
-- ring transceivers
- RinG_0_RX : IN std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ RinG_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
RING_0_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
- RinG_1_RX : IN std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
+ RinG_1_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0)
);
end disturb2_unb2c_sdp_station_full_wg;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd
index 57ae9b3a6054fa8f1c1576b1432c961be4516033..56ab74b8ea763ad4fd1062371ae48d0a70d39d44 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd
@@ -61,8 +61,8 @@ entity lofar2_unb2c_sdp_station_adc is
-- 1GbE Control Interface
ETH_CLK : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGin : IN std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd
index 0c40049edf3abdf967b79a134518ca68b44b3c48..8b224926a57bdd566cefdee30c8f93f22dd9f546 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd
@@ -61,8 +61,8 @@ entity lofar2_unb2c_sdp_station_bf is
-- 1GbE Control Interface
ETH_CLK : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGin : IN std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring.vhd
index d9d847fc3d5bfc5819037372ffce0b9d6e325d59..4d435fb0d3eaaee2776ffea7d6f167f3cd0726bf 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring.vhd
@@ -61,8 +61,8 @@ entity lofar2_unb2c_sdp_station_bf is
-- 1GbE Control Interface
ETH_CLK : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGin : IN std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
@@ -80,9 +80,9 @@ entity lofar2_unb2c_sdp_station_bf is
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
-- ring transceivers
- RinG_0_RX : IN std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ RinG_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
RING_0_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
- RinG_1_RX : IN std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
+ RinG_1_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd
index 652c5b8bfe25807cb6dfcdc04a413ae521efb29d..50debd5f1efcfecde2e172d0c4e238289c4e615a 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd
@@ -61,8 +61,8 @@ entity lofar2_unb2c_sdp_station_fsub is
-- 1GbE Control Interface
ETH_CLK : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGin : IN std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd
index 9eb7f059475658365c76ed91079ad2ee5aa80bff..1fc1aea0cff75b3f41722dbc2919f79442a3d6bb 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd
@@ -61,8 +61,8 @@ entity lofar2_unb2c_sdp_station_full is
-- 1GbE Control Interface
ETH_CLK : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGin : IN std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
@@ -78,9 +78,9 @@ entity lofar2_unb2c_sdp_station_full is
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
-- ring transceivers
- RinG_0_RX : IN std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ RinG_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
RING_0_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
- RinG_1_RX : IN std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
+ RinG_1_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
-- back transceivers (note only 12 are used in unb2c)
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg.vhd
index 9c87d6ec61f33fa3f3e85cf3ffbc5b32209c5a7c..112f7fd1572f09c1f1865c8575feaa93933f1492 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg.vhd
@@ -61,8 +61,8 @@ entity lofar2_unb2c_sdp_station_full_wg is
-- 1GbE Control Interface
ETH_CLK : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGin : IN std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
@@ -78,9 +78,9 @@ entity lofar2_unb2c_sdp_station_full_wg is
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
-- ring transceivers
- RinG_0_RX : IN std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ RinG_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
RING_0_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
- RinG_1_RX : IN std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
+ RinG_1_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0)
);
end lofar2_unb2c_sdp_station_full_wg;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd
index c4e17b7ddc88c0fd59c2d00b26c66b2d4e281984..d1f73f81764057bc409d1dfbb7a15227655f190d 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd
@@ -61,8 +61,8 @@ entity lofar2_unb2c_sdp_station_xsub_one is
-- 1GbE Control Interface
ETH_CLK : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGin : IN std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring.vhd
index a8b39e86ca74934d58704880873bdae246d8df24..076135ab2485c270ad10d158323ae3a95702571f 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring.vhd
@@ -61,8 +61,8 @@ entity lofar2_unb2c_sdp_station_xsub_ring is
-- 1GbE Control Interface
ETH_CLK : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGin : IN std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
@@ -78,9 +78,9 @@ entity lofar2_unb2c_sdp_station_xsub_ring is
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
-- ring transceivers
- RinG_0_RX : IN std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ RinG_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
RING_0_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
- RinG_1_RX : IN std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
+ RinG_1_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
-- back transceivers (note only 12 are used in unb2c)
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
index ff4b73b2907a757ce558526b20d214d6a960e564..b4c19309e4200cd28a473e7676046dbf8b4b8700 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
@@ -74,8 +74,8 @@ entity lofar2_unb2c_sdp_station is
-- 1GbE Control Interface
ETH_CLK : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGin : IN std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
@@ -89,9 +89,9 @@ entity lofar2_unb2c_sdp_station is
QSFP_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
-- ring transceivers
- RinG_0_RX : IN std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ RinG_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
RING_0_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
- RinG_1_RX : IN std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
+ RinG_1_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
-- LEDs
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd
index d34840b772c38e70f09c0f8e05e8e330cbb12d35..193fb753eddc671a83c39fa5db9e6f0480c1a0fe 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd
@@ -78,4 +78,4 @@ package body lofar2_unb2c_sdp_station_pkg is
end;
-end lofar2_unb2c_sdp_station_pkg;
+end lofar2_unb2c_sdp_station_pkg;
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
index a1bc5e5a3783ada758d2f828631512252ab7e07e..50c338f2b7c4b2e6b7a4de2b9bf1d9ac6c0473c8 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
@@ -563,4 +563,4 @@ package qsys_lofar2_unb2c_sdp_station_pkg is
ram_equalizer_gains_cross_readdata_export : in std_logic_vector(31 downto 0) := (others => 'x') -- export
);
end component qsys_lofar2_unb2c_sdp_station;
-end qsys_lofar2_unb2c_sdp_station_pkg;
+end qsys_lofar2_unb2c_sdp_station_pkg;
\ No newline at end of file
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index 21d1566665aafa47aaef94c796b8cbd7dd7e6163..3b39a07fdc59d3b474f17f04252c01429f47a922 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -284,7 +284,7 @@ package sdp_pkg is
-- hdr_fields_in_arr with all 0. Hence e.g. udp_checksum = 0 can be achieve via data path
-- and default hdr_fields_in_arr = 0 or via MM controlled and field_default(0).
-- eth ip udp app
- constant c_sdp_stat_hdr_field_sel : std_logic_vector(c_sdp_stat_nof_hdr_fields - 1 downto 0) := "1" &"101 " &"111011111001 " &"0100 " &"0100 " &"00000000 " &"1000000 " &"0 "; -- current
+ constant c_sdp_stat_hdr_field_sel : std_logic_vector(c_sdp_stat_nof_hdr_fields - 1 downto 0) := "1" &"101 " &"111011111001 " &"0100 " &"0100 " &"00000000 " &"1000000 " &"0 "; -- current
--CONSTANT c_sdp_stat_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_stat_nof_hdr_fields-1 DOWNTO 0) := "1"&"101"&"111011111001"&"0101"&"0100"&"00000000"&"0000100"&"0"; -- previous 26 nov 2021
--CONSTANT c_sdp_stat_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_stat_nof_hdr_fields-1 DOWNTO 0) := "0"&"100"&"000000010001"&"0100"&"0100"&"00000000"&"1000000"&"0"; -- initial
@@ -410,14 +410,14 @@ package sdp_pkg is
constant c_sdp_cep_payload_nof_longwords : natural := c_sdp_cep_nof_blocks_per_packet * c_sdp_cep_nof_beamlets_per_block / c_sdp_cep_nof_beamlets_per_longword; -- = 976
constant c_sdp_cep_packet_nof_longwords : natural := ceil_div(c_sdp_cep_header_len, c_longword_sz) + c_sdp_cep_payload_nof_longwords; -- without tail CRC, the CRC is applied by 10GbE MAC
- constant c_sdp_cep_nof_hdr_fields : natural := 3 +12 + 4 + 4 + 9 + 6 + 1; -- c_sdp_cep_header_len / c_longword_sz = 74 / 8 = 9.25 64b words = 592b
+ constant c_sdp_cep_nof_hdr_fields : natural := 3 + 12 + 4 + 4 + 9 + 6 + 1; -- c_sdp_cep_header_len / c_longword_sz = 74 / 8 = 9.25 64b words = 592b
-- hdr_field_sel bit selects where the hdr_field value is set:
-- . 0 = data path controlled, value is set in sdp_beamformer_output.vhd, so field_default() is not used.
-- . 1 = MM controlled, value is set via MM or by the field_default(), so any data path setting in
-- sdp_beamformer_output.vhd is not used.
-- Remarks: see remarks at c_sdp_stat_nof_hdr_fields.
-- eth ip udp app
- constant c_sdp_cep_hdr_field_sel : std_logic_vector(c_sdp_cep_nof_hdr_fields - 1 downto 0) := "111" &"111111111011 " &"1110 " &"1100 " &"100000010 " &"100110 " &"0 "; -- current
+ constant c_sdp_cep_hdr_field_sel : std_logic_vector(c_sdp_cep_nof_hdr_fields - 1 downto 0) := "111" &"111111111011 " &"1110 " &"1100 " &"100000010 " &"100110 " &"0 "; -- current
--CONSTANT c_sdp_cep_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_cep_nof_hdr_fields-1 DOWNTO 0) := "101"&"111111111001"&"0111"&"1100"&"100000010"&"000110"&"0"; -- previous 27 sep 2022
--CONSTANT c_sdp_cep_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_cep_nof_hdr_fields-1 DOWNTO 0) := "100"&"000000010001"&"0100"&"0100"&"100000000"&"101000"&"0"; -- initial
@@ -718,53 +718,53 @@ package body sdp_pkg is
constant c_marker_bst : natural := 66; -- = 0x42 = 'B'
constant c_marker_xst : natural := 88; -- = 0x58 = 'X'
begin
- return sel_a_b(g_statistics_type ="BST ", c_marker_bst,
- sel_a_b(g_statistics_type ="XST ", c_marker_xst,
+ return sel_a_b(g_statistics_type ="BST ", c_marker_bst,
+ sel_a_b(g_statistics_type ="XST ", c_marker_xst,
c_marker_sst)); -- SST, SST_OS
end func_sdp_get_stat_marker;
function func_sdp_get_stat_nof_signal_inputs(g_statistics_type : string) return natural is
begin
- return sel_a_b(g_statistics_type ="BST ", 0, -- not applicable for BST, so use 0,
- sel_a_b(g_statistics_type ="XST ", c_sdp_S_pn,
+ return sel_a_b(g_statistics_type ="BST ", 0, -- not applicable for BST, so use 0,
+ sel_a_b(g_statistics_type ="XST ", c_sdp_S_pn,
1)); -- SST, SST_OS
end func_sdp_get_stat_nof_signal_inputs;
function func_sdp_get_stat_from_mm_user_size(g_statistics_type : string) return natural is
-- see sdp_statistics_offload.vhd for description
begin
- return sel_a_b(g_statistics_type ="BST ", c_sdp_W_statistic_sz, -- = 2, so preserve X, Y order
- sel_a_b(g_statistics_type ="XST ", c_sdp_W_statistic_sz, -- = 2, so preserve Re, Im order
+ return sel_a_b(g_statistics_type ="BST ", c_sdp_W_statistic_sz, -- = 2, so preserve X, Y order
+ sel_a_b(g_statistics_type ="XST ", c_sdp_W_statistic_sz, -- = 2, so preserve Re, Im order
c_sdp_W_statistic_sz)); -- = 2, SST, SST_OS
end func_sdp_get_stat_from_mm_user_size;
function func_sdp_get_stat_from_mm_data_size(g_statistics_type : string) return natural is
begin
- return sel_a_b(g_statistics_type ="BST ", c_sdp_N_pol_bf * c_sdp_W_statistic_sz, -- = 4
- sel_a_b(g_statistics_type ="XST ", c_nof_complex * c_sdp_W_statistic_sz, -- = 4
+ return sel_a_b(g_statistics_type ="BST ", c_sdp_N_pol_bf * c_sdp_W_statistic_sz, -- = 4
+ sel_a_b(g_statistics_type ="XST ", c_nof_complex * c_sdp_W_statistic_sz, -- = 4
c_sdp_W_statistic_sz)); -- = 2, SST, SST_OS
end func_sdp_get_stat_from_mm_data_size;
function func_sdp_get_stat_from_mm_step_size(g_statistics_type : string) return natural is
constant c_data_size : natural := func_sdp_get_stat_from_mm_data_size(g_statistics_type);
begin
- return sel_a_b(g_statistics_type ="BST ", c_data_size, -- = 4
- sel_a_b(g_statistics_type ="XST ", c_data_size, -- = 4
+ return sel_a_b(g_statistics_type ="BST ", c_data_size, -- = 4
+ sel_a_b(g_statistics_type ="XST ", c_data_size, -- = 4
c_data_size * c_sdp_Q_fft)); -- = 4, SST, SST_OS
end func_sdp_get_stat_from_mm_step_size;
function func_sdp_get_stat_from_mm_nof_data(g_statistics_type : string) return natural is
begin
- return sel_a_b(g_statistics_type ="BST ", c_sdp_S_sub_bf, -- = 488
- sel_a_b(g_statistics_type ="XST ", c_sdp_X_sq, -- = 144
+ return sel_a_b(g_statistics_type ="BST ", c_sdp_S_sub_bf, -- = 488
+ sel_a_b(g_statistics_type ="XST ", c_sdp_X_sq, -- = 144
c_sdp_N_sub)); -- = 512, SST, SST_OS
end func_sdp_get_stat_from_mm_nof_data;
-- nof_statistics_per_packet = mm_nof_data * mm_data_size / c_sdp_W_statistic_sz
function func_sdp_get_stat_nof_statistics_per_packet(g_statistics_type : string) return natural is
begin
- return sel_a_b(g_statistics_type ="BST ", c_sdp_S_sub_bf * c_sdp_N_pol_bf, -- = 976
- sel_a_b(g_statistics_type ="XST ", c_sdp_X_sq * c_nof_complex, -- = 288
+ return sel_a_b(g_statistics_type ="BST ", c_sdp_S_sub_bf * c_sdp_N_pol_bf, -- = 976
+ sel_a_b(g_statistics_type ="XST ", c_sdp_X_sq * c_nof_complex, -- = 288
c_sdp_N_sub)); -- = 512, SST, SST_OS
end func_sdp_get_stat_nof_statistics_per_packet;
@@ -801,16 +801,16 @@ package body sdp_pkg is
function func_sdp_get_stat_udp_src_port(g_statistics_type : string; gn_index : natural) return std_logic_vector is
constant c_gn_index : std_logic_vector(7 downto 0) := to_uvec(gn_index, 8);
begin
- return sel_a_b(g_statistics_type ="BST ", c_sdp_bst_udp_src_port_15_8 & c_gn_index, -- BST = 0xD1 & gn_index
- sel_a_b(g_statistics_type ="XST ", c_sdp_xst_udp_src_port_15_8 & c_gn_index, -- XST = 0xD2 & gn_index
+ return sel_a_b(g_statistics_type ="BST ", c_sdp_bst_udp_src_port_15_8 & c_gn_index, -- BST = 0xD1 & gn_index
+ sel_a_b(g_statistics_type ="XST ", c_sdp_xst_udp_src_port_15_8 & c_gn_index, -- XST = 0xD2 & gn_index
c_sdp_sst_udp_src_port_15_8 & c_gn_index)); -- SST = 0xD0 & gn_index, SST_OS
end func_sdp_get_stat_udp_src_port;
function func_sdp_get_stat_nof_packets(g_statistics_type : string; S_pn, P_sq, N_crosslets : natural) return natural is
begin
- return sel_a_b(g_statistics_type ="BST ", 1,
- sel_a_b(g_statistics_type ="XST ", P_sq * N_crosslets,
- sel_a_b(g_statistics_type ="SST ", S_pn,
+ return sel_a_b(g_statistics_type ="BST ", 1,
+ sel_a_b(g_statistics_type ="XST ", P_sq * N_crosslets,
+ sel_a_b(g_statistics_type ="SST ", S_pn,
c_sdp_R_os * S_pn))); -- SST_OS
end func_sdp_get_stat_nof_packets;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
index 0b31b2cce8efb115931da2488df758625554fe51..64dd15a78ce386ab863a5bb9d35b09d728a74891 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
@@ -353,11 +353,11 @@ entity sdp_station is
-- RING_0 serial
RING_0_TX : out std_logic_vector(c_quad - 1 downto 0) := (others => '0');
- RinG_0_RX : IN std_logic_vector(c_quad - 1 downto 0) := (others => '0');
+ RinG_0_RX : in std_logic_vector(c_quad - 1 downto 0) := (others => '0');
-- RING_1 serial
RING_1_TX : out std_logic_vector(c_quad - 1 downto 0) := (others => '0');
- RinG_1_RX : IN std_logic_vector(c_quad - 1 downto 0) := (others => '0');
+ RinG_1_RX : in std_logic_vector(c_quad - 1 downto 0) := (others => '0');
----------------------------------------------
-- nw 10 GbE for beamlet output
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
index 65bc69fb54e5b0d5f0cc14301b0a63bb0243c25d..1c70e2514e07480cf7c53dc277c85b7fdd04d2d4 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
@@ -85,8 +85,8 @@ entity top is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
@@ -96,9 +96,9 @@ entity top is
QSFP_0_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
-- ring transceivers
- RinG_0_RX : IN std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
+ RinG_0_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0'); -- Using qsfp bus width also for ring interfaces
RING_0_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
- RinG_1_RX : IN std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
+ RinG_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
-- LEDs
@@ -1522,4 +1522,4 @@ begin
reg_ta2_unb2b_mm_io_waitrequest_export => reg_ta2_unb2b_mm_io_miso.waitrequest
);
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd
index 831efdd9316ef8d0e6b3ddbf4d5d8b3fa437fecf..cb65f2ef189f5e4a1c49c5099c7bf55170e3e364 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd
@@ -468,5 +468,4 @@ package top_components_pkg is
);
end component freeze_wrapper;
-end top_components_pkg;
-
+end top_components_pkg;
\ No newline at end of file
diff --git a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd
index 61abaf7b2d9a0aa1e774b02c226ab7afcb954b9d..25a59aff30c57bd16fbac1e9f8033e2f5c3dca03 100644
--- a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd
+++ b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd
@@ -82,8 +82,8 @@ entity top is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
@@ -99,9 +99,9 @@ entity top is
QSFP_1_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
-- ring transceivers
- RinG_0_RX : IN std_logic_vector(c_unb2b_board_tr_ring.bus_w - 1 downto 0) := (others => '0');
+ RinG_0_RX : in std_logic_vector(c_unb2b_board_tr_ring.bus_w - 1 downto 0) := (others => '0');
RING_0_TX : out std_logic_vector(c_unb2b_board_tr_ring.bus_w - 1 downto 0);
- RinG_1_RX : IN std_logic_vector(c_unb2b_board_tr_ring.bus_w - 1 downto 0) := (others => '0');
+ RinG_1_RX : in std_logic_vector(c_unb2b_board_tr_ring.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_ring.bus_w - 1 downto 0);
-- back transceivers
@@ -113,7 +113,7 @@ entity top is
JESD204B_SYNC : out std_logic_vector(0 downto 0);
-- SO-DIMM Memory Bank I
- MB_I_in : IN t_tech_ddr4_phy_in := c_tech_ddr4_phy_in_x;
+ MB_I_in : in t_tech_ddr4_phy_in := c_tech_ddr4_phy_in_x;
MB_I_IO : inout t_tech_ddr4_phy_io;
MB_I_OU : out t_tech_ddr4_phy_ou;
@@ -1046,4 +1046,4 @@ begin
);
-end str;
+end str;
\ No newline at end of file
diff --git a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top_components_pkg.vhd b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top_components_pkg.vhd
index b4b415bc1699a23b644f77d4d4b39924cde4b7d1..8a51bc11977d58239f37b33388811889a4cc5242 100644
--- a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top_components_pkg.vhd
+++ b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top_components_pkg.vhd
@@ -304,5 +304,4 @@ package top_components_pkg is
);
end component freeze_wrapper;
-end top_components_pkg;
-
+end top_components_pkg;
\ No newline at end of file
diff --git a/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd b/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
index 75990e9c1856cb966b5a8f9784a88e04d6c5e39d..49b752b3c1c9eeb888de28fe0c4bd8e486f1179b 100644
--- a/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
+++ b/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
@@ -188,7 +188,7 @@ begin
-- Reverse byte order
gen_reverse_rx_bytes : if g_reverse_bytes generate
gen_rx_bytes : for I in 0 to g_nof_bytes - 1 generate
- kernel_src_out_arr(stream).data(c_byte_w * (g_nof_bytes - I) - 1 downto c_byte_w * (g_nof_bytes - 1 -I)) <= dp_latency_adapter_tx_src_out_arr(stream).data(c_byte_w*(I+1)-1 downto c_byte_w*I);
+ kernel_src_out_arr(stream).data(c_byte_w * (g_nof_bytes - I) - 1 downto c_byte_w * (g_nof_bytes - 1 - I)) <= dp_latency_adapter_tx_src_out_arr(stream).data(c_byte_w * (I + 1) - 1 downto c_byte_w * I);
end generate;
end generate;
gen_no_reverse_rx_bytes : if not g_reverse_bytes generate
@@ -224,7 +224,7 @@ begin
-- Reverse byte order to correct for endianess
gen_reverse_tx_bytes : if g_reverse_bytes generate
gen_tx_bytes : for I in 0 to g_nof_bytes - 1 generate
- dp_latency_adapter_rx_snk_in_arr(stream).data(c_byte_w * (g_nof_bytes - I) - 1 downto c_byte_w * (g_nof_bytes - 1 -I)) <= kernel_snk_in_arr(stream).data(c_byte_w*(I+1) -1 downto c_byte_w*I);
+ dp_latency_adapter_rx_snk_in_arr(stream).data(c_byte_w * (g_nof_bytes - I) - 1 downto c_byte_w * (g_nof_bytes - 1 - I)) <= kernel_snk_in_arr(stream).data(c_byte_w * (I + 1) - 1 downto c_byte_w * I);
end generate;
end generate;
gen_no_reverse_tx_bytes : if not g_reverse_bytes generate
@@ -303,4 +303,4 @@ begin
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd b/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
index 379add9714637bd230c7424243182683f0312fd3..7e6d313423031a3dd2daf2b9d1a9ef5949b58d1f 100644
--- a/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
+++ b/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
@@ -374,4 +374,4 @@ begin
);
-end str;
+end str;
\ No newline at end of file
diff --git a/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.vhd b/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.vhd
index 93b0eca3cc00c5047f9207ed648e34bba60711f3..1704ba015db890b32778d9a04a9ab45e7eef76cf 100644
--- a/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.vhd
+++ b/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.vhd
@@ -244,4 +244,4 @@ begin
dp_latency_adapter_rx_src_in.xon <= '1';
-end str;
+end str;
\ No newline at end of file
diff --git a/applications/ta2/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd b/applications/ta2/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd
index 7e9a94cbebdcd666b738db3e41f87419c896f314..fcc99b8025be9f7e4425b07d397148dad6d92609 100644
--- a/applications/ta2/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd
+++ b/applications/ta2/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd
@@ -589,4 +589,4 @@ begin
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/applications/ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.vhd b/applications/ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.vhd
index 6d0ee5e241a4ea53ce4fa1e30563e280d37bfb33..688f2fe7fae130a67389abc2f7b5a631be14f964 100644
--- a/applications/ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.vhd
+++ b/applications/ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.vhd
@@ -366,7 +366,7 @@ begin
mb_I_emif_usr_reset <= not mb_I_emif_usr_reset_n;
mb_I_ref_rst_n <= not mb_I_ref_rst;
- gen_I_ip_arria10_e1sg_ddr4_8g_1600 : if g_ddr_MB_I.name ="DDR4 " and c_gigabytes_MB_I = 8 and g_ddr_MB_I.mts = 1600 generate
+ gen_I_ip_arria10_e1sg_ddr4_8g_1600 : if g_ddr_MB_I.name ="DDR4 " and c_gigabytes_MB_I = 8 and g_ddr_MB_I.mts = 1600 generate
u_ip_arria10_e1sg_ddr4_8g_1600 : ip_arria10_e1sg_ddr4_8g_1600
port map (
@@ -498,7 +498,7 @@ begin
mb_II_emif_usr_reset <= not mb_II_emif_usr_reset_n;
mb_II_ref_rst_n <= not mb_II_ref_rst;
- gen_II_ip_arria10_e1sg_ddr4_8g_1600 : if g_ddr_MB_II.name ="DDR4 " and c_gigabytes_MB_II = 8 and g_ddr_MB_II.mts = 1600 generate
+ gen_II_ip_arria10_e1sg_ddr4_8g_1600 : if g_ddr_MB_II.name ="DDR4 " and c_gigabytes_MB_II = 8 and g_ddr_MB_II.mts = 1600 generate
u_ip_arria10_e1sg_ddr4_8g_1600 : ip_arria10_e1sg_ddr4_8g_1600
port map (
@@ -543,4 +543,4 @@ begin
-end str;
+end str;
\ No newline at end of file
diff --git a/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd b/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd
index 0b2b1ddb67d06110b95efef596f490a49dae2a7d..5aa84f26ea945f1e5a31d5c52cab7de1f786dd41 100644
--- a/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd
+++ b/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd
@@ -203,4 +203,4 @@ begin
dp_latency_adapter_rx_src_in_arr(stream).xon <= '1';
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b_ip_wrapper.vhd b/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b_ip_wrapper.vhd
index bfc993a6e2b6ed86d87e6bc1a93e261e68174786..7ab3560c82969de47a450ea49259c78c0b12329c 100644
--- a/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b_ip_wrapper.vhd
+++ b/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b_ip_wrapper.vhd
@@ -116,4 +116,4 @@ begin
kernel_src_ready => kernel_src_ready
);
-end str;
+end str;
\ No newline at end of file
diff --git a/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd b/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd
index e6f0b5068edb4fb1c37b820e098ce3bd4fe3ef87..714b21fb5b78944f7bfeb94088cbb21ea17edbc2 100644
--- a/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd
+++ b/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd
@@ -260,4 +260,4 @@ gen_opencl : if g_use_opencl generate
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/applications/ta2/ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd b/applications/ta2/ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd
index 6ac1f5c59915368ec983fc2a4784c41e970e67a0..2b9350bb852289e569fe257174af12b1e27a255a 100644
--- a/applications/ta2/ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd
+++ b/applications/ta2/ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd
@@ -175,4 +175,4 @@ begin
-end tb;
+end tb;
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture.vhd
index f77e41b17026afa8b0e2ec6ce0c9732e5c693dea..695438230d6148db95ee1f3ddcd5c08c967374f7 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture.vhd
@@ -66,8 +66,8 @@ entity unb1_bn_capture is
-- 1GbE Control Interface
ETH_clk : in std_logic;
- ETH_SGin : IN std_logic;
- ETH_SGout : OUT std_logic;
+ ETH_SGin : in std_logic;
+ ETH_SGout : out std_logic;
-- ADC Interface
ADC_BI_A : in std_logic_vector(c_aduh_dd_ai.port_w - 1 downto 0);
@@ -742,4 +742,4 @@ begin
ADC_CD_SDA => ADC_CD_SDA
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_mux.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_mux.vhd
index 733326a6685531158aa014f366feffd19f41be58..22865a07dbed963384b7c2657b66f9a1dcd79252 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_mux.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_mux.vhd
@@ -112,4 +112,4 @@ begin
src_out => mux_wide_sosi
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage.vhd
index 0b3059ccef8a47d054b013eeb5279c6972a934ea..541838e2edb4dc9e37af32957dc3b3f1e0c54269 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage.vhd
@@ -253,4 +253,4 @@ begin
mm_rd_usedw => mm_rd_usedw
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage_reg.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage_reg.vhd
index 98c741fd942af469baeb308bd3a1b4dcc3fe67e8..c977058a0639b1ef09727970ad9b4cabea9d3f1e 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage_reg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage_reg.vhd
@@ -257,4 +257,4 @@ begin
);
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/unb1_bn_terminal_bg.vhd b/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/unb1_bn_terminal_bg.vhd
index 72d73a86113f1710bab7c36556783427df5c8437..3d63d939f9a07a2084ccdaef2fc090ec2797e747 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/unb1_bn_terminal_bg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/unb1_bn_terminal_bg.vhd
@@ -58,8 +58,8 @@ entity unb1_bn_terminal_bg is
-- 1GbE Control Interface
ETH_clk : in std_logic;
- ETH_SGin : IN std_logic;
- ETH_SGout : OUT std_logic;
+ ETH_SGin : in std_logic;
+ ETH_SGout : out std_logic;
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- TR clock BN-BI (backplane)
@@ -570,5 +570,3 @@ end;
-
-
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd b/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd
index 71213db6d8badbc145f8faac255bf746edd6f562..b86735063ae0828ae0ab2c394e28e823e5e65a99 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd
@@ -352,5 +352,4 @@ begin
back_rx_serial_2arr => back_rx_serial_2arr
);
-end tb;
-
+end tb;
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_tb_node_unb1_bn_terminal_bg.vhd b/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_tb_node_unb1_bn_terminal_bg.vhd
index 2cf29d4dd42d45519b6f4cddfa7e7571291555ac..346afc9013b360f7e7256bc24f9b59787c168f5b 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_tb_node_unb1_bn_terminal_bg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_tb_node_unb1_bn_terminal_bg.vhd
@@ -118,5 +118,4 @@ begin
assert not(NOW > 0 ps and tb_end = '1') report "Note: TB end" severity FAILURE; -- need to use FAILURE to stop the simulation, apparently resetting the tr_nonbonded is not enough
-end tb;
-
+end tb;
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
index c7c63dcee10074a9e968e506773c1e38f0b5fc85..2ca9ea30a918cc7fa24018bf340977c6376d198a 100644
--- a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
@@ -130,7 +130,7 @@ architecture str of mmm_unb1_ddr3 is
constant c_cal_clk_period : time := 25 ns;
constant c_sim_node_type : string(1 to 2) := sel_a_b(g_sim_node_nr <4, "FN", "BN");
- constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type ="BN ", g_sim_node_nr -4, g_sim_node_nr);
+ constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type ="BN ", g_sim_node_nr -4, g_sim_node_nr);
-- PIOs
signal pout_debug_wave : std_logic_vector(c_word_w - 1 downto 0);
@@ -398,5 +398,4 @@ begin
coe_writedata_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.wrdata(c_word_w - 1 downto 0)
);
end generate;
-end str;
-
+end str;
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd
index 744b0767220b8a7721a4dd26b3b1ab5ed8d12ccf..307312a922cc413ae109c1d3cd84be9867a4b8d8 100644
--- a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd
@@ -81,7 +81,7 @@ entity node_unb1_ddr3 is
reg_diag_rx_seq_miso : out t_mem_miso;
-- SO-DIMM Memory Bank I = ddr3_I
- MB_I_in : IN t_tech_ddr3_phy_in;
+ MB_I_in : in t_tech_ddr3_phy_in;
MB_I_IO : inout t_tech_ddr3_phy_io;
MB_I_OU : out t_tech_ddr3_phy_ou
);
@@ -188,4 +188,4 @@ begin
reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
reg_rx_seq_miso => reg_diag_rx_seq_miso
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/unb1_ddr3.vhd
index fc0aafbb282ace70baad567c120ddc183f481ebd..44b8bfdec392c4f69d8ffd5eb576a23094506e36 100644
--- a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/unb1_ddr3.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/unb1_ddr3.vhd
@@ -61,11 +61,11 @@ entity unb1_ddr3 is
-- 1GbE Control Interface
ETH_clk : in std_logic;
- ETH_SGin : IN std_logic;
- ETH_SGout : OUT std_logic;
+ ETH_SGin : in std_logic;
+ ETH_SGout : out std_logic;
-- SO-DIMM Memory Bank I
- MB_I_in : IN t_tech_ddr3_phy_in;
+ MB_I_in : in t_tech_ddr3_phy_in;
MB_I_IO : inout t_tech_ddr3_phy_io;
MB_I_OU : out t_tech_ddr3_phy_ou
);
diff --git a/boards/uniboard1/designs/unb1_ddr3/tb/vhdl/tb_unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/tb/vhdl/tb_unb1_ddr3.vhd
index 655331a823a291fa874487c47c4208584e98a3bf..cec9f6ec68d8e4bb8a2cb5f0f5701cae984e720b 100644
--- a/boards/uniboard1/designs/unb1_ddr3/tb/vhdl/tb_unb1_ddr3.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3/tb/vhdl/tb_unb1_ddr3.vhd
@@ -175,4 +175,4 @@ begin
mem3_ou => MB_I_in
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/unb1_ddr3_reorder_dual_rank.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/unb1_ddr3_reorder_dual_rank.vhd
index 928c5f91c38df503dbd2e227f7977b0561644027..eafdc3f5945aa669022331c30557360980db77f1 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/unb1_ddr3_reorder_dual_rank.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/unb1_ddr3_reorder_dual_rank.vhd
@@ -60,11 +60,11 @@ entity unb1_ddr3_reorder_dual_rank is
-- 1GbE Control Interface
ETH_clk : in std_logic;
- ETH_SGin : IN std_logic;
- ETH_SGout : OUT std_logic;
+ ETH_SGin : in std_logic;
+ ETH_SGout : out std_logic;
-- SO-DIMM Memory Bank I
- MB_I_in : IN t_tech_ddr3_phy_in;
+ MB_I_in : in t_tech_ddr3_phy_in;
MB_I_IO : inout t_tech_ddr3_phy_io;
MB_I_OU : out t_tech_ddr3_phy_ou
);
@@ -109,5 +109,3 @@ begin
end str;
-
-
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/unb1_ddr3_reorder_single_rank.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/unb1_ddr3_reorder_single_rank.vhd
index cde8e2b35a2602488bde2d45ed37832c674ccf5e..697049652a96634bc78bd349727068f730114577 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/unb1_ddr3_reorder_single_rank.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/unb1_ddr3_reorder_single_rank.vhd
@@ -60,11 +60,11 @@ entity unb1_ddr3_reorder_single_rank is
-- 1GbE Control Interface
ETH_clk : in std_logic;
- ETH_SGin : IN std_logic;
- ETH_SGout : OUT std_logic;
+ ETH_SGin : in std_logic;
+ ETH_SGout : out std_logic;
-- SO-DIMM Memory Bank I
- MB_I_in : IN t_tech_ddr3_phy_in;
+ MB_I_in : in t_tech_ddr3_phy_in;
MB_I_IO : inout t_tech_ddr3_phy_io;
MB_I_OU : out t_tech_ddr3_phy_ou
);
@@ -109,5 +109,3 @@ begin
end str;
-
-
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
index 7e1ac52a3d234d0c07868a7ff8af40f5c10c0b4a..211ccbffeb0314305c0fe54bdd741da8cf33f14e 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
@@ -140,7 +140,7 @@ architecture str of mmm_unb1_ddr3_reorder is
constant c_cal_clk_period : time := 25 ns;
constant c_sim_node_type : string(1 to 2) := sel_a_b(g_sim_node_nr <4, "FN", "BN");
- constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type ="BN ", g_sim_node_nr -4, g_sim_node_nr);
+ constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type ="BN ", g_sim_node_nr -4, g_sim_node_nr);
-- PIOs
signal pout_debug_wave : std_logic_vector(c_word_w - 1 downto 0);
@@ -429,4 +429,4 @@ begin
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/node_unb1_ddr3_reorder.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/node_unb1_ddr3_reorder.vhd
index ae51f05bde5793df1f10450f5ff4bb8881e06829..7e35fcbb9389ad68b8001a0d2035280ed79fc7a4 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/node_unb1_ddr3_reorder.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/node_unb1_ddr3_reorder.vhd
@@ -95,7 +95,7 @@ port (
reg_diag_rx_seq_miso : out t_mem_miso;
-- SO-DIMM Memory Bank I
- MB_I_in : IN t_tech_ddr3_phy_in;
+ MB_I_in : in t_tech_ddr3_phy_in;
MB_I_IO : inout t_tech_ddr3_phy_io;
MB_I_OU : out t_tech_ddr3_phy_ou
);
@@ -354,4 +354,4 @@ begin
in_sosi_arr => db_sosi_arr
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/unb1_ddr3_reorder.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/unb1_ddr3_reorder.vhd
index 8b5eb36907de3e450113e6b07eddc522dea970be..3abea63f15254389c1a40c2d26eb632b8baae3da 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/unb1_ddr3_reorder.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/unb1_ddr3_reorder.vhd
@@ -67,11 +67,11 @@ entity unb1_ddr3_reorder is
-- 1GbE Control Interface
ETH_clk : in std_logic;
- ETH_SGin : IN std_logic;
- ETH_SGout : OUT std_logic;
+ ETH_SGin : in std_logic;
+ ETH_SGout : out std_logic;
-- SO-DIMM Memory Bank I
- MB_I_in : IN t_tech_ddr3_phy_in;
+ MB_I_in : in t_tech_ddr3_phy_in;
MB_I_IO : inout t_tech_ddr3_phy_io;
MB_I_OU : out t_tech_ddr3_phy_ou
);
@@ -456,4 +456,4 @@ begin
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
index 2ca2ec7da92402c9eb1bc9f41219e76950540f75..7a7aac76341b756d6f6304652b5da8a32ca8939f 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
@@ -124,7 +124,7 @@ architecture str of mmm_unb_ddr3_transpose is
constant c_mm_clk_period : time := 100 ps;
constant c_sim_node_type : string(1 to 2) := sel_a_b(g_sim_node_nr <4, "FN", "BN");
- constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type ="BN ", g_sim_node_nr -4, g_sim_node_nr);
+ constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type ="BN ", g_sim_node_nr -4, g_sim_node_nr);
signal i_mm_clk : std_logic := '1';
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd
index 1c01ca31cd26bf6f036385427a1dbc9dda345e2c..2f6d5ed35940241b5d5dcadccde61bd8279b4340 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd
@@ -64,11 +64,11 @@ entity unb1_ddr3_transpose is
-- 1GbE Control Interface
ETH_clk : in std_logic;
- ETH_SGin : IN std_logic;
- ETH_SGout : OUT std_logic;
+ ETH_SGin : in std_logic;
+ ETH_SGout : out std_logic;
-- SO-DIMM Memory Bank I
- MB_I_in : IN t_tech_ddr3_phy_in := c_tech_ddr3_phy_in_x;
+ MB_I_in : in t_tech_ddr3_phy_in := c_tech_ddr3_phy_in_x;
MB_I_IO : inout t_tech_ddr3_phy_io;
MB_I_OU : out t_tech_ddr3_phy_ou
);
@@ -552,4 +552,4 @@ begin
in_sosi_arr => out_sosi_arr
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
index d8847b085f6dc44099c5805c3e25d9b46c89a14c..3784a74362caa06430b51eec80339ad9dca6e9d4 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
@@ -113,7 +113,7 @@ architecture str of mmm_unb1_fn_terminal_db is
constant c_tse_clk_period : time := 8 ns;
constant c_sim_node_type : string(1 to 2) := sel_a_b(g_sim_node_nr <4, "FN", "BN");
- constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type ="BN ", g_sim_node_nr -4, g_sim_node_nr);
+ constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type ="BN ", g_sim_node_nr -4, g_sim_node_nr);
signal i_mm_clk : std_logic := '1';
signal i_tse_clk : std_logic := '1';
@@ -378,5 +378,3 @@ end;
-
-
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/unb1_fn_terminal_db.vhd b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/unb1_fn_terminal_db.vhd
index f5cdec6bef24801a1b695e00fb2434f5a8a0e9ec..1ed87664114c94168bae120072f1fbebd1ebdcbd 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/unb1_fn_terminal_db.vhd
@@ -65,8 +65,8 @@ entity unb1_fn_terminal_db is
-- 1GbE Control Interface
ETH_clk : in std_logic;
- ETH_SGin : IN std_logic;
- ETH_SGout : OUT std_logic;
+ ETH_SGin : in std_logic;
+ ETH_SGout : out std_logic;
-- Transceiver clocks
--SA_CLK : IN STD_LOGIC := '0'; -- TR clock BN-BI (backplane)
@@ -413,5 +413,3 @@ end;
-
-
diff --git a/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd b/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
index 59270e496b6482889f85c4aa3da5de7a70698cf6..66cf60f5da352c2273f504276ecb0e981425db8d 100644
--- a/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
+++ b/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
@@ -110,7 +110,7 @@ architecture str of mmm_unb1_heater is
constant c_epcs_clk_period : time := 50 ns; -- 20 MHz
constant c_sim_node_type : string(1 to 2) := sel_a_b(g_sim_node_nr <4, "FN", "BN");
- constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type ="BN ", g_sim_node_nr -4, g_sim_node_nr);
+ constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type ="BN ", g_sim_node_nr -4, g_sim_node_nr);
signal i_mm_clk : std_logic := '1';
signal i_epcs_clk : std_logic := '1';
diff --git a/boards/uniboard1/designs/unb1_heater/src/vhdl/qsys_unb1_heater_pkg.vhd b/boards/uniboard1/designs/unb1_heater/src/vhdl/qsys_unb1_heater_pkg.vhd
index 72e8f11c1649ba03ddafc1683ad892271dc38ce8..56722c8122100c9a9a50a3927d49d2756e03eff7 100644
--- a/boards/uniboard1/designs/unb1_heater/src/vhdl/qsys_unb1_heater_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_heater/src/vhdl/qsys_unb1_heater_pkg.vhd
@@ -146,4 +146,4 @@ package qsys_unb1_heater_pkg is
);
end component qsys_unb1_heater;
-end qsys_unb1_heater_pkg;
+end qsys_unb1_heater_pkg;
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_heater/src/vhdl/unb1_heater.vhd b/boards/uniboard1/designs/unb1_heater/src/vhdl/unb1_heater.vhd
index 17c1cbae7f2eb3ef4b79a56cc0f18fa66c77f078..45454338578e723e474f632cd9dca8f6ce94455d 100644
--- a/boards/uniboard1/designs/unb1_heater/src/vhdl/unb1_heater.vhd
+++ b/boards/uniboard1/designs/unb1_heater/src/vhdl/unb1_heater.vhd
@@ -60,8 +60,8 @@ entity unb1_heater is
-- 1GbE Control Interface
ETH_clk : in std_logic;
- ETH_SGin : IN std_logic;
- ETH_SGout : OUT std_logic
+ ETH_SGin : in std_logic;
+ ETH_SGout : out std_logic
);
end unb1_heater;
@@ -349,4 +349,4 @@ begin
sla_in => reg_heater_mosi,
sla_out => reg_heater_miso
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/unb1_minimal_mm_arbiter.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/unb1_minimal_mm_arbiter.vhd
index 81f6486f519a72879538138ffa26464732acb52c..ee97a4bbb8323f610a043a88b239ccb1d5f50e1a 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/unb1_minimal_mm_arbiter.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/unb1_minimal_mm_arbiter.vhd
@@ -54,8 +54,8 @@ entity unb1_minimal_mm_arbiter is
-- 1GbE Control Interface
ETH_clk : in std_logic;
- ETH_SGin : IN std_logic;
- ETH_SGout : OUT std_logic
+ ETH_SGin : in std_logic;
+ ETH_SGout : out std_logic
);
end unb1_minimal_mm_arbiter;
@@ -98,4 +98,4 @@ begin
ETH_SGOUT => ETH_SGOUT
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/unb1_minimal_qsys.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/unb1_minimal_qsys.vhd
index 7834418b2c71e9bddbaf04eb4314f5d5d0c7c969..cb7c83c3d4f9083dae66afbf172462a20d4bfa46 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/unb1_minimal_qsys.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/unb1_minimal_qsys.vhd
@@ -54,8 +54,8 @@ entity unb1_minimal_qsys is
-- 1GbE Control Interface
ETH_clk : in std_logic;
- ETH_SGin : IN std_logic;
- ETH_SGout : OUT std_logic
+ ETH_SGin : in std_logic;
+ ETH_SGout : out std_logic
);
end unb1_minimal_qsys;
@@ -98,4 +98,4 @@ begin
ETH_SGOUT => ETH_SGOUT
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
index 651b64a5ca2dbf2db3a13ab2fbe72d4bd403d7ba..3c7c648c97b0458ae1cbba7afcffe754f3add57b 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
@@ -106,7 +106,7 @@ end mmm_unb1_minimal_qsys_wo_pll;
architecture str of mmm_unb1_minimal_qsys_wo_pll is
constant c_sim_node_type : string(1 to 2) := sel_a_b(g_sim_node_nr <4, "FN", "BN");
- constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type ="BN ", g_sim_node_nr -4, g_sim_node_nr);
+ constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type ="BN ", g_sim_node_nr -4, g_sim_node_nr);
constant c_sim_eth_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := x"00228608" & to_uvec(g_sim_unb_nr, c_byte_w) & to_uvec(g_sim_node_nr, c_byte_w);
constant c_sim_eth_control_rx_en : natural := 2 ** c_eth_mm_reg_control_bi.rx_en;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/unb1_minimal_qsys_wo_pll.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/unb1_minimal_qsys_wo_pll.vhd
index 76a13c389b19afc95a6c01caf246923f9407e004..a4bb0d9a77ae2fd4b2761c8da30467a5df7f630a 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/unb1_minimal_qsys_wo_pll.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/unb1_minimal_qsys_wo_pll.vhd
@@ -57,8 +57,8 @@ entity unb1_minimal_qsys_wo_pll is
-- 1GbE Control Interface
ETH_clk : in std_logic;
- ETH_SGin : IN std_logic;
- ETH_SGout : OUT std_logic
+ ETH_SGin : in std_logic;
+ ETH_SGout : out std_logic
);
end unb1_minimal_qsys_wo_pll;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.vhd
index 146686e2f71965b167d330e903bb1d1bbac21657..1ba8070dfc37f654a649a750f30db3343fe06f56 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.vhd
@@ -54,8 +54,8 @@ entity unb1_minimal_sopc is
-- 1GbE Control Interface
ETH_clk : in std_logic;
- ETH_SGin : IN std_logic;
- ETH_SGout : OUT std_logic
+ ETH_SGin : in std_logic;
+ ETH_SGout : out std_logic
);
end unb1_minimal_sopc;
@@ -97,4 +97,4 @@ begin
ETH_SGOUT => ETH_SGOUT
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd b/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
index 2b8bee1eb3c017fd6bd508df2ee34d3d9abdb137..961c399786353ebdac2678decfe69f301e54b0d8 100644
--- a/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
@@ -108,7 +108,7 @@ architecture str of mmm_unb1_minimal is
constant c_epcs_clk_period : time := 50 ns; -- 20 MHz
constant c_sim_node_type : string(1 to 2) := sel_a_b(g_sim_node_nr <4, "FN", "BN");
- constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type ="BN ", g_sim_node_nr -4, g_sim_node_nr);
+ constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type ="BN ", g_sim_node_nr -4, g_sim_node_nr);
signal i_mm_clk : std_logic := '1';
signal i_epcs_clk : std_logic := '1';
diff --git a/boards/uniboard1/designs/unb1_minimal/src/vhdl/qsys_unb1_minimal_pkg.vhd b/boards/uniboard1/designs/unb1_minimal/src/vhdl/qsys_unb1_minimal_pkg.vhd
index 8b09026719d656af5bcebd2eb4af46a4f39b3c2a..588a92f4c29a4394e05e9357b26ff4004f05cc76 100644
--- a/boards/uniboard1/designs/unb1_minimal/src/vhdl/qsys_unb1_minimal_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/src/vhdl/qsys_unb1_minimal_pkg.vhd
@@ -190,4 +190,4 @@ package qsys_unb1_minimal_pkg is
);
end component qsys_unb1_minimal_mm_arbiter;
-end qsys_unb1_minimal_pkg;
+end qsys_unb1_minimal_pkg;
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_minimal/src/vhdl/unb1_minimal.vhd b/boards/uniboard1/designs/unb1_minimal/src/vhdl/unb1_minimal.vhd
index f710d7054c738146edff55361a92d20376ff49b4..0b7323141ac2f0cc027f4e39de2eb1c23d3c2c83 100644
--- a/boards/uniboard1/designs/unb1_minimal/src/vhdl/unb1_minimal.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/src/vhdl/unb1_minimal.vhd
@@ -57,8 +57,8 @@ entity unb1_minimal is
-- 1GbE Control Interface
ETH_clk : in std_logic;
- ETH_SGin : IN std_logic;
- ETH_SGout : OUT std_logic
+ ETH_SGin : in std_logic;
+ ETH_SGout : out std_logic
);
end unb1_minimal;
@@ -73,8 +73,8 @@ architecture str of unb1_minimal is
-- Not simulating the 1GbE MAC+PHY speeds up simulation of unb1_minimal by a factor ~1.4.
constant c_use_phy : t_c_unb1_board_use_phy := (sel_a_b(g_sim, 0, 1), 0, 0, 0, 0, 0, 0, 1);
- constant c_use_qsys : boolean := g_design_name ="unb1_minimal_qsys ";
- constant c_use_sopc : boolean := g_design_name ="unb1_minimal_sopc ";
+ constant c_use_qsys : boolean := g_design_name ="unb1_minimal_qsys ";
+ constant c_use_sopc : boolean := g_design_name ="unb1_minimal_sopc ";
-- System
signal cs_sim : std_logic;
@@ -334,4 +334,4 @@ begin
-----------------------------------------------------------------------------
-- Insert node_[design_name] here
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
index 18d0dc936c4ad3f8d2eb5efa2208b8ea71074ab7..d0e98e2448903c445bf88a51a527edbf3fd20946 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
@@ -134,7 +134,7 @@ end entity mmm_unb1_terminal_bg_mesh_db;
architecture str of mmm_unb1_terminal_bg_mesh_db is
constant c_sim_node_type : string(1 to 2) := sel_a_b(g_sim_node_nr <4, "FN", "BN");
- constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type ="BN ", g_sim_node_nr -4, g_sim_node_nr);
+ constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type ="BN ", g_sim_node_nr -4, g_sim_node_nr);
constant c_sim_eth_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := x"00228608" & to_uvec(g_sim_unb_nr, c_byte_w) & to_uvec(g_sim_node_nr, c_byte_w);
constant c_sim_eth_control_rx_en : natural := 2 ** c_eth_mm_reg_control_bi.rx_en;
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/unb1_terminal_bg_mesh_db.vhd
index e7bee761d1903edd8ae7b031883bc4621c502f54..bb50d429bf0bc4ac3a76ae2dd4a0ecafda5ce219 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/unb1_terminal_bg_mesh_db.vhd
@@ -65,8 +65,8 @@ entity unb1_terminal_bg_mesh_db is
-- 1GbE Control Interface
ETH_clk : in std_logic;
- ETH_SGin : IN std_logic;
- ETH_SGout : OUT std_logic;
+ ETH_SGin : in std_logic;
+ ETH_SGout : out std_logic;
-- Transceiver clocks
SB_CLK : in std_logic := '0'; -- TR clock FN-BN (mesh)
@@ -487,5 +487,3 @@ end;
-
-
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
index 200f0e1e2f598ba505bc0e68a1b4a90ae333114b..c205c084e30e46fa358511742ce4b6e5c477fd88 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
@@ -56,8 +56,8 @@ entity unb1_test_10GbE is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic;
- ETH_SGout : OUT std_logic;
+ ETH_SGin : in std_logic;
+ ETH_SGout : out std_logic;
-- Transceiver clocks
SA_CLK : in std_logic; -- SerDes Clock BN-BI / SI_FN
@@ -156,4 +156,4 @@ begin
BN_BI_3_RX => BN_BI_3_RX
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/unb1_test_10GbE_tx_only.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/unb1_test_10GbE_tx_only.vhd
index d577c493b136d67940734d20cd3495cca749269f..0d5e90da7f146468ee0fc83b9512e6bfb007ccba 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/unb1_test_10GbE_tx_only.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/unb1_test_10GbE_tx_only.vhd
@@ -56,8 +56,8 @@ entity unb1_test_10GbE_tx_only is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic;
- ETH_SGout : OUT std_logic;
+ ETH_SGin : in std_logic;
+ ETH_SGout : out std_logic;
-- Transceiver clocks
SA_CLK : in std_logic; -- SerDes Clock BN-BI / SI_FN
@@ -139,4 +139,4 @@ begin
SI_FN_RSTN => SI_FN_RSTN
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/unb1_test_1GbE.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/unb1_test_1GbE.vhd
index b402a1a14550cba7d9260f4adc5b8302f429d77d..f389a07fc1602c8ceffc91f1b166565ec10e6925 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/unb1_test_1GbE.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/unb1_test_1GbE.vhd
@@ -56,8 +56,8 @@ entity unb1_test_1GbE is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic;
- ETH_SGout : OUT std_logic
+ ETH_SGin : in std_logic;
+ ETH_SGout : out std_logic
);
end unb1_test_1GbE;
@@ -100,4 +100,4 @@ begin
ETH_SGOUT => ETH_SGOUT
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/unb1_test_all.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/unb1_test_all.vhd
index 202dceab3a35597717832d653ed5bad34ee6093c..619bbb621c39f26f80de70139e52b0011302657f 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/unb1_test_all.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/unb1_test_all.vhd
@@ -57,8 +57,8 @@ entity unb1_test_all is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic;
- ETH_SGout : OUT std_logic;
+ ETH_SGin : in std_logic;
+ ETH_SGout : out std_logic;
-- Transceiver clocks
SA_CLK : in std_logic; -- SerDes Clock BN-BI / SI_FN
@@ -89,12 +89,12 @@ entity unb1_test_all is
BN_BI_3_RX : in std_logic_vector(c_unb1_board_ci.tr.bus_w - 1 downto 0);
-- SO-DIMM Memory Bank I
- MB_I_in : IN t_tech_ddr3_phy_in;
+ MB_I_in : in t_tech_ddr3_phy_in;
MB_I_IO : inout t_tech_ddr3_phy_io;
MB_I_OU : out t_tech_ddr3_phy_ou;
-- SO-DIMM Memory Bank II
- MB_II_in : IN t_tech_ddr3_phy_in;
+ MB_II_in : in t_tech_ddr3_phy_in;
MB_II_IO : inout t_tech_ddr3_phy_io;
MB_II_OU : out t_tech_ddr3_phy_ou
);
@@ -175,4 +175,4 @@ begin
MB_II_OU => MB_II_OU
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/unb1_test_ddr.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/unb1_test_ddr.vhd
index 6670cd962c8b9ba39bf2d47dda8c8a3fb84cbbff..0b1cf0a3b8ac083f8c2bbe4d9baf24108129e668 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/unb1_test_ddr.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/unb1_test_ddr.vhd
@@ -57,11 +57,11 @@ entity unb1_test_ddr is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic;
- ETH_SGout : OUT std_logic;
+ ETH_SGin : in std_logic;
+ ETH_SGout : out std_logic;
-- SO-DIMM Memory Bank I
- MB_I_in : IN t_tech_ddr3_phy_in;
+ MB_I_in : in t_tech_ddr3_phy_in;
MB_I_IO : inout t_tech_ddr3_phy_io;
MB_I_OU : out t_tech_ddr3_phy_ou
);
@@ -114,4 +114,4 @@ begin
-- MB_II_OU => MB_II_OU
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/unb1_test_ddr_16g_MB_I.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/unb1_test_ddr_16g_MB_I.vhd
index 858b0ff2d3a6745cf7471c94b00aed23dc3b422a..415404a36f6beb6e33c70b5571669ecaaa99d5d6 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/unb1_test_ddr_16g_MB_I.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/unb1_test_ddr_16g_MB_I.vhd
@@ -57,11 +57,11 @@ entity unb1_test_ddr_16g_MB_I is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic;
- ETH_SGout : OUT std_logic;
+ ETH_SGin : in std_logic;
+ ETH_SGout : out std_logic;
-- SO-DIMM Memory Bank I
- MB_I_in : IN t_tech_ddr3_phy_in;
+ MB_I_in : in t_tech_ddr3_phy_in;
MB_I_IO : inout t_tech_ddr3_phy_io;
MB_I_OU : out t_tech_ddr3_phy_ou
);
@@ -111,4 +111,4 @@ begin
MB_I_OU => MB_I_OU
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/unb1_test_ddr_16g_MB_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/unb1_test_ddr_16g_MB_II.vhd
index 027cb2e52d09eb0ded5cff2f3c6bd5feb378b071..86f2f6fd1b4758d66b2cd19a33e6f5a80c21c568 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/unb1_test_ddr_16g_MB_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/unb1_test_ddr_16g_MB_II.vhd
@@ -57,11 +57,11 @@ entity unb1_test_ddr_16g_MB_II is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic;
- ETH_SGout : OUT std_logic;
+ ETH_SGin : in std_logic;
+ ETH_SGout : out std_logic;
-- SO-DIMM Memory Bank II
- MB_II_in : IN t_tech_ddr3_phy_in;
+ MB_II_in : in t_tech_ddr3_phy_in;
MB_II_IO : inout t_tech_ddr3_phy_io;
MB_II_OU : out t_tech_ddr3_phy_ou
);
@@ -111,4 +111,4 @@ begin
MB_II_OU => MB_II_OU
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/unb1_test_ddr_16g_MB_I_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/unb1_test_ddr_16g_MB_I_II.vhd
index 24b09371a55735bbd808099c6e048a6d516d8e78..01299802c9519c7bf21e1e154b510888fbfc9825 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/unb1_test_ddr_16g_MB_I_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/unb1_test_ddr_16g_MB_I_II.vhd
@@ -57,16 +57,16 @@ entity unb1_test_ddr_16g_MB_I_II is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic;
- ETH_SGout : OUT std_logic;
+ ETH_SGin : in std_logic;
+ ETH_SGout : out std_logic;
-- SO-DIMM Memory Bank I
- MB_I_in : IN t_tech_ddr3_phy_in;
+ MB_I_in : in t_tech_ddr3_phy_in;
MB_I_IO : inout t_tech_ddr3_phy_io;
MB_I_OU : out t_tech_ddr3_phy_ou;
-- SO-DIMM Memory Bank II
- MB_II_in : IN t_tech_ddr3_phy_in;
+ MB_II_in : in t_tech_ddr3_phy_in;
MB_II_IO : inout t_tech_ddr3_phy_io;
MB_II_OU : out t_tech_ddr3_phy_ou
);
@@ -121,4 +121,4 @@ begin
MB_II_OU => MB_II_OU
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/unb1_test_ddr_MB_I_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/unb1_test_ddr_MB_I_II.vhd
index 7bbbb5171baff64b82fe67f724f004ca7701b0ca..8704f5b2489995ede5da580fb4c6bb9c5965e293 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/unb1_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/unb1_test_ddr_MB_I_II.vhd
@@ -57,16 +57,16 @@ entity unb1_test_ddr_MB_I_II is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic;
- ETH_SGout : OUT std_logic;
+ ETH_SGin : in std_logic;
+ ETH_SGout : out std_logic;
-- SO-DIMM Memory Bank I
- MB_I_in : IN t_tech_ddr3_phy_in;
+ MB_I_in : in t_tech_ddr3_phy_in;
MB_I_IO : inout t_tech_ddr3_phy_io;
MB_I_OU : out t_tech_ddr3_phy_ou;
-- SO-DIMM Memory Bank II
- MB_II_in : IN t_tech_ddr3_phy_in;
+ MB_II_in : in t_tech_ddr3_phy_in;
MB_II_IO : inout t_tech_ddr3_phy_io;
MB_II_OU : out t_tech_ddr3_phy_ou
);
@@ -121,4 +121,4 @@ begin
MB_II_OU => MB_II_OU
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
index cfbce35ae8aaad352d92f64a021aa83c3714ac1b..73428e9f95d64efea08efd53cc26f8a10182582b 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
@@ -241,7 +241,7 @@ architecture str of mmm_unb1_test is
-- Simulation
constant c_sim_node_type : string(1 to 2) := sel_a_b(g_sim_node_nr <4, "FN", "BN");
- constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type ="BN ", g_sim_node_nr -4, g_sim_node_nr);
+ constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type ="BN ", g_sim_node_nr -4, g_sim_node_nr);
constant c_sim_eth_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := x"00228608" & to_uvec(g_sim_unb_nr, c_byte_w) & to_uvec(g_sim_node_nr, c_byte_w);
constant c_sim_eth_control_rx_en : natural := 2 ** c_eth_mm_reg_control_bi.rx_en;
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/udp_stream.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/udp_stream.vhd
index c8d16c761c9019cc13b022eb48d22cbce30f1b3a..22b3a4ac2ef5573d48700918e808bc9194e28d98 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/udp_stream.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/udp_stream.vhd
@@ -113,7 +113,7 @@ architecture str of udp_stream is
to_uvec( 0, c_diag_bg_bsn_init_w));
- constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "1001" &"111011111100 " &"0001 " &"101111111 ";
+ constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "1001" &"111011111100 " &"0001 " &"101111111 ";
constant c_nof_crc_words : natural := 1;
constant c_max_nof_words_per_block : natural := g_bg_block_size;
constant c_min_nof_words_per_block : natural := 1;
@@ -348,4 +348,4 @@ begin
in_sosi_arr => diag_data_buf_snk_in_arr
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
index dc20be05ab60797bdad3c0acda5bd8587078400c..030fc77bdc41310a518da9fd688d5cfbf7d3f30a 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
@@ -68,8 +68,8 @@ entity unb1_test is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic;
- ETH_SGout : OUT std_logic;
+ ETH_SGin : in std_logic;
+ ETH_SGout : out std_logic;
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- SerDes Clock BN-BI / SI_FN
@@ -100,12 +100,12 @@ entity unb1_test is
BN_BI_3_RX : in std_logic_vector(c_unb1_board_ci.tr.bus_w - 1 downto 0) := (others => '0');
-- SO-DIMM Memory Bank I
- MB_I_in : IN t_tech_ddr3_phy_in := c_tech_ddr3_phy_in_x;
+ MB_I_in : in t_tech_ddr3_phy_in := c_tech_ddr3_phy_in_x;
MB_I_IO : inout t_tech_ddr3_phy_io;
MB_I_OU : out t_tech_ddr3_phy_ou;
-- SO-DIMM Memory Bank II
- MB_II_in : IN t_tech_ddr3_phy_in := c_tech_ddr3_phy_in_x;
+ MB_II_in : in t_tech_ddr3_phy_in := c_tech_ddr3_phy_in_x;
MB_II_IO : inout t_tech_ddr3_phy_io;
MB_II_OU : out t_tech_ddr3_phy_ou
);
@@ -986,4 +986,4 @@ gen_mms_io_ddr_diag_MB_II : if c_revision_select.use_ddr_MB_II = 1 generate
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test_pkg.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test_pkg.vhd
index 21acbfa5c1259beb8c59dd76bdd53cc3f19b7a81..a5d6c17234bc059ed5c55bdccb8f8d2c1d68d67c 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test_pkg.vhd
@@ -42,7 +42,7 @@ package unb1_test_pkg is
end record;
-- dp_offload_tx
- constant c_nof_hdr_fields : natural := 4 +12 + 4 + 9; -- Total header bits = 512
+ constant c_nof_hdr_fields : natural := 4 + 12 + 4 + 9; -- Total header bits = 512
constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( ( field_name_pad("eth_word_align" ), " ", 16, field_default(0) ),
( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
@@ -105,4 +105,4 @@ package body unb1_test_pkg is
end if;
end;
-end unb1_test_pkg;
+end unb1_test_pkg;
\ No newline at end of file
diff --git a/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/unb1_tr_10GbE.vhd b/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/unb1_tr_10GbE.vhd
index ffe4f29f50bcce2c5b09c73f6d1db458e95a1b1b..3d8392052350d9a2610a029fcbf989c768c3b721 100644
--- a/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/unb1_tr_10GbE.vhd
+++ b/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/unb1_tr_10GbE.vhd
@@ -66,8 +66,8 @@ entity unb1_tr_10GbE is
-- 1GbE Control Interface
ETH_clk : in std_logic;
- ETH_SGin : IN std_logic;
- ETH_SGout : OUT std_logic;
+ ETH_SGin : in std_logic;
+ ETH_SGout : out std_logic;
-- Transceiver clocks
SA_CLK : in std_logic; -- SerDes Clock BN-BI / SI_FN
@@ -531,4 +531,4 @@ begin
reg_mdio_1_miso <= reg_mdio_miso_arr(1);
reg_mdio_2_miso <= reg_mdio_miso_arr(2);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd
index 5655c807baf9583f30807f18fad5f32abe2a841d..a45cfda643bb27d2046ddcbbbd6341fc69532e45 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd
@@ -261,8 +261,8 @@ entity ctrl_unb1_board is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic;
- ETH_SGout : OUT std_logic
+ ETH_SGin : in std_logic;
+ ETH_SGout : out std_logic
);
end ctrl_unb1_board;
@@ -527,8 +527,8 @@ begin
------------------------------------------------------------------------------
-- Toggle red LED when unb1_minimal is running, green LED for other designs.
------------------------------------------------------------------------------
- led_toggle_red <= sel_a_b(g_design_name(1 to 8) ="unb1_min ", led_toggle, '0');
- led_toggle_green <= sel_a_b(g_design_name(1 to 8) /="unb1_min ", led_toggle, '0');
+ led_toggle_red <= sel_a_b(g_design_name(1 to 8) ="unb1_min ", led_toggle, '0');
+ led_toggle_green <= sel_a_b(g_design_name(1 to 8) /="unb1_min ", led_toggle, '0');
u_toggle : entity common_lib.common_toggle
port map (
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_sens.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_sens.vhd
index 6d30c980880c390314300e11a354ef2f1b0affd6..b877d713a72fbd695d76ac39a2636d3a1853eedd 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_sens.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_sens.vhd
@@ -114,4 +114,4 @@ begin
-- temp_high is 7 bits, preceded by a '0' to allow only positive temps to be set.
temp_alarm <= '1' when (signed(sens_data(0)) > signed('0' & temp_high)) else '0';
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_system_info.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_system_info.vhd
index 6e7baad578ae01f24786f4498e7161a297cfbffd..b476da96574d06eabc32c1eefa6585207a493a71 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_system_info.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_system_info.vhd
@@ -73,7 +73,7 @@ architecture str of mms_unb1_board_system_info is
-- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
-- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
- constant c_mif_name : string := sel_a_b(g_sim, "UNUSED", sel_a_b((g_design_name ="UNUSED "), g_design_name, c_path_prefix & g_design_name & ".mif"));
+ constant c_mif_name : string := sel_a_b(g_sim, "UNUSED", sel_a_b((g_design_name ="UNUSED "), g_design_name, c_path_prefix & g_design_name & ".mif"));
constant c_rom_addr_w : natural := 10; -- 2^10 = 1024 addresses * 32 bits = 4 kiB
@@ -138,4 +138,4 @@ begin
rd_val => rom_miso.rdval
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_io.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_io.vhd
index 9f03e7630840227db84b430043e0d1fea369e15c..0882c57358dd5558f2861579f2abea699bab94ad 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_io.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_io.vhd
@@ -73,5 +73,3 @@ end;
-
-
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_io.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_io.vhd
index 4f8dba193f6bc43d5c47c87651ec41b9a6e7e33b..c2c220b9df2428b580bef19fdd178d64f3b74078 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_io.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_io.vhd
@@ -71,5 +71,3 @@ end;
-
-
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_bidir.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_bidir.vhd
index c0533a463f8f44cbc18e6bb6e6045adcd88b2292..39ccd42c8894be35706dfb3ec23f90c90cd7b32f 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_bidir.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_bidir.vhd
@@ -196,4 +196,4 @@ begin
tx_usr_siso_2arr => tx_usr_siso_2arr
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info_reg.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info_reg.vhd
index 9655b84f5d4006639276e83e3da26105b02633e2..731ddfc6b3b33c23df58bfe83c278b81c6acf04b 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info_reg.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info_reg.vhd
@@ -148,4 +148,4 @@ begin
end process;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd
index 5afc55efaac9f2b01fec9ad2759ca65838de8a92..cf57fcaf6f7806ab122eec1002b0be82b3a03807 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd
@@ -410,4 +410,4 @@ begin
diagnostics_mm_miso => reg_diagnostics_miso
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_reg.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_reg.vhd
index 421d7f54ec88bcc98930eadb92dad468f0cb102c..58661bc80c9831b0bb359f1c856825dcd601ef14 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_reg.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_reg.vhd
@@ -86,4 +86,4 @@ begin
end if;
end process;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd
index 476306be78d7f3f36a3aa3664edaa77bba336de9..04d79f128d428e4291d6f5a25a8b51c0f05484bf 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd
@@ -208,4 +208,4 @@ begin
ana_volt_adin => c_uniboard_adin
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/boards/uniboard2/designs/unb2_led/src/vhdl/unb2_led.vhd b/boards/uniboard2/designs/unb2_led/src/vhdl/unb2_led.vhd
index 6f1107d8524a08d1e456194c3c4e5010062652df..149ed772eb8d6be31fb7d10e51e046e3abd5ee72 100644
--- a/boards/uniboard2/designs/unb2_led/src/vhdl/unb2_led.vhd
+++ b/boards/uniboard2/designs/unb2_led/src/vhdl/unb2_led.vhd
@@ -228,4 +228,4 @@ begin
QSFP_LED(5) <= '1';
QSFP_LED(9) <= '1';
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd b/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd
index 18bdad40deee3a0e5b949c4930c53e320d06ba31..1eb64ac881e1b4eb0b2c0368e1527360519e0710 100644
--- a/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd
+++ b/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd
@@ -64,8 +64,8 @@ entity unb2_minimal is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
QSFP_LED : out std_logic_vector(c_unb2_board_tr_qsfp_nof_leds - 1 downto 0)
);
@@ -376,4 +376,4 @@ begin
-- QSFP_LED => QSFP_LED
-- );
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/tb_unb2_test_10GbE.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/tb_unb2_test_10GbE.vhd
index 5fef21e3c5506b2d97872c1affd6ddcbb053acee..36f660a61d026e31748e6cb01dc55d8651328fb1 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/tb_unb2_test_10GbE.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/tb_unb2_test_10GbE.vhd
@@ -34,4 +34,4 @@ begin
generic map (
g_design_name => "unb2_test_10GbE"
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd
index e7d912cb38d3e6ffd650f9edd10fdedba918831f..905e6a838fb293590b3b65f59542d999f22935ad 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd
@@ -58,8 +58,8 @@ entity unb2_test_10GbE is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic; -- Clock 10GbE front (qsfp) and ring lines
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/tb_unb2_test_1GbE.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/tb_unb2_test_1GbE.vhd
index 4dc5b230a9c7cf048cda297fbd7e9841bfe432e1..c94f78265e18e6a702f18484b9136b6f427d8fa0 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/tb_unb2_test_1GbE.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/tb_unb2_test_1GbE.vhd
@@ -36,4 +36,4 @@ begin
generic map (
g_design_name => "unb2_test_1GbE"
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/unb2_test_1GbE.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/unb2_test_1GbE.vhd
index cbfe1900804fbda6b0d9087421f0eb70aa6280d9..073d3f47bd50100f380b1547ac457255304c29f9 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/unb2_test_1GbE.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/unb2_test_1GbE.vhd
@@ -62,8 +62,8 @@ entity unb2_test_1GbE is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
QSFP_LED : out std_logic_vector(c_unb2_board_tr_qsfp_nof_leds - 1 downto 0)
);
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/tb_unb2_test_all.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/tb_unb2_test_all.vhd
index b38c8fa5a967472d4d10cc725f1ba9e173da9cc8..f40a0c0445c0588a007063937da1b3fb68b30d75 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/tb_unb2_test_all.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/tb_unb2_test_all.vhd
@@ -37,4 +37,4 @@ begin
g_design_name => "unb2_test_all",
g_sim_model_ddr => FALSE
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/unb2_test_all.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/unb2_test_all.vhd
index 749820d360dfa4ba14af0b524d582d822c28f66a..0e6a262d237c6a7b5d8d6bb807a13a5f363d90c3 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/unb2_test_all.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/unb2_test_all.vhd
@@ -59,8 +59,8 @@ entity unb2_test_all is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic; -- Clock 10GbE front (qsfp) and ring lines
@@ -105,12 +105,12 @@ entity unb2_test_all is
QSFP_SCL : inout std_logic_vector(c_unb2_board_tr_qsfp.i2c_w - 1 downto 0);
-- SO-DIMM Memory Bank I
- MB_I_in : IN t_tech_ddr4_phy_in;
+ MB_I_in : in t_tech_ddr4_phy_in;
MB_I_IO : inout t_tech_ddr4_phy_io;
MB_I_OU : out t_tech_ddr4_phy_ou;
-- SO-DIMM Memory Bank II
- MB_II_in : IN t_tech_ddr4_phy_in;
+ MB_II_in : in t_tech_ddr4_phy_in;
MB_II_IO : inout t_tech_ddr4_phy_io;
MB_II_OU : out t_tech_ddr4_phy_ou;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/tb_unb2_test_ddr_MB_I.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/tb_unb2_test_ddr_MB_I.vhd
index 29ad5a09786ffdceb17f81bdab2ed84c597cf949..8843d959b4aa7494048fde661d0cf06d6a8a562d 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/tb_unb2_test_ddr_MB_I.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/tb_unb2_test_ddr_MB_I.vhd
@@ -37,4 +37,4 @@ begin
g_design_name => "unb2_test_ddr_MB_I",
g_sim_model_ddr => FALSE
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/unb2_test_ddr_MB_I.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/unb2_test_ddr_MB_I.vhd
index ddcf3523c2251dfb69fd05e157ce6f092985a4b8..5fa7a8c45f0ba26a2944721d39abf0d618a3890d 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/unb2_test_ddr_MB_I.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/unb2_test_ddr_MB_I.vhd
@@ -63,14 +63,14 @@ entity unb2_test_ddr_MB_I is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
-- DDR reference clocks
MB_I_REF_CLK : in std_logic; -- Reference clock for MB_I
-- SO-DIMM Memory Bank I
- MB_I_in : IN t_tech_ddr4_phy_in;
+ MB_I_in : in t_tech_ddr4_phy_in;
MB_I_IO : inout t_tech_ddr4_phy_io;
MB_I_OU : out t_tech_ddr4_phy_ou;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/tb_unb2_test_ddr_MB_II.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/tb_unb2_test_ddr_MB_II.vhd
index 6331c074eb41ba0cde1f05895c03e21661ed3463..ace8ec86bfccd94da0c3660ce95f9c05f07548e0 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/tb_unb2_test_ddr_MB_II.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/tb_unb2_test_ddr_MB_II.vhd
@@ -37,4 +37,4 @@ begin
g_design_name => "unb2_test_ddr_MB_II",
g_sim_model_ddr => FALSE
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/unb2_test_ddr_MB_II.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/unb2_test_ddr_MB_II.vhd
index eb22e47227ca578bb8a8b59835a1a389b39f9b4e..80780d95f36e276143222a79b814daa8d3d5f4d7 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/unb2_test_ddr_MB_II.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/unb2_test_ddr_MB_II.vhd
@@ -63,14 +63,14 @@ entity unb2_test_ddr_MB_II is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
-- DDR reference clocks
MB_II_REF_CLK : in std_logic; -- Reference clock for MB_II
-- SO-DIMM Memory Bank II
- MB_II_in : IN t_tech_ddr4_phy_in;
+ MB_II_in : in t_tech_ddr4_phy_in;
MB_II_IO : inout t_tech_ddr4_phy_io;
MB_II_OU : out t_tech_ddr4_phy_ou;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/tb_unb2_test_ddr_MB_I_II.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/tb_unb2_test_ddr_MB_I_II.vhd
index c239c3dfea0ad6c17ddf8a64d422f093f5db2148..884e1d3cac0f27c9c9fba5616f6b89d9dce94dba 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/tb_unb2_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/tb_unb2_test_ddr_MB_I_II.vhd
@@ -37,4 +37,4 @@ begin
g_design_name => "unb2_test_ddr_MB_I_II",
g_sim_model_ddr => FALSE
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/unb2_test_ddr_MB_I_II.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/unb2_test_ddr_MB_I_II.vhd
index 5c2708b9991785037a59423e153ddb3f68f8c940..154863e8e733ec4b9348f39a4265378be69f4da9 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/unb2_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/unb2_test_ddr_MB_I_II.vhd
@@ -63,20 +63,20 @@ entity unb2_test_ddr_MB_I_II is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
-- DDR reference clocks
MB_I_REF_CLK : in std_logic; -- Reference clock for MB_I
MB_II_REF_CLK : in std_logic; -- Reference clock for MB_II
-- SO-DIMM Memory Bank I
- MB_I_in : IN t_tech_ddr4_phy_in;
+ MB_I_in : in t_tech_ddr4_phy_in;
MB_I_IO : inout t_tech_ddr4_phy_io;
MB_I_OU : out t_tech_ddr4_phy_ou;
-- SO-DIMM Memory Bank II
- MB_II_in : IN t_tech_ddr4_phy_in;
+ MB_II_in : in t_tech_ddr4_phy_in;
MB_II_IO : inout t_tech_ddr4_phy_io;
MB_II_OU : out t_tech_ddr4_phy_ou;
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
index 15068ec8091f32ee4cdd47b372b68eb73ddb32cd..fc88857415f6671e209965d6807adbd76d5d6ee3 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
@@ -379,4 +379,4 @@ package qsys_unb2_test_pkg is
);
end component qsys_unb2_test;
-end qsys_unb2_test_pkg;
+end qsys_unb2_test_pkg;
\ No newline at end of file
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/udp_stream.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/udp_stream.vhd
index 472bd3f0af8cfdd4d651189571aeb5d644a756e3..997700c1e6f5e0871ad51a89e19cbd978409ca7c 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/udp_stream.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/udp_stream.vhd
@@ -353,4 +353,4 @@ begin
in_sosi_arr => diag_data_buf_snk_in_arr
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
index 99c9829140451df7cc74124eb87664cf9879facd..d11df011494693ba90b50edb7d1fb638e3575b69 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
@@ -71,8 +71,8 @@ entity unb2_test is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
@@ -123,12 +123,12 @@ entity unb2_test is
QSFP_RST : inout std_logic;
-- SO-DIMM Memory Bank I
- MB_I_in : IN t_tech_ddr4_phy_in := c_tech_ddr4_phy_in_x;
+ MB_I_in : in t_tech_ddr4_phy_in := c_tech_ddr4_phy_in_x;
MB_I_IO : inout t_tech_ddr4_phy_io;
MB_I_OU : out t_tech_ddr4_phy_ou;
-- SO-DIMM Memory Bank II
- MB_II_in : IN t_tech_ddr4_phy_in := c_tech_ddr4_phy_in_x;
+ MB_II_in : in t_tech_ddr4_phy_in := c_tech_ddr4_phy_in_x;
MB_II_IO : inout t_tech_ddr4_phy_io;
MB_II_OU : out t_tech_ddr4_phy_ou;
@@ -146,13 +146,13 @@ architecture str of unb2_test is
-- Revision controlled constants
constant c_use_1GbE : boolean := FALSE; --g_design_name="unb2_test_1GbE" OR g_design_name="unb2_test_10GbE" OR g_design_name="unb2_test_all";
- constant c_use_10GbE : boolean := g_design_name ="unb2_test_10GbE " or g_design_name ="unb2_test_all ";
+ constant c_use_10GbE : boolean := g_design_name ="unb2_test_10GbE " or g_design_name ="unb2_test_all ";
constant c_use_10GbE_qsfp : boolean := c_use_10GbE;
constant c_use_10GbE_ring : boolean := FALSE; --c_use_10GbE;
constant c_use_10GbE_back0 : boolean := FALSE; --c_use_10GbE;
constant c_use_10GbE_back1 : boolean := FALSE; --c_use_10GbE;
- constant c_use_MB_I : boolean := g_design_name ="unb2_test_ddr_MB_I " or g_design_name ="unb2_test_ddr_MB_I_II " or g_design_name ="unb2_test_all ";
- constant c_use_MB_II : boolean := g_design_name ="unb2_test_ddr_MB_II " or g_design_name ="unb2_test_ddr_MB_I_II " or g_design_name ="unb2_test_all ";
+ constant c_use_MB_I : boolean := g_design_name ="unb2_test_ddr_MB_I " or g_design_name ="unb2_test_ddr_MB_I_II " or g_design_name ="unb2_test_all ";
+ constant c_use_MB_II : boolean := g_design_name ="unb2_test_ddr_MB_II " or g_design_name ="unb2_test_ddr_MB_I_II " or g_design_name ="unb2_test_all ";
-- transceivers
constant c_nof_qsfp : natural := c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w;
@@ -1253,4 +1253,4 @@ begin
);
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test_pkg.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test_pkg.vhd
index 0594e2a468c2f956980cbbc78ec98823933236c6..2a38cf9fc963f6d8bec38857ee36e639fc7a9403 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test_pkg.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test_pkg.vhd
@@ -29,7 +29,7 @@ package unb2_test_pkg is
-- dp_offload_tx
--CONSTANT c_nof_hdr_fields : NATURAL := 1+3+12+4+2; -- Total header bits = 384 = 6 64b words
- constant c_nof_hdr_fields : natural := 3 +12 + 4 + 2; -- Total header bits = 384 = 6 64b words
+ constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 2; -- Total header bits = 384 = 6 64b words
constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( --( field_name_pad("align" ), " ", 16, field_default(0) ),
( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
@@ -54,6 +54,6 @@ package unb2_test_pkg is
( field_name_pad("usr_bsn" ), " ", 47, field_default(0) ));
--CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "1001"&"111111111100"&"0011"&"00";
- constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "001" &"111111111100 " &"0011 " &"00 ";
+ constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "001" &"111111111100 " &"0011 " &"00 ";
-end unb2_test_pkg;
+end unb2_test_pkg;
\ No newline at end of file
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
index 08eeb77e58d435161cf6bc2119a1e4b2ac5cdfb0..b7230d6bfd2cfc76306ecf2edadf3b4c45d2c6e4 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
@@ -241,8 +241,8 @@ entity ctrl_unb2_board is
-- 1GbE Control Interface
ETH_CLK : in std_logic; -- 125 MHz
- ETH_SGin : IN std_logic_vector(c_unb2_board_nof_eth - 1 downto 0) := (others => '0');
- ETH_SGout : OUT std_logic_vector(c_unb2_board_nof_eth - 1 downto 0)
+ ETH_SGin : in std_logic_vector(c_unb2_board_nof_eth - 1 downto 0) := (others => '0');
+ ETH_SGout : out std_logic_vector(c_unb2_board_nof_eth - 1 downto 0)
);
end ctrl_unb2_board;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_sens.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_sens.vhd
index 93bb82009232ced58f5ac0de9e2c813458c1002b..504e5e957c4160ab129eba4615d57e38fdff1af0 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_sens.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_sens.vhd
@@ -116,4 +116,4 @@ begin
-- temp_high is 7 bits, preceded by a '0' to allow only positive temps to be set.
temp_alarm <= '1' when (signed(sens_data(0)) > signed('0' & temp_high)) else '0';
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd
index cd4cefeee1d62f77d41f27f2d4b7e5c601fa7a22..7d19de3788afb0ee8b30b080e0add06d8e9f6680 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd
@@ -72,7 +72,7 @@ architecture str of mms_unb2_board_system_info is
-- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
-- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
- constant c_mif_name : string := sel_a_b(g_sim, "UNUSED", sel_a_b((g_design_name ="UNUSED "), g_design_name, c_path_prefix & g_design_name & ".mif"));
+ constant c_mif_name : string := sel_a_b(g_sim, "UNUSED", sel_a_b((g_design_name ="UNUSED "), g_design_name, c_path_prefix & g_design_name & ".mif"));
constant c_rom_addr_w : natural := 10; -- 2^10 = 1024 addresses * 32 bits = 4 kiB
@@ -137,4 +137,4 @@ begin
rd_val => rom_miso.rdval
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd
index 2389544a8ef3da4929c3fe4d801001865262e590..ebeb1fe33738f512d41a47e93a5972a34521446d 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd
@@ -118,4 +118,4 @@ begin
-- temp_high is 7 bits, preceded by a '0' to allow only positive temps to be set.
temp_alarm <= '0'; --<= '1' WHEN (SIGNED(sens_data(0)) > SIGNED('0' & temp_high)) ELSE '0';
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd
index 86b629682fa17af0789cb629e7dbdee40d7fe18e..2ac09a27cef3aa111dd48d62c7cd6b6fd5a06fae 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd
@@ -32,7 +32,7 @@ entity unb2_board_ring_io is
serial_tx_arr : in std_logic_vector(g_nof_ring_bus * c_unb2_board_tr_ring.bus_w - 1 downto 0) := (others => '0');
serial_rx_arr : out std_logic_vector(g_nof_ring_bus * c_unb2_board_tr_ring.bus_w - 1 downto 0);
- RinG_RX : IN t_unb2_board_ring_bus_2arr(g_nof_ring_bus - 1 downto 0) := (others => (others => '0'));
+ RinG_RX : in t_unb2_board_ring_bus_2arr(g_nof_ring_bus - 1 downto 0) := (others => (others => '0'));
RING_TX : out t_unb2_board_ring_bus_2arr(g_nof_ring_bus - 1 downto 0)
);
end unb2_board_ring_io;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info_reg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info_reg.vhd
index 57bbeb8b6f54ad27d8631067ec4483dd939c747c..805540631a8e7e67481c1a9de50c0a2f3d5609e0 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info_reg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info_reg.vhd
@@ -140,4 +140,4 @@ begin
end process;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_reg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_reg.vhd
index ecf702091aba25ff005a63911671529f88451692..3b03b7f01a9332d0e0899ea151a995fa6fd32467 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_reg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_reg.vhd
@@ -86,4 +86,4 @@ begin
end if;
end process;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_mms_unb2_board_sens.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
index 5ba0bfa64faa1f84cb4e2fce6094528889f1a127..b3250581255a7f9415b0df9ba7e2f581b280279e 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
@@ -208,4 +208,4 @@ begin
ana_volt_adin => c_uniboard_adin
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew_inst.vhd b/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew_inst.vhd
index f28d7d7ec8487b4c9120d7afb298085fa685fd64..078acc2f6e02c2452ebbc1db2e965b160e21b271 100644
--- a/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew_inst.vhd
+++ b/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew_inst.vhd
@@ -87,4 +87,4 @@
pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
local_cal_success => CONNECTED_TO_local_cal_success, -- status.local_cal_success
local_cal_fail => CONNECTED_TO_local_cal_fail -- .local_cal_fail
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew_inst.vhd b/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew_inst.vhd
index bc2c6c638c1bb7020987de197404c792edbf8f95..3b0322e0e36cb56f60d3d3f9bccc74292913cdc6 100644
--- a/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew_inst.vhd
+++ b/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew_inst.vhd
@@ -87,4 +87,4 @@
pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
local_cal_success => CONNECTED_TO_local_cal_success, -- status.local_cal_success
local_cal_fail => CONNECTED_TO_local_cal_fail -- .local_cal_fail
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/unb2a_heater.vhd b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/unb2a_heater.vhd
index 1bec7004a129644a7bb6c0a32b16cad2d82329cf..7ec5cf8326429308fe34888cf3da656b229f08d8 100644
--- a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/unb2a_heater.vhd
+++ b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/unb2a_heater.vhd
@@ -65,8 +65,8 @@ entity unb2a_heater is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
QSFP_LED : out std_logic_vector(c_unb2_board_tr_qsfp_nof_leds - 1 downto 0)
);
@@ -402,4 +402,4 @@ begin
sla_in => reg_heater_mosi,
sla_out => reg_heater_miso
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard2a/designs/unb2a_led/src/vhdl/unb2a_led.vhd b/boards/uniboard2a/designs/unb2a_led/src/vhdl/unb2a_led.vhd
index ec0e7bbda57589b7ce742f6f6002a3a009f1676a..bee3d20f09f64398c3405e6592780157f472c0bf 100644
--- a/boards/uniboard2a/designs/unb2a_led/src/vhdl/unb2a_led.vhd
+++ b/boards/uniboard2a/designs/unb2a_led/src/vhdl/unb2a_led.vhd
@@ -228,4 +228,4 @@ begin
QSFP_LED(5) <= '1';
QSFP_LED(9) <= '1';
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/unb2a_minimal.vhd b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/unb2a_minimal.vhd
index d8412c52669005893c53288e6ac4a09da628c4a0..4d8716ead24ce00a699136880eee10185b81e3cd 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/unb2a_minimal.vhd
+++ b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/unb2a_minimal.vhd
@@ -64,8 +64,8 @@ entity unb2a_minimal is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
QSFP_LED : out std_logic_vector(c_unb2_board_tr_qsfp_nof_leds - 1 downto 0)
);
@@ -374,4 +374,4 @@ begin
QSFP_LED => QSFP_LED
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/tb_unb2a_test_10GbE.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/tb_unb2a_test_10GbE.vhd
index 8d227982d4156f3dc91cffccfae6f7a792258be0..c05fbd5a35fbbbb7e408e04b42a08104e9d02962 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/tb_unb2a_test_10GbE.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/tb_unb2a_test_10GbE.vhd
@@ -34,4 +34,4 @@ begin
generic map (
g_design_name => "unb2a_test_10GbE"
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/unb2a_test_10GbE.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/unb2a_test_10GbE.vhd
index 32d7a17a69d9e28391cc9911c775244d70c30512..d3bca5910d1c3887ee5c6326246b2f76f58b10e3 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/unb2a_test_10GbE.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/unb2a_test_10GbE.vhd
@@ -58,8 +58,8 @@ entity unb2a_test_10GbE is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic; -- Clock 10GbE front (qsfp) and ring lines
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/tb_unb2a_test_1GbE.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/tb_unb2a_test_1GbE.vhd
index d2e6bc62a9439fde98a9acf4895a59ff92e02f2e..4785c3f427839da8b69f8197ef6fcc6f11953371 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/tb_unb2a_test_1GbE.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/tb_unb2a_test_1GbE.vhd
@@ -36,4 +36,4 @@ begin
generic map (
g_design_name => "unb2a_test_1GbE"
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/unb2a_test_1GbE.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/unb2a_test_1GbE.vhd
index 4ff06caea179966e4024acfc3e9cced2faeb55a6..e2768c56ce3835908ff13604898b652445a1b5aa 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/unb2a_test_1GbE.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/unb2a_test_1GbE.vhd
@@ -62,8 +62,8 @@ entity unb2a_test_1GbE is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
QSFP_LED : out std_logic_vector(c_unb2_board_tr_qsfp_nof_leds - 1 downto 0)
);
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/tb_unb2a_test_all.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/tb_unb2a_test_all.vhd
index 4410231db7970337342fcdd2dc653664933b3cdf..0f64bfcff5768aac6de71d67e2b29ea8ea880e55 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/tb_unb2a_test_all.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/tb_unb2a_test_all.vhd
@@ -37,4 +37,4 @@ begin
g_design_name => "unb2a_test_all",
g_sim_model_ddr => FALSE
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/unb2a_test_all.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/unb2a_test_all.vhd
index 2b40ce695c6034ab6bab1e69c98e5b0bba0d4c4e..e683a3b7b5c9e814892f0d0af49c3208f428462f 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/unb2a_test_all.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/unb2a_test_all.vhd
@@ -59,8 +59,8 @@ entity unb2a_test_all is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic; -- Clock 10GbE front (qsfp) and ring lines
@@ -105,12 +105,12 @@ entity unb2a_test_all is
QSFP_SCL : inout std_logic_vector(c_unb2_board_tr_qsfp.i2c_w - 1 downto 0);
-- SO-DIMM Memory Bank I
- MB_I_in : IN t_tech_ddr4_phy_in;
+ MB_I_in : in t_tech_ddr4_phy_in;
MB_I_IO : inout t_tech_ddr4_phy_io;
MB_I_OU : out t_tech_ddr4_phy_ou;
-- SO-DIMM Memory Bank II
- MB_II_in : IN t_tech_ddr4_phy_in;
+ MB_II_in : in t_tech_ddr4_phy_in;
MB_II_IO : inout t_tech_ddr4_phy_io;
MB_II_OU : out t_tech_ddr4_phy_ou;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/tb_unb2a_test_ddr_MB_I.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/tb_unb2a_test_ddr_MB_I.vhd
index ae93d7884fff6dabbdb56b4816591392022323ae..fde2a27b0b514f90e1425a67f733da37528948f1 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/tb_unb2a_test_ddr_MB_I.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/tb_unb2a_test_ddr_MB_I.vhd
@@ -37,4 +37,4 @@ begin
g_design_name => "unb2a_test_ddr_MB_I",
g_sim_model_ddr => FALSE
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/unb2a_test_ddr_MB_I.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/unb2a_test_ddr_MB_I.vhd
index 70a061a6a8e97758a097b02ee4529e67c213a6a7..29ebc518bfc164a2a20f6dcc7e351413633203e7 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/unb2a_test_ddr_MB_I.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/unb2a_test_ddr_MB_I.vhd
@@ -63,14 +63,14 @@ entity unb2a_test_ddr_MB_I is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
-- DDR reference clocks
MB_I_REF_CLK : in std_logic; -- Reference clock for MB_I
-- SO-DIMM Memory Bank I
- MB_I_in : IN t_tech_ddr4_phy_in;
+ MB_I_in : in t_tech_ddr4_phy_in;
MB_I_IO : inout t_tech_ddr4_phy_io;
MB_I_OU : out t_tech_ddr4_phy_ou;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/tb_unb2a_test_ddr_MB_II.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/tb_unb2a_test_ddr_MB_II.vhd
index a90a597a775190bd88270125fa0d5eaba3f13d66..2da5c6ca5546582a8d97a9df94a22af61d127dc8 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/tb_unb2a_test_ddr_MB_II.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/tb_unb2a_test_ddr_MB_II.vhd
@@ -37,4 +37,4 @@ begin
g_design_name => "unb2a_test_ddr_MB_II",
g_sim_model_ddr => FALSE
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/unb2a_test_ddr_MB_II.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/unb2a_test_ddr_MB_II.vhd
index 1ca8a1d3bc3630fea125b778231837c373b4c666..b53ea7bf0bd1c85bb50c9601ec727a0d81d2461b 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/unb2a_test_ddr_MB_II.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/unb2a_test_ddr_MB_II.vhd
@@ -63,14 +63,14 @@ entity unb2a_test_ddr_MB_II is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
-- DDR reference clocks
MB_II_REF_CLK : in std_logic; -- Reference clock for MB_II
-- SO-DIMM Memory Bank II
- MB_II_in : IN t_tech_ddr4_phy_in;
+ MB_II_in : in t_tech_ddr4_phy_in;
MB_II_IO : inout t_tech_ddr4_phy_io;
MB_II_OU : out t_tech_ddr4_phy_ou;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/tb_unb2a_test_ddr_MB_I_II.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/tb_unb2a_test_ddr_MB_I_II.vhd
index 977ca07ad541e82054bf771265100fb952670f07..eb27399e153c97293b9ec12ced461a31770c3865 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/tb_unb2a_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/tb_unb2a_test_ddr_MB_I_II.vhd
@@ -37,4 +37,4 @@ begin
g_design_name => "unb2a_test_ddr_MB_I_II",
g_sim_model_ddr => FALSE
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/unb2a_test_ddr_MB_I_II.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/unb2a_test_ddr_MB_I_II.vhd
index e4c6aa8dc61bbff5cbdb71348a87f008c7bd5b90..e7aae749768bc9cb8132385ac80f4a8006ef553f 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/unb2a_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/unb2a_test_ddr_MB_I_II.vhd
@@ -63,20 +63,20 @@ entity unb2a_test_ddr_MB_I_II is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
-- DDR reference clocks
MB_I_REF_CLK : in std_logic; -- Reference clock for MB_I
MB_II_REF_CLK : in std_logic; -- Reference clock for MB_II
-- SO-DIMM Memory Bank I
- MB_I_in : IN t_tech_ddr4_phy_in;
+ MB_I_in : in t_tech_ddr4_phy_in;
MB_I_IO : inout t_tech_ddr4_phy_io;
MB_I_OU : out t_tech_ddr4_phy_ou;
-- SO-DIMM Memory Bank II
- MB_II_in : IN t_tech_ddr4_phy_in;
+ MB_II_in : in t_tech_ddr4_phy_in;
MB_II_IO : inout t_tech_ddr4_phy_io;
MB_II_OU : out t_tech_ddr4_phy_ou;
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd
index e8e2abb6017af27712bafad63ff733cb8c11c63d..1ac78b3774badaf9b9f8b8a51ed1495edbda721b 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd
@@ -396,4 +396,4 @@ package qsys_unb2a_test_pkg is
-end qsys_unb2a_test_pkg;
+end qsys_unb2a_test_pkg;
\ No newline at end of file
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/udp_stream.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/udp_stream.vhd
index 997c9b7f7be4157ef60b3cb26461326722034fd1..a165a9131e40a14593ca014257144a4f76a2cc48 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/udp_stream.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/udp_stream.vhd
@@ -354,4 +354,4 @@ begin
in_sosi_arr => diag_data_buf_snk_in_arr
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd
index bbe99d15d86da0ea94f4f8af7f5a6da8337caa5d..8f213eb6c111fa31541dc59133a2851f91dda59d 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd
@@ -71,8 +71,8 @@ entity unb2a_test is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
@@ -123,12 +123,12 @@ entity unb2a_test is
QSFP_RST : inout std_logic;
-- SO-DIMM Memory Bank I
- MB_I_in : IN t_tech_ddr4_phy_in := c_tech_ddr4_phy_in_x;
+ MB_I_in : in t_tech_ddr4_phy_in := c_tech_ddr4_phy_in_x;
MB_I_IO : inout t_tech_ddr4_phy_io;
MB_I_OU : out t_tech_ddr4_phy_ou;
-- SO-DIMM Memory Bank II
- MB_II_in : IN t_tech_ddr4_phy_in := c_tech_ddr4_phy_in_x;
+ MB_II_in : in t_tech_ddr4_phy_in := c_tech_ddr4_phy_in_x;
MB_II_IO : inout t_tech_ddr4_phy_io;
MB_II_OU : out t_tech_ddr4_phy_ou;
@@ -148,13 +148,13 @@ architecture str of unb2a_test is
-- Revision controlled constants
constant c_use_1GbE : boolean := FALSE; --g_design_name="unb2a_test_1GbE" OR g_design_name="unb2a_test_10GbE" OR g_design_name="unb2a_test_all";
- constant c_use_10GbE : boolean := g_design_name ="unb2a_test_10GbE " or g_design_name ="unb2a_test_all ";
+ constant c_use_10GbE : boolean := g_design_name ="unb2a_test_10GbE " or g_design_name ="unb2a_test_all ";
constant c_use_10GbE_qsfp : boolean := c_use_10GbE;
constant c_use_10GbE_ring : boolean := FALSE; --c_use_10GbE;
constant c_use_10GbE_back0 : boolean := FALSE; --c_use_10GbE;
constant c_use_10GbE_back1 : boolean := FALSE; --c_use_10GbE;
- constant c_use_MB_I : boolean := g_design_name ="unb2a_test_ddr_MB_I " or g_design_name ="unb2a_test_ddr_MB_I_II " or g_design_name ="unb2a_test_all ";
- constant c_use_MB_II : boolean := g_design_name ="unb2a_test_ddr_MB_II " or g_design_name ="unb2a_test_ddr_MB_I_II " or g_design_name ="unb2a_test_all ";
+ constant c_use_MB_I : boolean := g_design_name ="unb2a_test_ddr_MB_I " or g_design_name ="unb2a_test_ddr_MB_I_II " or g_design_name ="unb2a_test_all ";
+ constant c_use_MB_II : boolean := g_design_name ="unb2a_test_ddr_MB_II " or g_design_name ="unb2a_test_ddr_MB_I_II " or g_design_name ="unb2a_test_all ";
-- transceivers
constant c_nof_qsfp : natural := c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w;
@@ -1269,4 +1269,4 @@ begin
);
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test_pkg.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test_pkg.vhd
index 1aed2beb13860ef748495f4c5f19e7a2e9f21c16..6b7df99fcf4e3e41423505afed5b73e94a8967e6 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test_pkg.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test_pkg.vhd
@@ -29,7 +29,7 @@ package unb2a_test_pkg is
-- dp_offload_tx
--CONSTANT c_nof_hdr_fields : NATURAL := 1+3+12+4+2; -- Total header bits = 384 = 6 64b words
- constant c_nof_hdr_fields : natural := 3 +12 + 4 + 2; -- Total header bits = 384 = 6 64b words
+ constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 2; -- Total header bits = 384 = 6 64b words
constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( --( field_name_pad("align" ), " ", 16, field_default(0) ),
( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
@@ -54,6 +54,6 @@ package unb2a_test_pkg is
( field_name_pad("usr_bsn" ), " ", 47, field_default(0) ));
--CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "1001"&"111111111100"&"0011"&"00";
- constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "001" &"111111111100 " &"0011 " &"00 ";
+ constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "001" &"111111111100 " &"0011 " &"00 ";
-end unb2a_test_pkg;
+end unb2a_test_pkg;
\ No newline at end of file
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/ctrl_unb2_board.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/ctrl_unb2_board.vhd
index 18e00ad1268875914d1cdbd83bc2d1f2392e3d0f..b66a3ead4150a13aef086cbd0989b67f70e0088b 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/ctrl_unb2_board.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/ctrl_unb2_board.vhd
@@ -243,8 +243,8 @@ entity ctrl_unb2_board is
-- 1GbE Control Interface
ETH_CLK : in std_logic; -- 125 MHz
- ETH_SGin : IN std_logic_vector(c_unb2_board_nof_eth - 1 downto 0) := (others => '0');
- ETH_SGout : OUT std_logic_vector(c_unb2_board_nof_eth - 1 downto 0)
+ ETH_SGin : in std_logic_vector(c_unb2_board_nof_eth - 1 downto 0) := (others => '0');
+ ETH_SGout : out std_logic_vector(c_unb2_board_nof_eth - 1 downto 0)
);
end ctrl_unb2_board;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_sens.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_sens.vhd
index 52011c00954d28fb3a996257aeff1ba8875eb6d4..cb4b8bbc7f01dcc0e60f2b8b4b8d7a22f4472156 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_sens.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_sens.vhd
@@ -118,4 +118,4 @@ begin
-- temp_high is 7 bits, preceded by a '0' to allow only positive temps to be set.
temp_alarm <= '1' when (signed(sens_data(0)) > signed('0' & temp_high)) else '0';
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_system_info.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_system_info.vhd
index cd4cefeee1d62f77d41f27f2d4b7e5c601fa7a22..7d19de3788afb0ee8b30b080e0add06d8e9f6680 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_system_info.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_system_info.vhd
@@ -72,7 +72,7 @@ architecture str of mms_unb2_board_system_info is
-- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
-- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
- constant c_mif_name : string := sel_a_b(g_sim, "UNUSED", sel_a_b((g_design_name ="UNUSED "), g_design_name, c_path_prefix & g_design_name & ".mif"));
+ constant c_mif_name : string := sel_a_b(g_sim, "UNUSED", sel_a_b((g_design_name ="UNUSED "), g_design_name, c_path_prefix & g_design_name & ".mif"));
constant c_rom_addr_w : natural := 10; -- 2^10 = 1024 addresses * 32 bits = 4 kiB
@@ -137,4 +137,4 @@ begin
rd_val => rom_miso.rdval
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_fpga_sens.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_fpga_sens.vhd
index 2389544a8ef3da4929c3fe4d801001865262e590..ebeb1fe33738f512d41a47e93a5972a34521446d 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_fpga_sens.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_fpga_sens.vhd
@@ -118,4 +118,4 @@ begin
-- temp_high is 7 bits, preceded by a '0' to allow only positive temps to be set.
temp_alarm <= '0'; --<= '1' WHEN (SIGNED(sens_data(0)) > SIGNED('0' & temp_high)) ELSE '0';
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_ring_io.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_ring_io.vhd
index 86b629682fa17af0789cb629e7dbdee40d7fe18e..2ac09a27cef3aa111dd48d62c7cd6b6fd5a06fae 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_ring_io.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_ring_io.vhd
@@ -32,7 +32,7 @@ entity unb2_board_ring_io is
serial_tx_arr : in std_logic_vector(g_nof_ring_bus * c_unb2_board_tr_ring.bus_w - 1 downto 0) := (others => '0');
serial_rx_arr : out std_logic_vector(g_nof_ring_bus * c_unb2_board_tr_ring.bus_w - 1 downto 0);
- RinG_RX : IN t_unb2_board_ring_bus_2arr(g_nof_ring_bus - 1 downto 0) := (others => (others => '0'));
+ RinG_RX : in t_unb2_board_ring_bus_2arr(g_nof_ring_bus - 1 downto 0) := (others => (others => '0'));
RING_TX : out t_unb2_board_ring_bus_2arr(g_nof_ring_bus - 1 downto 0)
);
end unb2_board_ring_io;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info_reg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info_reg.vhd
index 57bbeb8b6f54ad27d8631067ec4483dd939c747c..805540631a8e7e67481c1a9de50c0a2f3d5609e0 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info_reg.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info_reg.vhd
@@ -140,4 +140,4 @@ begin
end process;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_reg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_reg.vhd
index ecf702091aba25ff005a63911671529f88451692..3b03b7f01a9332d0e0899ea151a995fa6fd32467 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_reg.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_reg.vhd
@@ -86,4 +86,4 @@ begin
end if;
end process;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_mms_unb2_board_sens.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
index 2f6e79a242b03a14e3895adbfa6b2f571a2696d1..36f4d812c5dd801641ef3c328c96d427bbea2b27 100644
--- a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
@@ -211,4 +211,4 @@ begin
ana_volt_adin => c_uniboard_adin
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_arp_ping/src/vhdl/unb2b_arp_ping.vhd b/boards/uniboard2b/designs/unb2b_arp_ping/src/vhdl/unb2b_arp_ping.vhd
index 84e75f919e2d9248509344364fb8b5b1c30b0f3b..a74f800be1b7b2c1e00265f922faaff2feac5ad3 100644
--- a/boards/uniboard2b/designs/unb2b_arp_ping/src/vhdl/unb2b_arp_ping.vhd
+++ b/boards/uniboard2b/designs/unb2b_arp_ping/src/vhdl/unb2b_arp_ping.vhd
@@ -74,8 +74,8 @@ entity unb2b_arp_ping is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0)
);
@@ -387,4 +387,4 @@ begin
QSFP_LED => QSFP_LED
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/unb2b_heater.vhd b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/unb2b_heater.vhd
index af54c7cc4a73e2b3491279a037239b7bd4f3391d..2cedfb970197cd8e6d04bc6fda170d7259d532d9 100644
--- a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/unb2b_heater.vhd
+++ b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/unb2b_heater.vhd
@@ -65,8 +65,8 @@ entity unb2b_heater is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0)
);
@@ -406,4 +406,4 @@ begin
sla_in => reg_heater_mosi,
sla_out => reg_heater_miso
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
index b7b0b9421b284e8fdc22266e004bd1d10a7bb772..cd51286875c6c394041a42ddf10b6ab7a6c4ac10 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
@@ -15,4 +15,4 @@
outclk_1 => CONNECTED_TO_outclk_1, -- outclk1.clk
refclk => CONNECTED_TO_refclk, -- refclk.clk
rst => CONNECTED_TO_rst -- reset.reset
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
index 0464262396a9a713f4d39a1f4723b9edd3dd61fa..0a668a0c8a248b41b37084b169ceddc5e159c81d 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
@@ -11,4 +11,4 @@
clk => CONNECTED_TO_clk, -- clk.clk
in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
index 425df4f7db5953159a1866aca009b90f0a5b1f4a..fe390e7550d75be13a64ce3da19fe5ae7ea1463f 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
@@ -11,4 +11,4 @@
clk => CONNECTED_TO_clk, -- clk.clk
in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
index 213f6db90380d5cc7aaa7404b91ca84c84dc4f93..8e147e66f0354b598da92c26f43986f20504ec1a 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
@@ -159,4 +159,4 @@
reset_out5 => CONNECTED_TO_reset_out5, -- reset_out5.reset
reset_out6 => CONNECTED_TO_reset_out6, -- reset_out6.reset
reset_out7 => CONNECTED_TO_reset_out7 -- reset_out7.reset
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
index 4aa7f3aec3376b44a6c322e7ce6998d1be984757..4a4dd5d437232c07be643a76dc8107a953d65a4d 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
@@ -21,4 +21,4 @@
rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
rx_is_lockedtodata => CONNECTED_TO_rx_is_lockedtodata, -- rx_is_lockedtodata.rx_is_lockedtodata
rx_ready => CONNECTED_TO_rx_ready -- rx_ready.rx_ready
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
index b3899a24db71a83417108dbf99209a00c51af798..a5796f3aaa2accf706b6b116457f9898db29a702 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
@@ -13,4 +13,4 @@
in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
index 5df9fb0a9a23d44ed9dc84a08ad17fd635aa24ac..c135dff113ded97e10aff71bc85dabdfe00ed05f 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
@@ -13,4 +13,4 @@
in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
index 2f3daf68560be0b5aa56449818ecd126d5e80d0a..6b5b96f4f27103f72ee7e9d78f14af237651d704 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
@@ -97,4 +97,4 @@
sof => CONNECTED_TO_sof, -- sof.export
somf => CONNECTED_TO_somf, -- somf.export
sysref => CONNECTED_TO_sysref -- sysref.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
index 4d98d388128a9021807c47c80bdbb7985f3724c3..4c240b329fc1417edb8549e12f7a9e58dfb0a4b5 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
@@ -13,4 +13,4 @@
in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
index e9f2adf7d608e83045c0f39d64da8155b088f674..327b8730c779a44291ceba2819a55c1737aef04f 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
@@ -41,4 +41,4 @@
csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
index a6ccb8cfd25f0f0e88194637e9d418cedcffdafc..3ee82d53fc94895496d4cd2d5221dfcfaa359acf 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
@@ -41,4 +41,4 @@
csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
index c4db7d7c3f2edeee7bc4d5a3b2a992fd702d7939..a7a03b2b98e7d79044486d0643589e5b2c0ab2d2 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
@@ -673,18 +673,18 @@ package body common_pkg is
variable v_result : std_logic := '0';
begin
-- default any unused, the stage results will be kept in the LSBits and the last result in bit 0
- if operation ="and " then v_stage_arr := (others => (others => '1'));
- elsif operation ="or " then v_stage_arr := (others => (others => '0'));
- elsif operation ="xor " then v_stage_arr := (others => (others => '0'));
+ if operation ="and " then v_stage_arr := (others => (others => '1'));
+ elsif operation ="or " then v_stage_arr := (others => (others => '0'));
+ elsif operation ="xor " then v_stage_arr := (others => (others => '0'));
else
assert TRUE report "common_pkg: Unsupported vector_tree operation" severity FAILURE;
end if;
v_stage_arr(-1)(c_slv_w - 1 downto 0) := slv; -- any unused input c_w : c_slv_w bits have void default value
for J in 0 to c_nof_stages - 1 loop
for I in 0 to c_w / (2 ** (J + 1)) - 1 loop
- if operation ="and " then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) and v_stage_arr(J - 1)(2 * I + 1);
- elsif operation ="or " then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) or v_stage_arr(J - 1)(2 * I + 1);
- elsif operation ="xor " then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) xor v_stage_arr(J - 1)(2 * I + 1);
+ if operation ="and " then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) and v_stage_arr(J - 1)(2 * I + 1);
+ elsif operation ="or " then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) or v_stage_arr(J - 1)(2 * I + 1);
+ elsif operation ="xor " then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) xor v_stage_arr(J - 1)(2 * I + 1);
end if;
end loop;
end loop;
@@ -853,7 +853,7 @@ package body common_pkg is
variable vR : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
vR := R;
for I in vL'range loop
vP(I) := vL(I) + vR(I);
@@ -866,7 +866,7 @@ package body common_pkg is
variable vL : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
for I in vL'range loop
vP(I) := vL(I) + R;
end loop;
@@ -884,7 +884,7 @@ package body common_pkg is
variable vR : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
vR := R;
for I in vL'range loop
vP(I) := vL(I) - vR(I);
@@ -898,7 +898,7 @@ package body common_pkg is
variable vR : t_natural_arr(w - 1 downto 0);
variable vP : t_integer_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
vR := R;
for I in vL'range loop
vP(I) := vL(I) - vR(I);
@@ -911,7 +911,7 @@ package body common_pkg is
variable vL : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
for I in vL'range loop
vP(I) := vL(I) - R;
end loop;
@@ -936,7 +936,7 @@ package body common_pkg is
variable vR : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
vR := R;
for I in vL'range loop
vP(I) := vL(I) * vR(I);
@@ -949,7 +949,7 @@ package body common_pkg is
variable vL : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
for I in vL'range loop
vP(I) := vL(I) * R;
end loop;
@@ -967,7 +967,7 @@ package body common_pkg is
variable vR : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
vR := R;
for I in vL'range loop
vP(I) := vL(I) / vR(I);
@@ -980,7 +980,7 @@ package body common_pkg is
variable vL : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
for I in vL'range loop
vP(I) := vL(I) / R;
end loop;
@@ -1278,7 +1278,7 @@ package body common_pkg is
function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string is begin if sel < 9 then return sel_n(sel, a, b, c, d, e, f, g, h, i); else return j; end if; end;
function array_init(init : std_logic; nof : natural) return std_logic_vector is
- variable v_arr : std_logic_vector(0 TO nof - 1);
+ variable v_arr : std_logic_vector(0 to nof - 1);
begin
for I in v_arr'range loop
v_arr(I) := init;
@@ -2023,7 +2023,7 @@ package body common_pkg is
variable v_b : std_logic_vector(a'length - 1 downto 0);
begin
for I in v_a'range loop
- v_b(a'length - 1 -I) := v_a(I);
+ v_b(a'length - 1 - I) := v_a(I);
end loop;
return v_b;
end;
@@ -2038,7 +2038,7 @@ package body common_pkg is
variable v_b : t_slv_32_arr(a'length - 1 downto 0);
begin
for I in v_a'range loop
- v_b(a'length - 1 -I) := v_a(I);
+ v_b(a'length - 1 - I) := v_a(I);
end loop;
return v_b;
end;
@@ -2048,7 +2048,7 @@ package body common_pkg is
variable v_b : t_integer_arr(a'length - 1 downto 0);
begin
for I in v_a'range loop
- v_b(a'length - 1 -I) := v_a(I);
+ v_b(a'length - 1 - I) := v_a(I);
end loop;
return v_b;
end;
@@ -2058,7 +2058,7 @@ package body common_pkg is
variable v_b : t_natural_arr(a'length - 1 downto 0);
begin
for I in v_a'range loop
- v_b(a'length - 1 -I) := v_a(I);
+ v_b(a'length - 1 - I) := v_a(I);
end loop;
return v_b;
end;
@@ -2068,7 +2068,7 @@ package body common_pkg is
variable v_b : t_nat_natural_arr(a'length - 1 downto 0);
begin
for I in v_a'range loop
- v_b(a'length - 1 -I) := v_a(I);
+ v_b(a'length - 1 - I) := v_a(I);
end loop;
return v_b;
end;
@@ -2128,7 +2128,7 @@ package body common_pkg is
function slice_up(str : string; width : natural; i : natural; pad_char : character) return string is
variable padded_str : string(1 to width) := (others => '0');
begin
- padded_str := pad(str(i * width + 1 to (i +1) * width), width, '0');
+ padded_str := pad(str(i * width + 1 to (i + 1) * width), width, '0');
return padded_str;
end;
@@ -2225,7 +2225,7 @@ package body common_pkg is
-- Get the index K in the select setting array for the reorder2 cell on stage I and row J in a reorder network with N stages
function func_common_reorder2_get_select_index(I, J, N : natural) return integer is
- constant c_nof_reorder2_per_odd_stage : natural := N /2;
+ constant c_nof_reorder2_per_odd_stage : natural := N / 2;
constant c_nof_reorder2_per_even_stage : natural := (N - 1) / 2;
variable v_nof_odd_stages : natural;
variable v_nof_even_stages : natural;
@@ -2347,7 +2347,7 @@ package body common_pkg is
-- Create Pfactor SCLK periods within this DCLK period
SCLK <= '0';
if Pfactor > 1 then
- for I in 0 to 2 * Pfactor - 1 -2 loop
+ for I in 0 to 2 * Pfactor - 1 - 2 loop
wait for v_speriod / 2;
SCLK <= not SCLK;
end loop;
@@ -2359,4 +2359,4 @@ package body common_pkg is
wait;
end proc_common_dclk_generate_sclk;
-end common_pkg;
+end common_pkg;
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
index a9d8a6610cb8dd3dd9d765ffb11a28a45433ccfa..f75f3e2cc937b1b9b3cd70a802611cea70a10c27 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
@@ -265,7 +265,7 @@ package dp_stream_pkg is
function REPLICATE_DP_DATA( seq : std_logic_vector ) return std_logic_vector; -- replicate seq as often as fits in c_dp_stream_data_w
function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w : natural) return std_logic_vector; -- unreplicate data to width seq_w, return low seq_w bits and set mismatch MSbits bits to '1'
- function TO_DP_SOSI_unsigned(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : UNSIGNED) return t_dp_sosi_unsigned;
+ function TO_DP_SOSI_unsigned(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned;
-- Keep part of head data and combine part of tail data, use the other sosi from head_sosi
function func_dp_data_shift_first(head_sosi, tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail : natural) return t_dp_sosi;
@@ -590,7 +590,7 @@ package body dp_stream_pkg is
return v_vec(c_data_w - 1 downto 0);
end UNREPLICATE_DP_DATA;
- function TO_DP_SOSI_unsigned(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : UNSIGNED) return t_dp_sosi_unsigned is
+ function TO_DP_SOSI_unsigned(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned is
variable v_sosi_unsigned : t_dp_sosi_unsigned;
begin
v_sosi_unsigned.sync := sync;
@@ -737,8 +737,8 @@ package body dp_stream_pkg is
for I in dp'range loop
if mask(I) = '1' then
v_any := '1';
- if str ="READY " then v_vec(I) := dp(I).ready;
- elsif str ="XON " then v_vec(I) := dp(I).xon;
+ if str ="READY " then v_vec(I) := dp(I).ready;
+ elsif str ="XON " then v_vec(I) := dp(I).xon;
else report "Error in func_dp_stream_arr_and for t_dp_siso_arr";
end if;
end if;
@@ -759,10 +759,10 @@ package body dp_stream_pkg is
for I in dp'range loop
if mask(I) = '1' then
v_any := '1';
- if str ="VALID " then v_vec(I) := dp(I).valid;
- elsif str ="SOP " then v_vec(I) := dp(I).sop;
- elsif str ="EOP " then v_vec(I) := dp(I).eop;
- elsif str ="SYNC " then v_vec(I) := dp(I).sync;
+ if str ="VALID " then v_vec(I) := dp(I).valid;
+ elsif str ="SOP " then v_vec(I) := dp(I).sop;
+ elsif str ="EOP " then v_vec(I) := dp(I).eop;
+ elsif str ="SYNC " then v_vec(I) := dp(I).sync;
else report "Error in func_dp_stream_arr_and for t_dp_sosi_arr";
end if;
end if;
@@ -795,8 +795,8 @@ package body dp_stream_pkg is
for I in dp'range loop
if mask(I) = '1' then
v_any := '1';
- if str ="READY " then v_vec(I) := dp(I).ready;
- elsif str ="XON " then v_vec(I) := dp(I).xon;
+ if str ="READY " then v_vec(I) := dp(I).ready;
+ elsif str ="XON " then v_vec(I) := dp(I).xon;
else report "Error in func_dp_stream_arr_or for t_dp_siso_arr";
end if;
end if;
@@ -817,10 +817,10 @@ package body dp_stream_pkg is
for I in dp'range loop
if mask(I) = '1' then
v_any := '1';
- if str ="VALID " then v_vec(I) := dp(I).valid;
- elsif str ="SOP " then v_vec(I) := dp(I).sop;
- elsif str ="EOP " then v_vec(I) := dp(I).eop;
- elsif str ="SYNC " then v_vec(I) := dp(I).sync;
+ if str ="VALID " then v_vec(I) := dp(I).valid;
+ elsif str ="SOP " then v_vec(I) := dp(I).sop;
+ elsif str ="EOP " then v_vec(I) := dp(I).eop;
+ elsif str ="SYNC " then v_vec(I) := dp(I).sync;
else report "Error in func_dp_stream_arr_or for t_dp_sosi_arr";
end if;
end if;
@@ -852,8 +852,8 @@ package body dp_stream_pkg is
variable v_slv : std_logic_vector(dp'range) := slv; -- map to ensure same range as for dp
begin
for I in dp'range loop
- if str ="READY " then v_dp(I).ready := v_slv(I);
- elsif str ="XON " then v_dp(I).xon := v_slv(I);
+ if str ="READY " then v_dp(I).ready := v_slv(I);
+ elsif str ="XON " then v_dp(I).xon := v_slv(I);
else report "Error in func_dp_stream_arr_set for t_dp_siso_arr";
end if;
end loop;
@@ -865,10 +865,10 @@ package body dp_stream_pkg is
variable v_slv : std_logic_vector(dp'range) := slv; -- map to ensure same range as for dp
begin
for I in dp'range loop
- if str ="VALID " then v_dp(I).valid := v_slv(I);
- elsif str ="SOP " then v_dp(I).sop := v_slv(I);
- elsif str ="EOP " then v_dp(I).eop := v_slv(I);
- elsif str ="SYNC " then v_dp(I).sync := v_slv(I);
+ if str ="VALID " then v_dp(I).valid := v_slv(I);
+ elsif str ="SOP " then v_dp(I).sop := v_slv(I);
+ elsif str ="EOP " then v_dp(I).eop := v_slv(I);
+ elsif str ="SYNC " then v_dp(I).sync := v_slv(I);
else report "Error in func_dp_stream_arr_set for t_dp_sosi_arr";
end if;
end loop;
@@ -891,8 +891,8 @@ package body dp_stream_pkg is
variable v_ctrl : std_logic_vector(dp'range);
begin
for I in dp'range loop
- if str ="READY " then v_ctrl(I) := dp(I).ready;
- elsif str ="XON " then v_ctrl(I) := dp(I).xon;
+ if str ="READY " then v_ctrl(I) := dp(I).ready;
+ elsif str ="XON " then v_ctrl(I) := dp(I).xon;
else report "Error in func_dp_stream_arr_get for t_dp_siso_arr";
end if;
end loop;
@@ -903,10 +903,10 @@ package body dp_stream_pkg is
variable v_ctrl : std_logic_vector(dp'range);
begin
for I in dp'range loop
- if str ="VALID " then v_ctrl(I) := dp(I).valid;
- elsif str ="SOP " then v_ctrl(I) := dp(I).sop;
- elsif str ="EOP " then v_ctrl(I) := dp(I).eop;
- elsif str ="SYNC " then v_ctrl(I) := dp(I).sync;
+ if str ="VALID " then v_ctrl(I) := dp(I).valid;
+ elsif str ="SOP " then v_ctrl(I) := dp(I).sop;
+ elsif str ="EOP " then v_ctrl(I) := dp(I).eop;
+ elsif str ="SYNC " then v_ctrl(I) := dp(I).sync;
else report "Error in func_dp_stream_arr_get for t_dp_sosi_arr";
end if;
end loop;
@@ -1245,12 +1245,12 @@ package body dp_stream_pkg is
function func_dp_stream_set_data(dp : t_dp_sosi; slv : std_logic_vector; str : string) return t_dp_sosi is
variable v_dp : t_dp_sosi := dp;
begin
- if str ="DATA " then v_dp.data := RESIZE_DP_DATA(slv);
- elsif str ="DSP " then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ if str ="DATA " then v_dp.data := RESIZE_DP_DATA(slv);
+ elsif str ="DSP " then v_dp.re := RESIZE_DP_DSP_DATA(slv);
v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str ="RE " then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- elsif str ="IM " then v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str ="all " then v_dp.data := RESIZE_DP_DATA(slv);
+ elsif str ="RE " then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ elsif str ="IM " then v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str ="all " then v_dp.data := RESIZE_DP_DATA(slv);
v_dp.re := RESIZE_DP_DSP_DATA(slv);
v_dp.im := RESIZE_DP_DSP_DATA(slv);
else report "Error in func_dp_stream_set_data for t_dp_sosi";
@@ -1420,10 +1420,10 @@ package body dp_stream_pkg is
v_src_out.im := (others => '0');
for i in 0 to nof_data - 1 loop
v_in_data := snk_in.data((i + 1) * in_w - 1 downto i * in_w);
- if data_representation ="unsigned " then -- treat data as unsigned
+ if data_representation ="unsigned " then -- treat data as unsigned
v_out_data := RESIZE_UVEC(v_in_data, out_w);
else
- if data_representation ="signed " then -- treat data as signed
+ if data_representation ="signed " then -- treat data as signed
v_out_data := RESIZE_SVEC(v_in_data, out_w);
else
-- treat data as complex
@@ -1486,4 +1486,4 @@ package body dp_stream_pkg is
return src_out_arr(0);
end;
-end dp_stream_pkg;
+end dp_stream_pkg;
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
index 3ca37696f6210b475ad03f17fa917465a1738f28..74e8f2b1e63dd3b34662c44f06b72139cb8dedda 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
@@ -106,7 +106,7 @@ package eth_pkg is
-- . write/read back registers
type t_eth_demux_ports_arr is array(1 to c_eth_nof_udp_ports) of std_logic_vector(c_network_udp_port_w - 1 downto 0);
type t_eth_mm_reg_demux is record
- udp_ports_en : std_logic_vector(1 TO c_eth_nof_udp_ports); -- [16]
+ udp_ports_en : std_logic_vector(1 to c_eth_nof_udp_ports); -- [16]
udp_ports : t_eth_demux_ports_arr; -- [15:0]
end record;
@@ -349,4 +349,4 @@ package body eth_pkg is
return v_reg;
end func_eth_mm_reg_status;
-end eth_pkg;
+end eth_pkg;
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
index c4db7d7c3f2edeee7bc4d5a3b2a992fd702d7939..a7a03b2b98e7d79044486d0643589e5b2c0ab2d2 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
@@ -673,18 +673,18 @@ package body common_pkg is
variable v_result : std_logic := '0';
begin
-- default any unused, the stage results will be kept in the LSBits and the last result in bit 0
- if operation ="and " then v_stage_arr := (others => (others => '1'));
- elsif operation ="or " then v_stage_arr := (others => (others => '0'));
- elsif operation ="xor " then v_stage_arr := (others => (others => '0'));
+ if operation ="and " then v_stage_arr := (others => (others => '1'));
+ elsif operation ="or " then v_stage_arr := (others => (others => '0'));
+ elsif operation ="xor " then v_stage_arr := (others => (others => '0'));
else
assert TRUE report "common_pkg: Unsupported vector_tree operation" severity FAILURE;
end if;
v_stage_arr(-1)(c_slv_w - 1 downto 0) := slv; -- any unused input c_w : c_slv_w bits have void default value
for J in 0 to c_nof_stages - 1 loop
for I in 0 to c_w / (2 ** (J + 1)) - 1 loop
- if operation ="and " then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) and v_stage_arr(J - 1)(2 * I + 1);
- elsif operation ="or " then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) or v_stage_arr(J - 1)(2 * I + 1);
- elsif operation ="xor " then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) xor v_stage_arr(J - 1)(2 * I + 1);
+ if operation ="and " then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) and v_stage_arr(J - 1)(2 * I + 1);
+ elsif operation ="or " then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) or v_stage_arr(J - 1)(2 * I + 1);
+ elsif operation ="xor " then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) xor v_stage_arr(J - 1)(2 * I + 1);
end if;
end loop;
end loop;
@@ -853,7 +853,7 @@ package body common_pkg is
variable vR : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
vR := R;
for I in vL'range loop
vP(I) := vL(I) + vR(I);
@@ -866,7 +866,7 @@ package body common_pkg is
variable vL : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
for I in vL'range loop
vP(I) := vL(I) + R;
end loop;
@@ -884,7 +884,7 @@ package body common_pkg is
variable vR : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
vR := R;
for I in vL'range loop
vP(I) := vL(I) - vR(I);
@@ -898,7 +898,7 @@ package body common_pkg is
variable vR : t_natural_arr(w - 1 downto 0);
variable vP : t_integer_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
vR := R;
for I in vL'range loop
vP(I) := vL(I) - vR(I);
@@ -911,7 +911,7 @@ package body common_pkg is
variable vL : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
for I in vL'range loop
vP(I) := vL(I) - R;
end loop;
@@ -936,7 +936,7 @@ package body common_pkg is
variable vR : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
vR := R;
for I in vL'range loop
vP(I) := vL(I) * vR(I);
@@ -949,7 +949,7 @@ package body common_pkg is
variable vL : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
for I in vL'range loop
vP(I) := vL(I) * R;
end loop;
@@ -967,7 +967,7 @@ package body common_pkg is
variable vR : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
vR := R;
for I in vL'range loop
vP(I) := vL(I) / vR(I);
@@ -980,7 +980,7 @@ package body common_pkg is
variable vL : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
for I in vL'range loop
vP(I) := vL(I) / R;
end loop;
@@ -1278,7 +1278,7 @@ package body common_pkg is
function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string is begin if sel < 9 then return sel_n(sel, a, b, c, d, e, f, g, h, i); else return j; end if; end;
function array_init(init : std_logic; nof : natural) return std_logic_vector is
- variable v_arr : std_logic_vector(0 TO nof - 1);
+ variable v_arr : std_logic_vector(0 to nof - 1);
begin
for I in v_arr'range loop
v_arr(I) := init;
@@ -2023,7 +2023,7 @@ package body common_pkg is
variable v_b : std_logic_vector(a'length - 1 downto 0);
begin
for I in v_a'range loop
- v_b(a'length - 1 -I) := v_a(I);
+ v_b(a'length - 1 - I) := v_a(I);
end loop;
return v_b;
end;
@@ -2038,7 +2038,7 @@ package body common_pkg is
variable v_b : t_slv_32_arr(a'length - 1 downto 0);
begin
for I in v_a'range loop
- v_b(a'length - 1 -I) := v_a(I);
+ v_b(a'length - 1 - I) := v_a(I);
end loop;
return v_b;
end;
@@ -2048,7 +2048,7 @@ package body common_pkg is
variable v_b : t_integer_arr(a'length - 1 downto 0);
begin
for I in v_a'range loop
- v_b(a'length - 1 -I) := v_a(I);
+ v_b(a'length - 1 - I) := v_a(I);
end loop;
return v_b;
end;
@@ -2058,7 +2058,7 @@ package body common_pkg is
variable v_b : t_natural_arr(a'length - 1 downto 0);
begin
for I in v_a'range loop
- v_b(a'length - 1 -I) := v_a(I);
+ v_b(a'length - 1 - I) := v_a(I);
end loop;
return v_b;
end;
@@ -2068,7 +2068,7 @@ package body common_pkg is
variable v_b : t_nat_natural_arr(a'length - 1 downto 0);
begin
for I in v_a'range loop
- v_b(a'length - 1 -I) := v_a(I);
+ v_b(a'length - 1 - I) := v_a(I);
end loop;
return v_b;
end;
@@ -2128,7 +2128,7 @@ package body common_pkg is
function slice_up(str : string; width : natural; i : natural; pad_char : character) return string is
variable padded_str : string(1 to width) := (others => '0');
begin
- padded_str := pad(str(i * width + 1 to (i +1) * width), width, '0');
+ padded_str := pad(str(i * width + 1 to (i + 1) * width), width, '0');
return padded_str;
end;
@@ -2225,7 +2225,7 @@ package body common_pkg is
-- Get the index K in the select setting array for the reorder2 cell on stage I and row J in a reorder network with N stages
function func_common_reorder2_get_select_index(I, J, N : natural) return integer is
- constant c_nof_reorder2_per_odd_stage : natural := N /2;
+ constant c_nof_reorder2_per_odd_stage : natural := N / 2;
constant c_nof_reorder2_per_even_stage : natural := (N - 1) / 2;
variable v_nof_odd_stages : natural;
variable v_nof_even_stages : natural;
@@ -2347,7 +2347,7 @@ package body common_pkg is
-- Create Pfactor SCLK periods within this DCLK period
SCLK <= '0';
if Pfactor > 1 then
- for I in 0 to 2 * Pfactor - 1 -2 loop
+ for I in 0 to 2 * Pfactor - 1 - 2 loop
wait for v_speriod / 2;
SCLK <= not SCLK;
end loop;
@@ -2359,4 +2359,4 @@ package body common_pkg is
wait;
end proc_common_dclk_generate_sclk;
-end common_pkg;
+end common_pkg;
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
index a9d8a6610cb8dd3dd9d765ffb11a28a45433ccfa..f75f3e2cc937b1b9b3cd70a802611cea70a10c27 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
@@ -265,7 +265,7 @@ package dp_stream_pkg is
function REPLICATE_DP_DATA( seq : std_logic_vector ) return std_logic_vector; -- replicate seq as often as fits in c_dp_stream_data_w
function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w : natural) return std_logic_vector; -- unreplicate data to width seq_w, return low seq_w bits and set mismatch MSbits bits to '1'
- function TO_DP_SOSI_unsigned(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : UNSIGNED) return t_dp_sosi_unsigned;
+ function TO_DP_SOSI_unsigned(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned;
-- Keep part of head data and combine part of tail data, use the other sosi from head_sosi
function func_dp_data_shift_first(head_sosi, tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail : natural) return t_dp_sosi;
@@ -590,7 +590,7 @@ package body dp_stream_pkg is
return v_vec(c_data_w - 1 downto 0);
end UNREPLICATE_DP_DATA;
- function TO_DP_SOSI_unsigned(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : UNSIGNED) return t_dp_sosi_unsigned is
+ function TO_DP_SOSI_unsigned(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned is
variable v_sosi_unsigned : t_dp_sosi_unsigned;
begin
v_sosi_unsigned.sync := sync;
@@ -737,8 +737,8 @@ package body dp_stream_pkg is
for I in dp'range loop
if mask(I) = '1' then
v_any := '1';
- if str ="READY " then v_vec(I) := dp(I).ready;
- elsif str ="XON " then v_vec(I) := dp(I).xon;
+ if str ="READY " then v_vec(I) := dp(I).ready;
+ elsif str ="XON " then v_vec(I) := dp(I).xon;
else report "Error in func_dp_stream_arr_and for t_dp_siso_arr";
end if;
end if;
@@ -759,10 +759,10 @@ package body dp_stream_pkg is
for I in dp'range loop
if mask(I) = '1' then
v_any := '1';
- if str ="VALID " then v_vec(I) := dp(I).valid;
- elsif str ="SOP " then v_vec(I) := dp(I).sop;
- elsif str ="EOP " then v_vec(I) := dp(I).eop;
- elsif str ="SYNC " then v_vec(I) := dp(I).sync;
+ if str ="VALID " then v_vec(I) := dp(I).valid;
+ elsif str ="SOP " then v_vec(I) := dp(I).sop;
+ elsif str ="EOP " then v_vec(I) := dp(I).eop;
+ elsif str ="SYNC " then v_vec(I) := dp(I).sync;
else report "Error in func_dp_stream_arr_and for t_dp_sosi_arr";
end if;
end if;
@@ -795,8 +795,8 @@ package body dp_stream_pkg is
for I in dp'range loop
if mask(I) = '1' then
v_any := '1';
- if str ="READY " then v_vec(I) := dp(I).ready;
- elsif str ="XON " then v_vec(I) := dp(I).xon;
+ if str ="READY " then v_vec(I) := dp(I).ready;
+ elsif str ="XON " then v_vec(I) := dp(I).xon;
else report "Error in func_dp_stream_arr_or for t_dp_siso_arr";
end if;
end if;
@@ -817,10 +817,10 @@ package body dp_stream_pkg is
for I in dp'range loop
if mask(I) = '1' then
v_any := '1';
- if str ="VALID " then v_vec(I) := dp(I).valid;
- elsif str ="SOP " then v_vec(I) := dp(I).sop;
- elsif str ="EOP " then v_vec(I) := dp(I).eop;
- elsif str ="SYNC " then v_vec(I) := dp(I).sync;
+ if str ="VALID " then v_vec(I) := dp(I).valid;
+ elsif str ="SOP " then v_vec(I) := dp(I).sop;
+ elsif str ="EOP " then v_vec(I) := dp(I).eop;
+ elsif str ="SYNC " then v_vec(I) := dp(I).sync;
else report "Error in func_dp_stream_arr_or for t_dp_sosi_arr";
end if;
end if;
@@ -852,8 +852,8 @@ package body dp_stream_pkg is
variable v_slv : std_logic_vector(dp'range) := slv; -- map to ensure same range as for dp
begin
for I in dp'range loop
- if str ="READY " then v_dp(I).ready := v_slv(I);
- elsif str ="XON " then v_dp(I).xon := v_slv(I);
+ if str ="READY " then v_dp(I).ready := v_slv(I);
+ elsif str ="XON " then v_dp(I).xon := v_slv(I);
else report "Error in func_dp_stream_arr_set for t_dp_siso_arr";
end if;
end loop;
@@ -865,10 +865,10 @@ package body dp_stream_pkg is
variable v_slv : std_logic_vector(dp'range) := slv; -- map to ensure same range as for dp
begin
for I in dp'range loop
- if str ="VALID " then v_dp(I).valid := v_slv(I);
- elsif str ="SOP " then v_dp(I).sop := v_slv(I);
- elsif str ="EOP " then v_dp(I).eop := v_slv(I);
- elsif str ="SYNC " then v_dp(I).sync := v_slv(I);
+ if str ="VALID " then v_dp(I).valid := v_slv(I);
+ elsif str ="SOP " then v_dp(I).sop := v_slv(I);
+ elsif str ="EOP " then v_dp(I).eop := v_slv(I);
+ elsif str ="SYNC " then v_dp(I).sync := v_slv(I);
else report "Error in func_dp_stream_arr_set for t_dp_sosi_arr";
end if;
end loop;
@@ -891,8 +891,8 @@ package body dp_stream_pkg is
variable v_ctrl : std_logic_vector(dp'range);
begin
for I in dp'range loop
- if str ="READY " then v_ctrl(I) := dp(I).ready;
- elsif str ="XON " then v_ctrl(I) := dp(I).xon;
+ if str ="READY " then v_ctrl(I) := dp(I).ready;
+ elsif str ="XON " then v_ctrl(I) := dp(I).xon;
else report "Error in func_dp_stream_arr_get for t_dp_siso_arr";
end if;
end loop;
@@ -903,10 +903,10 @@ package body dp_stream_pkg is
variable v_ctrl : std_logic_vector(dp'range);
begin
for I in dp'range loop
- if str ="VALID " then v_ctrl(I) := dp(I).valid;
- elsif str ="SOP " then v_ctrl(I) := dp(I).sop;
- elsif str ="EOP " then v_ctrl(I) := dp(I).eop;
- elsif str ="SYNC " then v_ctrl(I) := dp(I).sync;
+ if str ="VALID " then v_ctrl(I) := dp(I).valid;
+ elsif str ="SOP " then v_ctrl(I) := dp(I).sop;
+ elsif str ="EOP " then v_ctrl(I) := dp(I).eop;
+ elsif str ="SYNC " then v_ctrl(I) := dp(I).sync;
else report "Error in func_dp_stream_arr_get for t_dp_sosi_arr";
end if;
end loop;
@@ -1245,12 +1245,12 @@ package body dp_stream_pkg is
function func_dp_stream_set_data(dp : t_dp_sosi; slv : std_logic_vector; str : string) return t_dp_sosi is
variable v_dp : t_dp_sosi := dp;
begin
- if str ="DATA " then v_dp.data := RESIZE_DP_DATA(slv);
- elsif str ="DSP " then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ if str ="DATA " then v_dp.data := RESIZE_DP_DATA(slv);
+ elsif str ="DSP " then v_dp.re := RESIZE_DP_DSP_DATA(slv);
v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str ="RE " then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- elsif str ="IM " then v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str ="all " then v_dp.data := RESIZE_DP_DATA(slv);
+ elsif str ="RE " then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ elsif str ="IM " then v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str ="all " then v_dp.data := RESIZE_DP_DATA(slv);
v_dp.re := RESIZE_DP_DSP_DATA(slv);
v_dp.im := RESIZE_DP_DSP_DATA(slv);
else report "Error in func_dp_stream_set_data for t_dp_sosi";
@@ -1420,10 +1420,10 @@ package body dp_stream_pkg is
v_src_out.im := (others => '0');
for i in 0 to nof_data - 1 loop
v_in_data := snk_in.data((i + 1) * in_w - 1 downto i * in_w);
- if data_representation ="unsigned " then -- treat data as unsigned
+ if data_representation ="unsigned " then -- treat data as unsigned
v_out_data := RESIZE_UVEC(v_in_data, out_w);
else
- if data_representation ="signed " then -- treat data as signed
+ if data_representation ="signed " then -- treat data as signed
v_out_data := RESIZE_SVEC(v_in_data, out_w);
else
-- treat data as complex
@@ -1486,4 +1486,4 @@ package body dp_stream_pkg is
return src_out_arr(0);
end;
-end dp_stream_pkg;
+end dp_stream_pkg;
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
index 3ca37696f6210b475ad03f17fa917465a1738f28..74e8f2b1e63dd3b34662c44f06b72139cb8dedda 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
@@ -106,7 +106,7 @@ package eth_pkg is
-- . write/read back registers
type t_eth_demux_ports_arr is array(1 to c_eth_nof_udp_ports) of std_logic_vector(c_network_udp_port_w - 1 downto 0);
type t_eth_mm_reg_demux is record
- udp_ports_en : std_logic_vector(1 TO c_eth_nof_udp_ports); -- [16]
+ udp_ports_en : std_logic_vector(1 to c_eth_nof_udp_ports); -- [16]
udp_ports : t_eth_demux_ports_arr; -- [15:0]
end record;
@@ -349,4 +349,4 @@ package body eth_pkg is
return v_reg;
end func_eth_mm_reg_status;
-end eth_pkg;
+end eth_pkg;
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
index c25f4d4776a354b90c243f9e0f6d4c0ffc4a4ecc..705524fb12c47fa822c568e717d3f18963d7cc87 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
@@ -81,4 +81,4 @@
coe_tse_waitrequest_export => CONNECTED_TO_coe_tse_waitrequest_export, -- tse_waitrequest.export
coe_tse_write_export => CONNECTED_TO_coe_tse_write_export, -- tse_write.export
coe_tse_writedata_export => CONNECTED_TO_coe_tse_writedata_export -- tse_writedata.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
index c7ca333408b002445817fc66d2b8c8111d6197ac..7bc86549a50407b84e052a86a6e6a143d0ab946f 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
@@ -13,4 +13,4 @@
in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
index 3e5eaafd868c45ef34e30a8dad9dab73449317f8..26d93a9ea30cb8643ffe32207b93aa21193fe2c6 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
@@ -57,4 +57,4 @@
irq => CONNECTED_TO_irq, -- irq.irq
reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
reset_req => CONNECTED_TO_reset_req -- .reset_req
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
index c08fcff0abdd4a786a80116dc6269e2e413475cd..c2abb9e91f687cabdedff86d2d692f8b221aaf5e 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
@@ -97,4 +97,4 @@
sof => CONNECTED_TO_sof, -- sof.export
somf => CONNECTED_TO_somf, -- somf.export
sysref => CONNECTED_TO_sysref -- sysref.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd
index c649161846cb038720bcdf711777fee68d05431a..b4173dc058e0d5b5c5820fb8d12153d10d5088f8 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd
@@ -757,4 +757,4 @@ begin
--
--synthesis read_comments_as_HDL off
-end europa;
+end europa;
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
index da3c2aa0181c85bc9c7bbd373f3847f1810ec1fb..c9c479a863d07b04ec60cddb00941ed037d3a402 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
@@ -25,4 +25,4 @@
clk => CONNECTED_TO_clk, -- clk.clk
av_irq => CONNECTED_TO_av_irq, -- irq.irq
rst_n => CONNECTED_TO_rst_n -- reset.reset_n
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd
index 19adb8c437d4a0283fe6ce73ec1be5dddf1b5755..1949dd0fa4f5a139ce4b9ee8083935c1af23c191 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd
@@ -115,4 +115,4 @@ begin
--vhdl renameroo for output signals
readdata <= internal_readdata;
-end europa;
+end europa;
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
index 6ad2b21a321d7fc6b052fa99f2cab846205280df..ecb126859925864d13a9e71a87f62344b2e25c9e 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
@@ -25,4 +25,4 @@
readdata => CONNECTED_TO_readdata, -- .readdata
writedata => CONNECTED_TO_writedata, -- .writedata
byteenable => CONNECTED_TO_byteenable -- .byteenable
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
index 9e07f4b8fe33ddb566b916d8d6623ec3c750fbb5..ec3101547f6408d720595d0f927b5d5c2e1506a2 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
@@ -41,4 +41,4 @@
csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
index d3e5d94238fb3b6ff7f39aa1682fc056ebb73652..0794de5258c9dc63924fbd02c4855973fd51fd9b 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
@@ -41,4 +41,4 @@
csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd
index 12348df1d3a2f455eab871bd6b7378cf2318f261..07d15bd0f771ebdf4e6046c8bf62294a88660f94 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd
@@ -68,4 +68,4 @@ begin
readdata <= std_logic_vector'("00000000000000000000000000000000") or (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(read_mux_out)));
out_port <= data_out;
-end europa;
+end europa;
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
index 159b52690b55259dad655e9c976788e9ea5146ae..c63d9306e76cbfd60b817a46df2032905119a9aa 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
@@ -21,4 +21,4 @@
writedata => CONNECTED_TO_writedata, -- .writedata
chipselect => CONNECTED_TO_chipselect, -- .chipselect
readdata => CONNECTED_TO_readdata -- .readdata
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
index dfa2f39fe1bb4e5ca3903d7bd2d38c1daa7bc5d0..ca70a8648ec81b1f25d6bbbd55930b5d52c902eb 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
@@ -41,4 +41,4 @@
csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
index 789342aa93d4009f761e9f3149c36eeadf3530bb..24610ced4a0afa79fa2df090df98e3c4bb58601c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
@@ -41,4 +41,4 @@
csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
index 7cdf6ac161a5c25da865a44f08b28175ddd0af2f..81ba1431b7f36c3246f8c4b4839df0bdd9a27957 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
@@ -41,4 +41,4 @@
csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
index 952f9fa07a3eb2deea90c13efc65be3b8b646736..a12984f10bbf0d09735d96acde9a27c5f344468e 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
@@ -41,4 +41,4 @@
csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
index 4e82d31b6b9d6407a435657a5050f8dbce4a94bb..d283f75c59a8e56f82266b5ea5df067be4cde6ca 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
@@ -41,4 +41,4 @@
csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
index fc8e7129557ae72f7dd50329c37ed574d2236c07..3eb5fb91db727323ade6d08518e4f05267aaccbd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
@@ -41,4 +41,4 @@
csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
index 8f1fa9306f2393a7b82b34840f29cd4f9d336011..a15759ed5cacd25f1d02bb0ae2257ba9fcdf613e 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
@@ -41,4 +41,4 @@
csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
index 6c55e1250f8422fd4313cb1e13891701c3e2819d..e349d2f690494b83716368382044e44c530ff8af 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
@@ -41,4 +41,4 @@
csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
index e1eab332082486cfbe90545463d9bc7f6ddcea50..0a6189d1f8d02a09efcfd8e27230257bd6525225 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
@@ -41,4 +41,4 @@
csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
index ad6aca5eccffbc5900c7ea8afb18f52475af39a3..060d8f43d74d87e100fcd9d8bfb2b25ce5f94ce6 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
@@ -41,4 +41,4 @@
csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
index d021b96883fb1192c3ecf575486624514609de21..7aa35c95742f359513d404dfd07e048e39fdc85e 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
@@ -41,4 +41,4 @@
csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
index 84e748f11e8ffbd6f2e0895e78d6268f68b0075c..3156e1f7115453925a47d0e3ce6ebfef982b9cf4 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
@@ -41,4 +41,4 @@
csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd
index e965bdbf560982e2f8b296e01918df0e61e357ee..fa95d5ce0a4c2f5bac3b1737908132b8b970becf 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd
@@ -146,7 +146,7 @@ begin
irq <= timeout_occurred and control_interrupt_enable;
--s1, which is an e_avalon_slave
- read_mux_out <= ((A_REP(to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000001")))), 16) and (std_logic_vector'("000000000000000") & (A_TOSTDLOGICVECTor(control_register))))) OR ((A_REP(to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000000")))), 16) and (std_logic_vector'("00000000000000") & (std_logic_vector'(A_ToStdLogicVector(counter_is_running) & A_ToStdLogicVector(timeout_occurred))))));
+ read_mux_out <= ((A_REP(to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000001")))), 16) and (std_logic_vector'("000000000000000") & (A_TOSTDLOGICVECTor(control_register))))) or ((A_REP(to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000000")))), 16) and (std_logic_vector'("00000000000000") & (std_logic_vector'(A_ToStdLogicVector(counter_is_running) & A_ToStdLogicVector(timeout_occurred))))));
process (clk, reset_n)
begin
if reset_n = '0' then
@@ -177,4 +177,4 @@ begin
control_interrupt_enable <= control_register;
status_wr_strobe <= (chipselect and not write_n) and to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000000"))));
-end europa;
+end europa;
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
index 89bce420fd86c0facac177eff6b93b90a9a9e9cf..5dc19007e00295cd33b03bc364f621968353ef93 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
@@ -21,4 +21,4 @@
readdata => CONNECTED_TO_readdata, -- .readdata
chipselect => CONNECTED_TO_chipselect, -- .chipselect
write_n => CONNECTED_TO_write_n -- .write_n
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/unb2b_jesd_node0.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/unb2b_jesd_node0.vhd
index e3344b13ba36ed085acb5597707d9717572db1e9..f9e990ff59226530f1369484ab10f5269479ba5e 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/unb2b_jesd_node0.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/unb2b_jesd_node0.vhd
@@ -66,8 +66,8 @@ entity unb2b_jesd_node0 is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
@@ -131,4 +131,4 @@ begin
jesd204_device_clk => jesd204_device_clk
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
index b7b0b9421b284e8fdc22266e004bd1d10a7bb772..cd51286875c6c394041a42ddf10b6ab7a6c4ac10 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
@@ -15,4 +15,4 @@
outclk_1 => CONNECTED_TO_outclk_1, -- outclk1.clk
refclk => CONNECTED_TO_refclk, -- refclk.clk
rst => CONNECTED_TO_rst -- reset.reset
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
index 0464262396a9a713f4d39a1f4723b9edd3dd61fa..0a668a0c8a248b41b37084b169ceddc5e159c81d 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
@@ -11,4 +11,4 @@
clk => CONNECTED_TO_clk, -- clk.clk
in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
index 425df4f7db5953159a1866aca009b90f0a5b1f4a..fe390e7550d75be13a64ce3da19fe5ae7ea1463f 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
@@ -11,4 +11,4 @@
clk => CONNECTED_TO_clk, -- clk.clk
in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
index 213f6db90380d5cc7aaa7404b91ca84c84dc4f93..8e147e66f0354b598da92c26f43986f20504ec1a 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
@@ -159,4 +159,4 @@
reset_out5 => CONNECTED_TO_reset_out5, -- reset_out5.reset
reset_out6 => CONNECTED_TO_reset_out6, -- reset_out6.reset
reset_out7 => CONNECTED_TO_reset_out7 -- reset_out7.reset
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
index 4aa7f3aec3376b44a6c322e7ce6998d1be984757..4a4dd5d437232c07be643a76dc8107a953d65a4d 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
@@ -21,4 +21,4 @@
rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
rx_is_lockedtodata => CONNECTED_TO_rx_is_lockedtodata, -- rx_is_lockedtodata.rx_is_lockedtodata
rx_ready => CONNECTED_TO_rx_ready -- rx_ready.rx_ready
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
index b3899a24db71a83417108dbf99209a00c51af798..a5796f3aaa2accf706b6b116457f9898db29a702 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
@@ -13,4 +13,4 @@
in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
index 5df9fb0a9a23d44ed9dc84a08ad17fd635aa24ac..c135dff113ded97e10aff71bc85dabdfe00ed05f 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
@@ -13,4 +13,4 @@
in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
index 2f3daf68560be0b5aa56449818ecd126d5e80d0a..6b5b96f4f27103f72ee7e9d78f14af237651d704 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
@@ -97,4 +97,4 @@
sof => CONNECTED_TO_sof, -- sof.export
somf => CONNECTED_TO_somf, -- somf.export
sysref => CONNECTED_TO_sysref -- sysref.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
index 4d98d388128a9021807c47c80bdbb7985f3724c3..4c240b329fc1417edb8549e12f7a9e58dfb0a4b5 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
@@ -13,4 +13,4 @@
in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
index e9f2adf7d608e83045c0f39d64da8155b088f674..327b8730c779a44291ceba2819a55c1737aef04f 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
@@ -41,4 +41,4 @@
csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
index a6ccb8cfd25f0f0e88194637e9d418cedcffdafc..3ee82d53fc94895496d4cd2d5221dfcfaa359acf 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
@@ -41,4 +41,4 @@
csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
index c4db7d7c3f2edeee7bc4d5a3b2a992fd702d7939..a7a03b2b98e7d79044486d0643589e5b2c0ab2d2 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
@@ -673,18 +673,18 @@ package body common_pkg is
variable v_result : std_logic := '0';
begin
-- default any unused, the stage results will be kept in the LSBits and the last result in bit 0
- if operation ="and " then v_stage_arr := (others => (others => '1'));
- elsif operation ="or " then v_stage_arr := (others => (others => '0'));
- elsif operation ="xor " then v_stage_arr := (others => (others => '0'));
+ if operation ="and " then v_stage_arr := (others => (others => '1'));
+ elsif operation ="or " then v_stage_arr := (others => (others => '0'));
+ elsif operation ="xor " then v_stage_arr := (others => (others => '0'));
else
assert TRUE report "common_pkg: Unsupported vector_tree operation" severity FAILURE;
end if;
v_stage_arr(-1)(c_slv_w - 1 downto 0) := slv; -- any unused input c_w : c_slv_w bits have void default value
for J in 0 to c_nof_stages - 1 loop
for I in 0 to c_w / (2 ** (J + 1)) - 1 loop
- if operation ="and " then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) and v_stage_arr(J - 1)(2 * I + 1);
- elsif operation ="or " then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) or v_stage_arr(J - 1)(2 * I + 1);
- elsif operation ="xor " then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) xor v_stage_arr(J - 1)(2 * I + 1);
+ if operation ="and " then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) and v_stage_arr(J - 1)(2 * I + 1);
+ elsif operation ="or " then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) or v_stage_arr(J - 1)(2 * I + 1);
+ elsif operation ="xor " then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) xor v_stage_arr(J - 1)(2 * I + 1);
end if;
end loop;
end loop;
@@ -853,7 +853,7 @@ package body common_pkg is
variable vR : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
vR := R;
for I in vL'range loop
vP(I) := vL(I) + vR(I);
@@ -866,7 +866,7 @@ package body common_pkg is
variable vL : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
for I in vL'range loop
vP(I) := vL(I) + R;
end loop;
@@ -884,7 +884,7 @@ package body common_pkg is
variable vR : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
vR := R;
for I in vL'range loop
vP(I) := vL(I) - vR(I);
@@ -898,7 +898,7 @@ package body common_pkg is
variable vR : t_natural_arr(w - 1 downto 0);
variable vP : t_integer_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
vR := R;
for I in vL'range loop
vP(I) := vL(I) - vR(I);
@@ -911,7 +911,7 @@ package body common_pkg is
variable vL : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
for I in vL'range loop
vP(I) := vL(I) - R;
end loop;
@@ -936,7 +936,7 @@ package body common_pkg is
variable vR : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
vR := R;
for I in vL'range loop
vP(I) := vL(I) * vR(I);
@@ -949,7 +949,7 @@ package body common_pkg is
variable vL : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
for I in vL'range loop
vP(I) := vL(I) * R;
end loop;
@@ -967,7 +967,7 @@ package body common_pkg is
variable vR : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
vR := R;
for I in vL'range loop
vP(I) := vL(I) / vR(I);
@@ -980,7 +980,7 @@ package body common_pkg is
variable vL : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
for I in vL'range loop
vP(I) := vL(I) / R;
end loop;
@@ -1278,7 +1278,7 @@ package body common_pkg is
function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string is begin if sel < 9 then return sel_n(sel, a, b, c, d, e, f, g, h, i); else return j; end if; end;
function array_init(init : std_logic; nof : natural) return std_logic_vector is
- variable v_arr : std_logic_vector(0 TO nof - 1);
+ variable v_arr : std_logic_vector(0 to nof - 1);
begin
for I in v_arr'range loop
v_arr(I) := init;
@@ -2023,7 +2023,7 @@ package body common_pkg is
variable v_b : std_logic_vector(a'length - 1 downto 0);
begin
for I in v_a'range loop
- v_b(a'length - 1 -I) := v_a(I);
+ v_b(a'length - 1 - I) := v_a(I);
end loop;
return v_b;
end;
@@ -2038,7 +2038,7 @@ package body common_pkg is
variable v_b : t_slv_32_arr(a'length - 1 downto 0);
begin
for I in v_a'range loop
- v_b(a'length - 1 -I) := v_a(I);
+ v_b(a'length - 1 - I) := v_a(I);
end loop;
return v_b;
end;
@@ -2048,7 +2048,7 @@ package body common_pkg is
variable v_b : t_integer_arr(a'length - 1 downto 0);
begin
for I in v_a'range loop
- v_b(a'length - 1 -I) := v_a(I);
+ v_b(a'length - 1 - I) := v_a(I);
end loop;
return v_b;
end;
@@ -2058,7 +2058,7 @@ package body common_pkg is
variable v_b : t_natural_arr(a'length - 1 downto 0);
begin
for I in v_a'range loop
- v_b(a'length - 1 -I) := v_a(I);
+ v_b(a'length - 1 - I) := v_a(I);
end loop;
return v_b;
end;
@@ -2068,7 +2068,7 @@ package body common_pkg is
variable v_b : t_nat_natural_arr(a'length - 1 downto 0);
begin
for I in v_a'range loop
- v_b(a'length - 1 -I) := v_a(I);
+ v_b(a'length - 1 - I) := v_a(I);
end loop;
return v_b;
end;
@@ -2128,7 +2128,7 @@ package body common_pkg is
function slice_up(str : string; width : natural; i : natural; pad_char : character) return string is
variable padded_str : string(1 to width) := (others => '0');
begin
- padded_str := pad(str(i * width + 1 to (i +1) * width), width, '0');
+ padded_str := pad(str(i * width + 1 to (i + 1) * width), width, '0');
return padded_str;
end;
@@ -2225,7 +2225,7 @@ package body common_pkg is
-- Get the index K in the select setting array for the reorder2 cell on stage I and row J in a reorder network with N stages
function func_common_reorder2_get_select_index(I, J, N : natural) return integer is
- constant c_nof_reorder2_per_odd_stage : natural := N /2;
+ constant c_nof_reorder2_per_odd_stage : natural := N / 2;
constant c_nof_reorder2_per_even_stage : natural := (N - 1) / 2;
variable v_nof_odd_stages : natural;
variable v_nof_even_stages : natural;
@@ -2347,7 +2347,7 @@ package body common_pkg is
-- Create Pfactor SCLK periods within this DCLK period
SCLK <= '0';
if Pfactor > 1 then
- for I in 0 to 2 * Pfactor - 1 -2 loop
+ for I in 0 to 2 * Pfactor - 1 - 2 loop
wait for v_speriod / 2;
SCLK <= not SCLK;
end loop;
@@ -2359,4 +2359,4 @@ package body common_pkg is
wait;
end proc_common_dclk_generate_sclk;
-end common_pkg;
+end common_pkg;
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
index a9d8a6610cb8dd3dd9d765ffb11a28a45433ccfa..f75f3e2cc937b1b9b3cd70a802611cea70a10c27 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
@@ -265,7 +265,7 @@ package dp_stream_pkg is
function REPLICATE_DP_DATA( seq : std_logic_vector ) return std_logic_vector; -- replicate seq as often as fits in c_dp_stream_data_w
function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w : natural) return std_logic_vector; -- unreplicate data to width seq_w, return low seq_w bits and set mismatch MSbits bits to '1'
- function TO_DP_SOSI_unsigned(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : UNSIGNED) return t_dp_sosi_unsigned;
+ function TO_DP_SOSI_unsigned(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned;
-- Keep part of head data and combine part of tail data, use the other sosi from head_sosi
function func_dp_data_shift_first(head_sosi, tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail : natural) return t_dp_sosi;
@@ -590,7 +590,7 @@ package body dp_stream_pkg is
return v_vec(c_data_w - 1 downto 0);
end UNREPLICATE_DP_DATA;
- function TO_DP_SOSI_unsigned(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : UNSIGNED) return t_dp_sosi_unsigned is
+ function TO_DP_SOSI_unsigned(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned is
variable v_sosi_unsigned : t_dp_sosi_unsigned;
begin
v_sosi_unsigned.sync := sync;
@@ -737,8 +737,8 @@ package body dp_stream_pkg is
for I in dp'range loop
if mask(I) = '1' then
v_any := '1';
- if str ="READY " then v_vec(I) := dp(I).ready;
- elsif str ="XON " then v_vec(I) := dp(I).xon;
+ if str ="READY " then v_vec(I) := dp(I).ready;
+ elsif str ="XON " then v_vec(I) := dp(I).xon;
else report "Error in func_dp_stream_arr_and for t_dp_siso_arr";
end if;
end if;
@@ -759,10 +759,10 @@ package body dp_stream_pkg is
for I in dp'range loop
if mask(I) = '1' then
v_any := '1';
- if str ="VALID " then v_vec(I) := dp(I).valid;
- elsif str ="SOP " then v_vec(I) := dp(I).sop;
- elsif str ="EOP " then v_vec(I) := dp(I).eop;
- elsif str ="SYNC " then v_vec(I) := dp(I).sync;
+ if str ="VALID " then v_vec(I) := dp(I).valid;
+ elsif str ="SOP " then v_vec(I) := dp(I).sop;
+ elsif str ="EOP " then v_vec(I) := dp(I).eop;
+ elsif str ="SYNC " then v_vec(I) := dp(I).sync;
else report "Error in func_dp_stream_arr_and for t_dp_sosi_arr";
end if;
end if;
@@ -795,8 +795,8 @@ package body dp_stream_pkg is
for I in dp'range loop
if mask(I) = '1' then
v_any := '1';
- if str ="READY " then v_vec(I) := dp(I).ready;
- elsif str ="XON " then v_vec(I) := dp(I).xon;
+ if str ="READY " then v_vec(I) := dp(I).ready;
+ elsif str ="XON " then v_vec(I) := dp(I).xon;
else report "Error in func_dp_stream_arr_or for t_dp_siso_arr";
end if;
end if;
@@ -817,10 +817,10 @@ package body dp_stream_pkg is
for I in dp'range loop
if mask(I) = '1' then
v_any := '1';
- if str ="VALID " then v_vec(I) := dp(I).valid;
- elsif str ="SOP " then v_vec(I) := dp(I).sop;
- elsif str ="EOP " then v_vec(I) := dp(I).eop;
- elsif str ="SYNC " then v_vec(I) := dp(I).sync;
+ if str ="VALID " then v_vec(I) := dp(I).valid;
+ elsif str ="SOP " then v_vec(I) := dp(I).sop;
+ elsif str ="EOP " then v_vec(I) := dp(I).eop;
+ elsif str ="SYNC " then v_vec(I) := dp(I).sync;
else report "Error in func_dp_stream_arr_or for t_dp_sosi_arr";
end if;
end if;
@@ -852,8 +852,8 @@ package body dp_stream_pkg is
variable v_slv : std_logic_vector(dp'range) := slv; -- map to ensure same range as for dp
begin
for I in dp'range loop
- if str ="READY " then v_dp(I).ready := v_slv(I);
- elsif str ="XON " then v_dp(I).xon := v_slv(I);
+ if str ="READY " then v_dp(I).ready := v_slv(I);
+ elsif str ="XON " then v_dp(I).xon := v_slv(I);
else report "Error in func_dp_stream_arr_set for t_dp_siso_arr";
end if;
end loop;
@@ -865,10 +865,10 @@ package body dp_stream_pkg is
variable v_slv : std_logic_vector(dp'range) := slv; -- map to ensure same range as for dp
begin
for I in dp'range loop
- if str ="VALID " then v_dp(I).valid := v_slv(I);
- elsif str ="SOP " then v_dp(I).sop := v_slv(I);
- elsif str ="EOP " then v_dp(I).eop := v_slv(I);
- elsif str ="SYNC " then v_dp(I).sync := v_slv(I);
+ if str ="VALID " then v_dp(I).valid := v_slv(I);
+ elsif str ="SOP " then v_dp(I).sop := v_slv(I);
+ elsif str ="EOP " then v_dp(I).eop := v_slv(I);
+ elsif str ="SYNC " then v_dp(I).sync := v_slv(I);
else report "Error in func_dp_stream_arr_set for t_dp_sosi_arr";
end if;
end loop;
@@ -891,8 +891,8 @@ package body dp_stream_pkg is
variable v_ctrl : std_logic_vector(dp'range);
begin
for I in dp'range loop
- if str ="READY " then v_ctrl(I) := dp(I).ready;
- elsif str ="XON " then v_ctrl(I) := dp(I).xon;
+ if str ="READY " then v_ctrl(I) := dp(I).ready;
+ elsif str ="XON " then v_ctrl(I) := dp(I).xon;
else report "Error in func_dp_stream_arr_get for t_dp_siso_arr";
end if;
end loop;
@@ -903,10 +903,10 @@ package body dp_stream_pkg is
variable v_ctrl : std_logic_vector(dp'range);
begin
for I in dp'range loop
- if str ="VALID " then v_ctrl(I) := dp(I).valid;
- elsif str ="SOP " then v_ctrl(I) := dp(I).sop;
- elsif str ="EOP " then v_ctrl(I) := dp(I).eop;
- elsif str ="SYNC " then v_ctrl(I) := dp(I).sync;
+ if str ="VALID " then v_ctrl(I) := dp(I).valid;
+ elsif str ="SOP " then v_ctrl(I) := dp(I).sop;
+ elsif str ="EOP " then v_ctrl(I) := dp(I).eop;
+ elsif str ="SYNC " then v_ctrl(I) := dp(I).sync;
else report "Error in func_dp_stream_arr_get for t_dp_sosi_arr";
end if;
end loop;
@@ -1245,12 +1245,12 @@ package body dp_stream_pkg is
function func_dp_stream_set_data(dp : t_dp_sosi; slv : std_logic_vector; str : string) return t_dp_sosi is
variable v_dp : t_dp_sosi := dp;
begin
- if str ="DATA " then v_dp.data := RESIZE_DP_DATA(slv);
- elsif str ="DSP " then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ if str ="DATA " then v_dp.data := RESIZE_DP_DATA(slv);
+ elsif str ="DSP " then v_dp.re := RESIZE_DP_DSP_DATA(slv);
v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str ="RE " then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- elsif str ="IM " then v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str ="all " then v_dp.data := RESIZE_DP_DATA(slv);
+ elsif str ="RE " then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ elsif str ="IM " then v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str ="all " then v_dp.data := RESIZE_DP_DATA(slv);
v_dp.re := RESIZE_DP_DSP_DATA(slv);
v_dp.im := RESIZE_DP_DSP_DATA(slv);
else report "Error in func_dp_stream_set_data for t_dp_sosi";
@@ -1420,10 +1420,10 @@ package body dp_stream_pkg is
v_src_out.im := (others => '0');
for i in 0 to nof_data - 1 loop
v_in_data := snk_in.data((i + 1) * in_w - 1 downto i * in_w);
- if data_representation ="unsigned " then -- treat data as unsigned
+ if data_representation ="unsigned " then -- treat data as unsigned
v_out_data := RESIZE_UVEC(v_in_data, out_w);
else
- if data_representation ="signed " then -- treat data as signed
+ if data_representation ="signed " then -- treat data as signed
v_out_data := RESIZE_SVEC(v_in_data, out_w);
else
-- treat data as complex
@@ -1486,4 +1486,4 @@ package body dp_stream_pkg is
return src_out_arr(0);
end;
-end dp_stream_pkg;
+end dp_stream_pkg;
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
index 3ca37696f6210b475ad03f17fa917465a1738f28..74e8f2b1e63dd3b34662c44f06b72139cb8dedda 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
@@ -106,7 +106,7 @@ package eth_pkg is
-- . write/read back registers
type t_eth_demux_ports_arr is array(1 to c_eth_nof_udp_ports) of std_logic_vector(c_network_udp_port_w - 1 downto 0);
type t_eth_mm_reg_demux is record
- udp_ports_en : std_logic_vector(1 TO c_eth_nof_udp_ports); -- [16]
+ udp_ports_en : std_logic_vector(1 to c_eth_nof_udp_ports); -- [16]
udp_ports : t_eth_demux_ports_arr; -- [15:0]
end record;
@@ -349,4 +349,4 @@ package body eth_pkg is
return v_reg;
end func_eth_mm_reg_status;
-end eth_pkg;
+end eth_pkg;
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
index c4db7d7c3f2edeee7bc4d5a3b2a992fd702d7939..a7a03b2b98e7d79044486d0643589e5b2c0ab2d2 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
@@ -673,18 +673,18 @@ package body common_pkg is
variable v_result : std_logic := '0';
begin
-- default any unused, the stage results will be kept in the LSBits and the last result in bit 0
- if operation ="and " then v_stage_arr := (others => (others => '1'));
- elsif operation ="or " then v_stage_arr := (others => (others => '0'));
- elsif operation ="xor " then v_stage_arr := (others => (others => '0'));
+ if operation ="and " then v_stage_arr := (others => (others => '1'));
+ elsif operation ="or " then v_stage_arr := (others => (others => '0'));
+ elsif operation ="xor " then v_stage_arr := (others => (others => '0'));
else
assert TRUE report "common_pkg: Unsupported vector_tree operation" severity FAILURE;
end if;
v_stage_arr(-1)(c_slv_w - 1 downto 0) := slv; -- any unused input c_w : c_slv_w bits have void default value
for J in 0 to c_nof_stages - 1 loop
for I in 0 to c_w / (2 ** (J + 1)) - 1 loop
- if operation ="and " then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) and v_stage_arr(J - 1)(2 * I + 1);
- elsif operation ="or " then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) or v_stage_arr(J - 1)(2 * I + 1);
- elsif operation ="xor " then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) xor v_stage_arr(J - 1)(2 * I + 1);
+ if operation ="and " then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) and v_stage_arr(J - 1)(2 * I + 1);
+ elsif operation ="or " then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) or v_stage_arr(J - 1)(2 * I + 1);
+ elsif operation ="xor " then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) xor v_stage_arr(J - 1)(2 * I + 1);
end if;
end loop;
end loop;
@@ -853,7 +853,7 @@ package body common_pkg is
variable vR : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
vR := R;
for I in vL'range loop
vP(I) := vL(I) + vR(I);
@@ -866,7 +866,7 @@ package body common_pkg is
variable vL : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
for I in vL'range loop
vP(I) := vL(I) + R;
end loop;
@@ -884,7 +884,7 @@ package body common_pkg is
variable vR : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
vR := R;
for I in vL'range loop
vP(I) := vL(I) - vR(I);
@@ -898,7 +898,7 @@ package body common_pkg is
variable vR : t_natural_arr(w - 1 downto 0);
variable vP : t_integer_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
vR := R;
for I in vL'range loop
vP(I) := vL(I) - vR(I);
@@ -911,7 +911,7 @@ package body common_pkg is
variable vL : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
for I in vL'range loop
vP(I) := vL(I) - R;
end loop;
@@ -936,7 +936,7 @@ package body common_pkg is
variable vR : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
vR := R;
for I in vL'range loop
vP(I) := vL(I) * vR(I);
@@ -949,7 +949,7 @@ package body common_pkg is
variable vL : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
for I in vL'range loop
vP(I) := vL(I) * R;
end loop;
@@ -967,7 +967,7 @@ package body common_pkg is
variable vR : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
vR := R;
for I in vL'range loop
vP(I) := vL(I) / vR(I);
@@ -980,7 +980,7 @@ package body common_pkg is
variable vL : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
for I in vL'range loop
vP(I) := vL(I) / R;
end loop;
@@ -1278,7 +1278,7 @@ package body common_pkg is
function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string is begin if sel < 9 then return sel_n(sel, a, b, c, d, e, f, g, h, i); else return j; end if; end;
function array_init(init : std_logic; nof : natural) return std_logic_vector is
- variable v_arr : std_logic_vector(0 TO nof - 1);
+ variable v_arr : std_logic_vector(0 to nof - 1);
begin
for I in v_arr'range loop
v_arr(I) := init;
@@ -2023,7 +2023,7 @@ package body common_pkg is
variable v_b : std_logic_vector(a'length - 1 downto 0);
begin
for I in v_a'range loop
- v_b(a'length - 1 -I) := v_a(I);
+ v_b(a'length - 1 - I) := v_a(I);
end loop;
return v_b;
end;
@@ -2038,7 +2038,7 @@ package body common_pkg is
variable v_b : t_slv_32_arr(a'length - 1 downto 0);
begin
for I in v_a'range loop
- v_b(a'length - 1 -I) := v_a(I);
+ v_b(a'length - 1 - I) := v_a(I);
end loop;
return v_b;
end;
@@ -2048,7 +2048,7 @@ package body common_pkg is
variable v_b : t_integer_arr(a'length - 1 downto 0);
begin
for I in v_a'range loop
- v_b(a'length - 1 -I) := v_a(I);
+ v_b(a'length - 1 - I) := v_a(I);
end loop;
return v_b;
end;
@@ -2058,7 +2058,7 @@ package body common_pkg is
variable v_b : t_natural_arr(a'length - 1 downto 0);
begin
for I in v_a'range loop
- v_b(a'length - 1 -I) := v_a(I);
+ v_b(a'length - 1 - I) := v_a(I);
end loop;
return v_b;
end;
@@ -2068,7 +2068,7 @@ package body common_pkg is
variable v_b : t_nat_natural_arr(a'length - 1 downto 0);
begin
for I in v_a'range loop
- v_b(a'length - 1 -I) := v_a(I);
+ v_b(a'length - 1 - I) := v_a(I);
end loop;
return v_b;
end;
@@ -2128,7 +2128,7 @@ package body common_pkg is
function slice_up(str : string; width : natural; i : natural; pad_char : character) return string is
variable padded_str : string(1 to width) := (others => '0');
begin
- padded_str := pad(str(i * width + 1 to (i +1) * width), width, '0');
+ padded_str := pad(str(i * width + 1 to (i + 1) * width), width, '0');
return padded_str;
end;
@@ -2225,7 +2225,7 @@ package body common_pkg is
-- Get the index K in the select setting array for the reorder2 cell on stage I and row J in a reorder network with N stages
function func_common_reorder2_get_select_index(I, J, N : natural) return integer is
- constant c_nof_reorder2_per_odd_stage : natural := N /2;
+ constant c_nof_reorder2_per_odd_stage : natural := N / 2;
constant c_nof_reorder2_per_even_stage : natural := (N - 1) / 2;
variable v_nof_odd_stages : natural;
variable v_nof_even_stages : natural;
@@ -2347,7 +2347,7 @@ package body common_pkg is
-- Create Pfactor SCLK periods within this DCLK period
SCLK <= '0';
if Pfactor > 1 then
- for I in 0 to 2 * Pfactor - 1 -2 loop
+ for I in 0 to 2 * Pfactor - 1 - 2 loop
wait for v_speriod / 2;
SCLK <= not SCLK;
end loop;
@@ -2359,4 +2359,4 @@ package body common_pkg is
wait;
end proc_common_dclk_generate_sclk;
-end common_pkg;
+end common_pkg;
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
index a9d8a6610cb8dd3dd9d765ffb11a28a45433ccfa..f75f3e2cc937b1b9b3cd70a802611cea70a10c27 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
@@ -265,7 +265,7 @@ package dp_stream_pkg is
function REPLICATE_DP_DATA( seq : std_logic_vector ) return std_logic_vector; -- replicate seq as often as fits in c_dp_stream_data_w
function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w : natural) return std_logic_vector; -- unreplicate data to width seq_w, return low seq_w bits and set mismatch MSbits bits to '1'
- function TO_DP_SOSI_unsigned(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : UNSIGNED) return t_dp_sosi_unsigned;
+ function TO_DP_SOSI_unsigned(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned;
-- Keep part of head data and combine part of tail data, use the other sosi from head_sosi
function func_dp_data_shift_first(head_sosi, tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail : natural) return t_dp_sosi;
@@ -590,7 +590,7 @@ package body dp_stream_pkg is
return v_vec(c_data_w - 1 downto 0);
end UNREPLICATE_DP_DATA;
- function TO_DP_SOSI_unsigned(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : UNSIGNED) return t_dp_sosi_unsigned is
+ function TO_DP_SOSI_unsigned(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned is
variable v_sosi_unsigned : t_dp_sosi_unsigned;
begin
v_sosi_unsigned.sync := sync;
@@ -737,8 +737,8 @@ package body dp_stream_pkg is
for I in dp'range loop
if mask(I) = '1' then
v_any := '1';
- if str ="READY " then v_vec(I) := dp(I).ready;
- elsif str ="XON " then v_vec(I) := dp(I).xon;
+ if str ="READY " then v_vec(I) := dp(I).ready;
+ elsif str ="XON " then v_vec(I) := dp(I).xon;
else report "Error in func_dp_stream_arr_and for t_dp_siso_arr";
end if;
end if;
@@ -759,10 +759,10 @@ package body dp_stream_pkg is
for I in dp'range loop
if mask(I) = '1' then
v_any := '1';
- if str ="VALID " then v_vec(I) := dp(I).valid;
- elsif str ="SOP " then v_vec(I) := dp(I).sop;
- elsif str ="EOP " then v_vec(I) := dp(I).eop;
- elsif str ="SYNC " then v_vec(I) := dp(I).sync;
+ if str ="VALID " then v_vec(I) := dp(I).valid;
+ elsif str ="SOP " then v_vec(I) := dp(I).sop;
+ elsif str ="EOP " then v_vec(I) := dp(I).eop;
+ elsif str ="SYNC " then v_vec(I) := dp(I).sync;
else report "Error in func_dp_stream_arr_and for t_dp_sosi_arr";
end if;
end if;
@@ -795,8 +795,8 @@ package body dp_stream_pkg is
for I in dp'range loop
if mask(I) = '1' then
v_any := '1';
- if str ="READY " then v_vec(I) := dp(I).ready;
- elsif str ="XON " then v_vec(I) := dp(I).xon;
+ if str ="READY " then v_vec(I) := dp(I).ready;
+ elsif str ="XON " then v_vec(I) := dp(I).xon;
else report "Error in func_dp_stream_arr_or for t_dp_siso_arr";
end if;
end if;
@@ -817,10 +817,10 @@ package body dp_stream_pkg is
for I in dp'range loop
if mask(I) = '1' then
v_any := '1';
- if str ="VALID " then v_vec(I) := dp(I).valid;
- elsif str ="SOP " then v_vec(I) := dp(I).sop;
- elsif str ="EOP " then v_vec(I) := dp(I).eop;
- elsif str ="SYNC " then v_vec(I) := dp(I).sync;
+ if str ="VALID " then v_vec(I) := dp(I).valid;
+ elsif str ="SOP " then v_vec(I) := dp(I).sop;
+ elsif str ="EOP " then v_vec(I) := dp(I).eop;
+ elsif str ="SYNC " then v_vec(I) := dp(I).sync;
else report "Error in func_dp_stream_arr_or for t_dp_sosi_arr";
end if;
end if;
@@ -852,8 +852,8 @@ package body dp_stream_pkg is
variable v_slv : std_logic_vector(dp'range) := slv; -- map to ensure same range as for dp
begin
for I in dp'range loop
- if str ="READY " then v_dp(I).ready := v_slv(I);
- elsif str ="XON " then v_dp(I).xon := v_slv(I);
+ if str ="READY " then v_dp(I).ready := v_slv(I);
+ elsif str ="XON " then v_dp(I).xon := v_slv(I);
else report "Error in func_dp_stream_arr_set for t_dp_siso_arr";
end if;
end loop;
@@ -865,10 +865,10 @@ package body dp_stream_pkg is
variable v_slv : std_logic_vector(dp'range) := slv; -- map to ensure same range as for dp
begin
for I in dp'range loop
- if str ="VALID " then v_dp(I).valid := v_slv(I);
- elsif str ="SOP " then v_dp(I).sop := v_slv(I);
- elsif str ="EOP " then v_dp(I).eop := v_slv(I);
- elsif str ="SYNC " then v_dp(I).sync := v_slv(I);
+ if str ="VALID " then v_dp(I).valid := v_slv(I);
+ elsif str ="SOP " then v_dp(I).sop := v_slv(I);
+ elsif str ="EOP " then v_dp(I).eop := v_slv(I);
+ elsif str ="SYNC " then v_dp(I).sync := v_slv(I);
else report "Error in func_dp_stream_arr_set for t_dp_sosi_arr";
end if;
end loop;
@@ -891,8 +891,8 @@ package body dp_stream_pkg is
variable v_ctrl : std_logic_vector(dp'range);
begin
for I in dp'range loop
- if str ="READY " then v_ctrl(I) := dp(I).ready;
- elsif str ="XON " then v_ctrl(I) := dp(I).xon;
+ if str ="READY " then v_ctrl(I) := dp(I).ready;
+ elsif str ="XON " then v_ctrl(I) := dp(I).xon;
else report "Error in func_dp_stream_arr_get for t_dp_siso_arr";
end if;
end loop;
@@ -903,10 +903,10 @@ package body dp_stream_pkg is
variable v_ctrl : std_logic_vector(dp'range);
begin
for I in dp'range loop
- if str ="VALID " then v_ctrl(I) := dp(I).valid;
- elsif str ="SOP " then v_ctrl(I) := dp(I).sop;
- elsif str ="EOP " then v_ctrl(I) := dp(I).eop;
- elsif str ="SYNC " then v_ctrl(I) := dp(I).sync;
+ if str ="VALID " then v_ctrl(I) := dp(I).valid;
+ elsif str ="SOP " then v_ctrl(I) := dp(I).sop;
+ elsif str ="EOP " then v_ctrl(I) := dp(I).eop;
+ elsif str ="SYNC " then v_ctrl(I) := dp(I).sync;
else report "Error in func_dp_stream_arr_get for t_dp_sosi_arr";
end if;
end loop;
@@ -1245,12 +1245,12 @@ package body dp_stream_pkg is
function func_dp_stream_set_data(dp : t_dp_sosi; slv : std_logic_vector; str : string) return t_dp_sosi is
variable v_dp : t_dp_sosi := dp;
begin
- if str ="DATA " then v_dp.data := RESIZE_DP_DATA(slv);
- elsif str ="DSP " then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ if str ="DATA " then v_dp.data := RESIZE_DP_DATA(slv);
+ elsif str ="DSP " then v_dp.re := RESIZE_DP_DSP_DATA(slv);
v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str ="RE " then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- elsif str ="IM " then v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str ="all " then v_dp.data := RESIZE_DP_DATA(slv);
+ elsif str ="RE " then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ elsif str ="IM " then v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str ="all " then v_dp.data := RESIZE_DP_DATA(slv);
v_dp.re := RESIZE_DP_DSP_DATA(slv);
v_dp.im := RESIZE_DP_DSP_DATA(slv);
else report "Error in func_dp_stream_set_data for t_dp_sosi";
@@ -1420,10 +1420,10 @@ package body dp_stream_pkg is
v_src_out.im := (others => '0');
for i in 0 to nof_data - 1 loop
v_in_data := snk_in.data((i + 1) * in_w - 1 downto i * in_w);
- if data_representation ="unsigned " then -- treat data as unsigned
+ if data_representation ="unsigned " then -- treat data as unsigned
v_out_data := RESIZE_UVEC(v_in_data, out_w);
else
- if data_representation ="signed " then -- treat data as signed
+ if data_representation ="signed " then -- treat data as signed
v_out_data := RESIZE_SVEC(v_in_data, out_w);
else
-- treat data as complex
@@ -1486,4 +1486,4 @@ package body dp_stream_pkg is
return src_out_arr(0);
end;
-end dp_stream_pkg;
+end dp_stream_pkg;
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
index 3ca37696f6210b475ad03f17fa917465a1738f28..74e8f2b1e63dd3b34662c44f06b72139cb8dedda 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
@@ -106,7 +106,7 @@ package eth_pkg is
-- . write/read back registers
type t_eth_demux_ports_arr is array(1 to c_eth_nof_udp_ports) of std_logic_vector(c_network_udp_port_w - 1 downto 0);
type t_eth_mm_reg_demux is record
- udp_ports_en : std_logic_vector(1 TO c_eth_nof_udp_ports); -- [16]
+ udp_ports_en : std_logic_vector(1 to c_eth_nof_udp_ports); -- [16]
udp_ports : t_eth_demux_ports_arr; -- [15:0]
end record;
@@ -349,4 +349,4 @@ package body eth_pkg is
return v_reg;
end func_eth_mm_reg_status;
-end eth_pkg;
+end eth_pkg;
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
index c25f4d4776a354b90c243f9e0f6d4c0ffc4a4ecc..705524fb12c47fa822c568e717d3f18963d7cc87 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
@@ -81,4 +81,4 @@
coe_tse_waitrequest_export => CONNECTED_TO_coe_tse_waitrequest_export, -- tse_waitrequest.export
coe_tse_write_export => CONNECTED_TO_coe_tse_write_export, -- tse_write.export
coe_tse_writedata_export => CONNECTED_TO_coe_tse_writedata_export -- tse_writedata.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
index c7ca333408b002445817fc66d2b8c8111d6197ac..7bc86549a50407b84e052a86a6e6a143d0ab946f 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
@@ -13,4 +13,4 @@
in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
index 3e5eaafd868c45ef34e30a8dad9dab73449317f8..26d93a9ea30cb8643ffe32207b93aa21193fe2c6 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
@@ -57,4 +57,4 @@
irq => CONNECTED_TO_irq, -- irq.irq
reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
reset_req => CONNECTED_TO_reset_req -- .reset_req
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
index c08fcff0abdd4a786a80116dc6269e2e413475cd..c2abb9e91f687cabdedff86d2d692f8b221aaf5e 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
@@ -97,4 +97,4 @@
sof => CONNECTED_TO_sof, -- sof.export
somf => CONNECTED_TO_somf, -- somf.export
sysref => CONNECTED_TO_sysref -- sysref.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd
index c649161846cb038720bcdf711777fee68d05431a..b4173dc058e0d5b5c5820fb8d12153d10d5088f8 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd
@@ -757,4 +757,4 @@ begin
--
--synthesis read_comments_as_HDL off
-end europa;
+end europa;
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
index da3c2aa0181c85bc9c7bbd373f3847f1810ec1fb..c9c479a863d07b04ec60cddb00941ed037d3a402 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
@@ -25,4 +25,4 @@
clk => CONNECTED_TO_clk, -- clk.clk
av_irq => CONNECTED_TO_av_irq, -- irq.irq
rst_n => CONNECTED_TO_rst_n -- reset.reset_n
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd
index 19adb8c437d4a0283fe6ce73ec1be5dddf1b5755..1949dd0fa4f5a139ce4b9ee8083935c1af23c191 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd
@@ -115,4 +115,4 @@ begin
--vhdl renameroo for output signals
readdata <= internal_readdata;
-end europa;
+end europa;
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
index 6ad2b21a321d7fc6b052fa99f2cab846205280df..ecb126859925864d13a9e71a87f62344b2e25c9e 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
@@ -25,4 +25,4 @@
readdata => CONNECTED_TO_readdata, -- .readdata
writedata => CONNECTED_TO_writedata, -- .writedata
byteenable => CONNECTED_TO_byteenable -- .byteenable
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
index 9e07f4b8fe33ddb566b916d8d6623ec3c750fbb5..ec3101547f6408d720595d0f927b5d5c2e1506a2 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
@@ -41,4 +41,4 @@
csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
index d3e5d94238fb3b6ff7f39aa1682fc056ebb73652..0794de5258c9dc63924fbd02c4855973fd51fd9b 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
@@ -41,4 +41,4 @@
csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd
index 12348df1d3a2f455eab871bd6b7378cf2318f261..07d15bd0f771ebdf4e6046c8bf62294a88660f94 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd
@@ -68,4 +68,4 @@ begin
readdata <= std_logic_vector'("00000000000000000000000000000000") or (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(read_mux_out)));
out_port <= data_out;
-end europa;
+end europa;
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
index 159b52690b55259dad655e9c976788e9ea5146ae..c63d9306e76cbfd60b817a46df2032905119a9aa 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
@@ -21,4 +21,4 @@
writedata => CONNECTED_TO_writedata, -- .writedata
chipselect => CONNECTED_TO_chipselect, -- .chipselect
readdata => CONNECTED_TO_readdata -- .readdata
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
index dfa2f39fe1bb4e5ca3903d7bd2d38c1daa7bc5d0..ca70a8648ec81b1f25d6bbbd55930b5d52c902eb 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
@@ -41,4 +41,4 @@
csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
index 789342aa93d4009f761e9f3149c36eeadf3530bb..24610ced4a0afa79fa2df090df98e3c4bb58601c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
@@ -41,4 +41,4 @@
csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
index 7cdf6ac161a5c25da865a44f08b28175ddd0af2f..81ba1431b7f36c3246f8c4b4839df0bdd9a27957 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
@@ -41,4 +41,4 @@
csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
index 952f9fa07a3eb2deea90c13efc65be3b8b646736..a12984f10bbf0d09735d96acde9a27c5f344468e 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
@@ -41,4 +41,4 @@
csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
index 4e82d31b6b9d6407a435657a5050f8dbce4a94bb..d283f75c59a8e56f82266b5ea5df067be4cde6ca 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
@@ -41,4 +41,4 @@
csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
index fc8e7129557ae72f7dd50329c37ed574d2236c07..3eb5fb91db727323ade6d08518e4f05267aaccbd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
@@ -41,4 +41,4 @@
csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
index 8f1fa9306f2393a7b82b34840f29cd4f9d336011..a15759ed5cacd25f1d02bb0ae2257ba9fcdf613e 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
@@ -41,4 +41,4 @@
csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
index 6c55e1250f8422fd4313cb1e13891701c3e2819d..e349d2f690494b83716368382044e44c530ff8af 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
@@ -41,4 +41,4 @@
csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
index e1eab332082486cfbe90545463d9bc7f6ddcea50..0a6189d1f8d02a09efcfd8e27230257bd6525225 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
@@ -41,4 +41,4 @@
csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
index ad6aca5eccffbc5900c7ea8afb18f52475af39a3..060d8f43d74d87e100fcd9d8bfb2b25ce5f94ce6 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
@@ -41,4 +41,4 @@
csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
index d021b96883fb1192c3ecf575486624514609de21..7aa35c95742f359513d404dfd07e048e39fdc85e 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
@@ -41,4 +41,4 @@
csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
index 84e748f11e8ffbd6f2e0895e78d6268f68b0075c..3156e1f7115453925a47d0e3ce6ebfef982b9cf4 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
@@ -41,4 +41,4 @@
csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd
index e965bdbf560982e2f8b296e01918df0e61e357ee..fa95d5ce0a4c2f5bac3b1737908132b8b970becf 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd
@@ -146,7 +146,7 @@ begin
irq <= timeout_occurred and control_interrupt_enable;
--s1, which is an e_avalon_slave
- read_mux_out <= ((A_REP(to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000001")))), 16) and (std_logic_vector'("000000000000000") & (A_TOSTDLOGICVECTor(control_register))))) OR ((A_REP(to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000000")))), 16) and (std_logic_vector'("00000000000000") & (std_logic_vector'(A_ToStdLogicVector(counter_is_running) & A_ToStdLogicVector(timeout_occurred))))));
+ read_mux_out <= ((A_REP(to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000001")))), 16) and (std_logic_vector'("000000000000000") & (A_TOSTDLOGICVECTor(control_register))))) or ((A_REP(to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000000")))), 16) and (std_logic_vector'("00000000000000") & (std_logic_vector'(A_ToStdLogicVector(counter_is_running) & A_ToStdLogicVector(timeout_occurred))))));
process (clk, reset_n)
begin
if reset_n = '0' then
@@ -177,4 +177,4 @@ begin
control_interrupt_enable <= control_register;
status_wr_strobe <= (chipselect and not write_n) and to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000000"))));
-end europa;
+end europa;
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
index 89bce420fd86c0facac177eff6b93b90a9a9e9cf..5dc19007e00295cd33b03bc364f621968353ef93 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
@@ -21,4 +21,4 @@
readdata => CONNECTED_TO_readdata, -- .readdata
chipselect => CONNECTED_TO_chipselect, -- .chipselect
write_n => CONNECTED_TO_write_n -- .write_n
- );
+ );
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/unb2b_jesd_node3.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/unb2b_jesd_node3.vhd
index 63ad9d9a69c351eaa1af8698a80c95025b4587ca..9ff7cd431291d4c218a05c6b2fcea77516a0c169 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/unb2b_jesd_node3.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/unb2b_jesd_node3.vhd
@@ -66,8 +66,8 @@ entity unb2b_jesd_node3 is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
@@ -131,4 +131,4 @@ begin
jesd204_device_clk => jesd204_device_clk
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd
index a35cf837a5723e7eb36c43230177aee2de5e84ba..ed56980eb1e126024f1d40509c5906e491b69876 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd
@@ -67,8 +67,8 @@ entity unb2b_jesd is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
@@ -432,4 +432,4 @@ begin
in_sync => st_pps
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/unb2b_minimal_125m.vhd b/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/unb2b_minimal_125m.vhd
index 5dac4afb376e1171c47b17220bfa5556ffc21c3d..2290b579a18fef1b97f79dec44b329ba0f297228 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/unb2b_minimal_125m.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/unb2b_minimal_125m.vhd
@@ -65,8 +65,8 @@ entity unb2b_minimal_125m is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0)
);
diff --git a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd
index 48448b9faa96d184fe0e240c6c5633ec8a8e529f..298a993f610739d13d7b88526bdee7aff8b36f60 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd
@@ -65,8 +65,8 @@ entity unb2b_minimal is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0)
);
@@ -78,7 +78,7 @@ architecture str of unb2b_minimal is
-- Firmware version x.y
-- If x >= 2, rom_info starts on 0x10000 and max size = 0x8192 words
constant c_fw_version : t_unb2b_board_fw_version := (2, 0);
- constant c_use_125m : boolean := g_design_name ="unb2b_minimal_125m ";
+ constant c_use_125m : boolean := g_design_name ="unb2b_minimal_125m ";
constant c_mm_clk_freq : natural := sel_a_b(c_use_125m, c_unb2b_board_mm_clk_freq_125M, c_unb2b_board_mm_clk_freq_50M);
-- System
@@ -390,4 +390,4 @@ begin
QSFP_LED => QSFP_LED
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/tb_unb2b_test_10GbE.vhd b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/tb_unb2b_test_10GbE.vhd
index e65f0a6da3db1f816beeb5d3b1bbbda7950633fd..bf61b65bbfbc8159c8d4adc0b9827b15b1df3fd0 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/tb_unb2b_test_10GbE.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/tb_unb2b_test_10GbE.vhd
@@ -34,4 +34,4 @@ begin
generic map (
g_design_name => "unb2b_test_10GbE"
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/unb2b_test_10GbE.vhd b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/unb2b_test_10GbE.vhd
index 4fc72d123dab361d83c13b9e10cbc353fc36d32f..c270a715a3652a211040ba2b6c5a1fc65fe34265 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/unb2b_test_10GbE.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/unb2b_test_10GbE.vhd
@@ -58,8 +58,8 @@ entity unb2b_test_10GbE is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic; -- Clock 10GbE front (qsfp) and ring lines
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/tb_unb2b_test_ddr_MB_I_II.vhd b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/tb_unb2b_test_ddr_MB_I_II.vhd
index 418f563b1140e82db106e7b581ff8297af976fd9..a4cb9c852c860ed8c6f33323f40cf4a7b721d376 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/tb_unb2b_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/tb_unb2b_test_ddr_MB_I_II.vhd
@@ -37,4 +37,4 @@ begin
g_design_name => "unb2b_test_ddr_MB_I_II",
g_sim_model_ddr => FALSE
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/unb2b_test_ddr_MB_I_II.vhd b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/unb2b_test_ddr_MB_I_II.vhd
index b2ee169f52a8f535896b39b183e461c21717a7fe..cd053632c651f9efb9ba2822222f448a46abb44f 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/unb2b_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/unb2b_test_ddr_MB_I_II.vhd
@@ -63,20 +63,20 @@ entity unb2b_test_ddr_MB_I_II is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- DDR reference clocks
MB_I_REF_CLK : in std_logic; -- Reference clock for MB_I
MB_II_REF_CLK : in std_logic; -- Reference clock for MB_II
-- SO-DIMM Memory Bank I
- MB_I_in : IN t_tech_ddr4_phy_in;
+ MB_I_in : in t_tech_ddr4_phy_in;
MB_I_IO : inout t_tech_ddr4_phy_io;
MB_I_OU : out t_tech_ddr4_phy_ou;
-- SO-DIMM Memory Bank II
- MB_II_in : IN t_tech_ddr4_phy_in;
+ MB_II_in : in t_tech_ddr4_phy_in;
MB_II_IO : inout t_tech_ddr4_phy_io;
MB_II_OU : out t_tech_ddr4_phy_ou;
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
index dc1476517cb51a57aee9832f50f723e97f29065e..1fbf269895a3a13b602a5973f4f4c6e790f11b19 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
@@ -388,4 +388,4 @@ package qsys_unb2b_test_pkg is
-end qsys_unb2b_test_pkg;
+end qsys_unb2b_test_pkg;
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/udp_stream.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/udp_stream.vhd
index 23b35ae35f0af8f13d6e4593f692976a229b9b51..a1697d7b7cf4b10f0cffe6b3814aee1701a31736 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/udp_stream.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/udp_stream.vhd
@@ -354,4 +354,4 @@ begin
in_sosi_arr => diag_data_buf_snk_in_arr
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd
index 0e940e699097d700985ac79c0f4cca315c42f9ff..897865a404860984e16512471da639199683df8e 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd
@@ -71,8 +71,8 @@ entity unb2b_test is
-- 1GbE Control Interface
ETH_CLK : in std_logic;
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
@@ -123,12 +123,12 @@ entity unb2b_test is
QSFP_RST : inout std_logic;
-- SO-DIMM Memory Bank I
- MB_I_in : IN t_tech_ddr4_phy_in := c_tech_ddr4_phy_in_x;
+ MB_I_in : in t_tech_ddr4_phy_in := c_tech_ddr4_phy_in_x;
MB_I_IO : inout t_tech_ddr4_phy_io;
MB_I_OU : out t_tech_ddr4_phy_ou;
-- SO-DIMM Memory Bank II
- MB_II_in : IN t_tech_ddr4_phy_in := c_tech_ddr4_phy_in_x;
+ MB_II_in : in t_tech_ddr4_phy_in := c_tech_ddr4_phy_in_x;
MB_II_IO : inout t_tech_ddr4_phy_io;
MB_II_OU : out t_tech_ddr4_phy_ou;
@@ -148,13 +148,13 @@ architecture str of unb2b_test is
-- Revision controlled constants
constant c_use_1GbE : boolean := FALSE; --g_design_name="unb2b_test_1GbE" OR g_design_name="unb2b_test_10GbE" OR g_design_name="unb2b_test_all";
- constant c_use_10GbE : boolean := g_design_name ="unb2b_test_10GbE " or g_design_name ="unb2b_test_all ";
+ constant c_use_10GbE : boolean := g_design_name ="unb2b_test_10GbE " or g_design_name ="unb2b_test_all ";
constant c_use_10GbE_qsfp : boolean := c_use_10GbE;
constant c_use_10GbE_ring : boolean := FALSE; --c_use_10GbE;
constant c_use_10GbE_back0 : boolean := FALSE; --c_use_10GbE;
constant c_use_10GbE_back1 : boolean := FALSE; --c_use_10GbE;
- constant c_use_MB_I : boolean := g_design_name ="unb2b_test_ddr_MB_I " or g_design_name ="unb2b_test_ddr_MB_I_II " or g_design_name ="unb2b_test_all ";
- constant c_use_MB_II : boolean := g_design_name ="unb2b_test_ddr_MB_II " or g_design_name ="unb2b_test_ddr_MB_I_II " or g_design_name ="unb2b_test_all ";
+ constant c_use_MB_I : boolean := g_design_name ="unb2b_test_ddr_MB_I " or g_design_name ="unb2b_test_ddr_MB_I_II " or g_design_name ="unb2b_test_all ";
+ constant c_use_MB_II : boolean := g_design_name ="unb2b_test_ddr_MB_II " or g_design_name ="unb2b_test_ddr_MB_I_II " or g_design_name ="unb2b_test_all ";
-- transceivers
constant c_nof_qsfp : natural := c_unb2b_board_tr_qsfp.nof_bus * c_unb2b_board_tr_qsfp.bus_w;
@@ -1261,4 +1261,4 @@ begin
);
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test_pkg.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test_pkg.vhd
index f4aaac280d3a813ead99700beb38e57672601a30..3b1dae7d19c6a609e3868181a93d282d6f57315f 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test_pkg.vhd
@@ -29,7 +29,7 @@ package unb2b_test_pkg is
-- dp_offload_tx
--CONSTANT c_nof_hdr_fields : NATURAL := 1+3+12+4+2; -- Total header bits = 384 = 6 64b words
- constant c_nof_hdr_fields : natural := 3 +12 + 4 + 2; -- Total header bits = 384 = 6 64b words
+ constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 2; -- Total header bits = 384 = 6 64b words
constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( --( field_name_pad("align" ), " ", 16, field_default(0) ),
( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
@@ -54,6 +54,6 @@ package unb2b_test_pkg is
( field_name_pad("usr_bsn" ), " ", 47, field_default(0) ));
--CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "1001"&"111111111100"&"0011"&"00";
- constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "001" &"111111111100 " &"0011 " &"00 ";
+ constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "001" &"111111111100 " &"0011 " &"00 ";
-end unb2b_test_pkg;
+end unb2b_test_pkg;
\ No newline at end of file
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
index ee4a5d6a88286ed61a057c1da6012a74e9fb0e54..8970689946b02520b96f70c581d94d358a3cfbf1 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
@@ -250,8 +250,8 @@ entity ctrl_unb2b_board is
-- 1GbE Control Interface
ETH_CLK : in std_logic; -- 125 MHz
- ETH_SGin : IN std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0) := (others => '0');
- ETH_SGout : OUT std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0)
+ ETH_SGin : in std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0) := (others => '0');
+ ETH_SGout : out std_logic_vector(c_unb2b_board_nof_eth - 1 downto 0)
);
end ctrl_unb2b_board;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_sens.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_sens.vhd
index 3b6a50dfbc9769339d13390b12485d6bdb774e85..a9720b77586affa5d42f6a57add92bf7dfea652c 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_sens.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_sens.vhd
@@ -118,4 +118,4 @@ begin
-- temp_high is 7 bits, preceded by a '0' to allow only positive temps to be set.
temp_alarm <= '1' when (signed(sens_data(0)) > signed('0' & temp_high)) else '0';
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd
index 9320a5023a7bbeb17c930de3da3f2250fab15a78..e2764d43e14b2e2fc2d9238a367e3a611943f73b 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd
@@ -72,7 +72,7 @@ architecture str of mms_unb2b_board_system_info is
-- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
-- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
- constant c_mif_name : string := sel_a_b(g_sim, "UNUSED", sel_a_b((g_design_name ="UNUSED "), g_design_name, c_path_prefix & g_design_name & ".mif"));
+ constant c_mif_name : string := sel_a_b(g_sim, "UNUSED", sel_a_b((g_design_name ="UNUSED "), g_design_name, c_path_prefix & g_design_name & ".mif"));
constant c_rom_addr_w : natural := 13; -- 2^13 = 8192 addresses * 32 bits = 32 kiB
@@ -137,4 +137,4 @@ begin
rd_val => rom_miso.rdval
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd
index e4ef196556c3040bb88875910caf937d426e9088..15af6cb78b57bb4f5310515388d24462c6d5c929 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd
@@ -78,4 +78,4 @@ begin
reg_voltage_store_miso => reg_voltage_miso
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_ring_io.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_ring_io.vhd
index 62df93bea343cb9abf5ff870695658863a992874..7a965e9d7ed878c2174d4ddbc883919c1887191c 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_ring_io.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_ring_io.vhd
@@ -32,7 +32,7 @@ entity unb2b_board_ring_io is
serial_tx_arr : in std_logic_vector(g_nof_ring_bus * c_unb2b_board_tr_ring.bus_w - 1 downto 0) := (others => '0');
serial_rx_arr : out std_logic_vector(g_nof_ring_bus * c_unb2b_board_tr_ring.bus_w - 1 downto 0);
- RinG_RX : IN t_unb2b_board_ring_bus_2arr(g_nof_ring_bus - 1 downto 0) := (others => (others => '0'));
+ RinG_RX : in t_unb2b_board_ring_bus_2arr(g_nof_ring_bus - 1 downto 0) := (others => (others => '0'));
RING_TX : out t_unb2b_board_ring_bus_2arr(g_nof_ring_bus - 1 downto 0)
);
end unb2b_board_ring_io;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd
index 6696033d8b9e384b48f23607e1d5b35f38f57ca6..03c19edb6b9b06ea9b612c67c61e6e9b21998266 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd
@@ -151,4 +151,4 @@ begin
end process;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_reg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_reg.vhd
index 80e1717c3a3892493ed406da6422b0fb556da459..9221d701d54519ae8361a1d723fb35e5a88ec251 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_reg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_reg.vhd
@@ -86,4 +86,4 @@ begin
end if;
end process;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2b_board_sens.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2b_board_sens.vhd
index d074d2deb62fe18f88cefe1e209d3b7796fb6187..49264f60372b074a049bc29170770e165d2ccdad 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2b_board_sens.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2b_board_sens.vhd
@@ -211,4 +211,4 @@ begin
ana_volt_adin => c_uniboard_adin
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/boards/uniboard2c/designs/unb2c_led/src/vhdl/unb2c_led.vhd b/boards/uniboard2c/designs/unb2c_led/src/vhdl/unb2c_led.vhd
index b442c9e59bc093a17b18b2d225940198d39fb967..e63f299e81de7bcc221506b1eca34b990305bba5 100644
--- a/boards/uniboard2c/designs/unb2c_led/src/vhdl/unb2c_led.vhd
+++ b/boards/uniboard2c/designs/unb2c_led/src/vhdl/unb2c_led.vhd
@@ -247,4 +247,4 @@ begin
QSFP_LED(5) <= ETH_CLK(0);
QSFP_LED(9) <= ETH_CLK(1);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/unb2c_minimal.vhd b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/unb2c_minimal.vhd
index 510dd2dd8bb0ddfe01f8e1f4eed124fb482d0b10..6d03df6459432cd7f0bfb7a0c47409dcff9e664b 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/unb2c_minimal.vhd
+++ b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/unb2c_minimal.vhd
@@ -57,8 +57,8 @@ entity unb2c_minimal is
-- 1GbE Control Interface
ETH_CLK : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGin : IN std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0)
);
@@ -356,4 +356,4 @@ begin
QSFP_LED => QSFP_LED
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/tb_unb2c_test_10GbE.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/tb_unb2c_test_10GbE.vhd
index 76dc43cc5ac583999da09546a989ba4b299b5f5f..7f219e6e4ce8f5c5d8188681eff57eb030f161fb 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/tb_unb2c_test_10GbE.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/tb_unb2c_test_10GbE.vhd
@@ -34,4 +34,4 @@ begin
generic map (
g_design_name => "unb2c_test_10GbE"
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd
index a6474c97b349cbedcc8962df38fbab6c877361c3..a7647a12ca0882ed97412e548be10cd8e6d6a8e8 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd
@@ -55,8 +55,8 @@ entity unb2c_test_10GbE is
-- 1GbE Control Interface
ETH_CLK : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGin : IN std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic; -- Clock 10GbE front (qsfp) and ring lines
@@ -68,9 +68,9 @@ entity unb2c_test_10GbE is
--BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2c_board_tr_back.bus_w * c_unb2c_board_tr_back.nof_bus)-1 downto 0);
-- ring transceivers
- RinG_0_RX : IN std_logic_vector(c_unb2c_board_tr_ring.bus_w - 1 downto 0);
+ RinG_0_RX : in std_logic_vector(c_unb2c_board_tr_ring.bus_w - 1 downto 0);
RING_0_TX : out std_logic_vector(c_unb2c_board_tr_ring.bus_w - 1 downto 0);
- RinG_1_RX : IN std_logic_vector(c_unb2c_board_tr_ring.bus_w - 1 downto 0);
+ RinG_1_RX : in std_logic_vector(c_unb2c_board_tr_ring.bus_w - 1 downto 0);
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_ring.bus_w - 1 downto 0);
-- front transceivers
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd
index b13c20863b812344425d2073416f5b99fe2d3dac..21751a5ae25b7d58e7003843fe4fceb137eb84d6 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd
@@ -95,4 +95,4 @@ begin
QSFP_LED => open
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd
index 37fd0b06f7230cc9fc9ab7fd97597854490b47c5..b9b0f586a8b1a75621bae0cfa4807af17de6ec72 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd
@@ -59,8 +59,8 @@ entity unb2c_test_1GbE_I is
-- 1GbE Control Interface
ETH_CLK : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGin : IN std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0)
);
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/tb_unb2c_test_1GbE_II.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/tb_unb2c_test_1GbE_II.vhd
index 5fd77ad14f1318ad615b084931faa1e2f1540de2..07d84c26d8b5918de1b7cc57ac19825a45a3bf6a 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/tb_unb2c_test_1GbE_II.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/tb_unb2c_test_1GbE_II.vhd
@@ -98,4 +98,4 @@ begin
QSFP_LED => open
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/unb2c_test_1GbE_II.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/unb2c_test_1GbE_II.vhd
index 9fdff96fcbb474ee4d04f0c3e16651964eb1e9d6..e1a01987164af9374e35700e30055ca9df017615 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/unb2c_test_1GbE_II.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/unb2c_test_1GbE_II.vhd
@@ -59,8 +59,8 @@ entity unb2c_test_1GbE_II is
-- 1GbE Control Interface
ETH_CLK : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGin : IN std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0)
);
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/tb_unb2c_test_ddr.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/tb_unb2c_test_ddr.vhd
index 0fc29fe4c9efd8553fe971894944d378bf04718c..d874b5f98cd42b1368221767b11018d70151a9e1 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/tb_unb2c_test_ddr.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/tb_unb2c_test_ddr.vhd
@@ -34,4 +34,4 @@ begin
generic map (
g_design_name => "unb2c_test_ddr"
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/unb2c_test_ddr.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/unb2c_test_ddr.vhd
index 51b5b1b528a0e7ee8d8c8f5be9fd5af2e64458c2..6973347515205c221366e745d09efcd795b7fa3e 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/unb2c_test_ddr.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/unb2c_test_ddr.vhd
@@ -56,20 +56,20 @@ entity unb2c_test_ddr is
-- 1GbE Control Interface
ETH_CLK : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGin : IN std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- DDR reference clocks
MB_I_REF_CLK : in std_logic; -- Reference clock for MB_I
MB_II_REF_CLK : in std_logic; -- Reference clock for MB_II
-- SO-DIMM Memory Bank I
- MB_I_in : IN t_tech_ddr4_phy_in;
+ MB_I_in : in t_tech_ddr4_phy_in;
MB_I_IO : inout t_tech_ddr4_phy_io;
MB_I_OU : out t_tech_ddr4_phy_ou;
-- SO-DIMM Memory Bank II
- MB_II_in : IN t_tech_ddr4_phy_in;
+ MB_II_in : in t_tech_ddr4_phy_in;
MB_II_IO : inout t_tech_ddr4_phy_io;
MB_II_OU : out t_tech_ddr4_phy_ou;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/tb_unb2c_test_ddr_16G.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/tb_unb2c_test_ddr_16G.vhd
index c63f189950bc4061a1338e565eef53cb6d72d7dc..706610c210a00f467e662a15eabac482a2385464 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/tb_unb2c_test_ddr_16G.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/tb_unb2c_test_ddr_16G.vhd
@@ -34,4 +34,4 @@ begin
generic map (
g_design_name => "unb2c_test_ddr_16G"
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/unb2c_test_ddr_16G.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/unb2c_test_ddr_16G.vhd
index e04755ae0ba981c6d492cb85ebd234817c02321a..c2cdd01586a7a1e85ccbb5e3917d936d8a6c1848 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/unb2c_test_ddr_16G.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/unb2c_test_ddr_16G.vhd
@@ -56,20 +56,20 @@ entity unb2c_test_ddr_16G is
-- 1GbE Control Interface
ETH_CLK : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGin : IN std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- DDR reference clocks
MB_I_REF_CLK : in std_logic; -- Reference clock for MB_I
MB_II_REF_CLK : in std_logic; -- Reference clock for MB_II
-- SO-DIMM Memory Bank I
- MB_I_in : IN t_tech_ddr4_phy_in;
+ MB_I_in : in t_tech_ddr4_phy_in;
MB_I_IO : inout t_tech_ddr4_phy_io;
MB_I_OU : out t_tech_ddr4_phy_ou;
-- SO-DIMM Memory Bank II
- MB_II_in : IN t_tech_ddr4_phy_in;
+ MB_II_in : in t_tech_ddr4_phy_in;
MB_II_IO : inout t_tech_ddr4_phy_io;
MB_II_OU : out t_tech_ddr4_phy_ou;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/tb_unb2c_test_heater.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/tb_unb2c_test_heater.vhd
index a321178bf99afb723bc997ab0854d007c01ae489..3ce7215ba82b13b73daf6a69ee19a3c8f685a61d 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/tb_unb2c_test_heater.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/tb_unb2c_test_heater.vhd
@@ -34,4 +34,4 @@ begin
generic map (
g_design_name => "unb2c_test_heater"
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/unb2c_test_heater.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/unb2c_test_heater.vhd
index 11663ce1465be3126af8e0ab72829197177c765c..442c1e2c3c2cfac5096ccc9976ac2d6d82430241 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/unb2c_test_heater.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/unb2c_test_heater.vhd
@@ -55,8 +55,8 @@ entity unb2c_test_heater is
-- 1GbE Control Interface
ETH_CLK : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGin : IN std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0)
);
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/tb_unb2c_test_jesd204b.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/tb_unb2c_test_jesd204b.vhd
index 965114b740c95c37bac4bddfae53f92f8b27468a..4074cb96b495cff9807f628c30bd6caa1396de95 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/tb_unb2c_test_jesd204b.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/tb_unb2c_test_jesd204b.vhd
@@ -34,4 +34,4 @@ begin
generic map (
g_design_name => "unb2c_test_jesd204b"
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/unb2c_test_jesd204b.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/unb2c_test_jesd204b.vhd
index 7a930cb1b92f5a042b809b9a602b375899de3b15..600ac43c1dc13f4e47a8280bb0cb3267cb372caf 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/unb2c_test_jesd204b.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/unb2c_test_jesd204b.vhd
@@ -54,8 +54,8 @@ entity unb2c_test_jesd204b is
-- 1GbE Control Interface
ETH_CLK : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGin : IN std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- jesd204b
BCK_REF_CLK : in std_logic; -- Clock 10GbE back. From external reference. To be used for JESD204B_REFCLK
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd
index 76a491885bc9835514606707a32f981a2a2ed0ac..a0d6f8208909d5904e4bd9ffd91a0255a91ce1a9 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd
@@ -55,8 +55,8 @@ entity unb2c_test_minimal is
-- 1GbE Control Interface
ETH_CLK : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGin : IN std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0)
);
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd
index d0a3da9dc92fa55a18869c04bf8ed9c7a89dfd17..a9e1735f142594666dde826fec480dc3000dbb4a 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd
@@ -465,4 +465,4 @@ package qsys_unb2c_test_pkg is
);
end component qsys_unb2c_test;
-end qsys_unb2c_test_pkg;
+end qsys_unb2c_test_pkg;
\ No newline at end of file
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/udp_stream.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/udp_stream.vhd
index f0c507112ff9027f0dbd5dd6dfe480696014e395..576ba85848c44b11b45de96be21a127e1581d196 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/udp_stream.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/udp_stream.vhd
@@ -354,4 +354,4 @@ begin
in_sosi_arr => diag_data_buf_snk_in_arr
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
index d2408d1d3eeda225ff7dfd1239b4326fed4f8eda..eab316a241fda308714a7f65a5cf6c260dd888b7 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
@@ -69,8 +69,8 @@ entity unb2c_test is
-- 1GbE Control Interface
ETH_CLK : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGin : IN std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
- ETH_SGout : OUT std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGin : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
+ ETH_SGout : out std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
@@ -91,9 +91,9 @@ entity unb2c_test is
JESD204B_SYNC : out std_logic_vector(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
-- ring transceivers
- RinG_0_RX : IN std_logic_vector(c_unb2c_board_tr_ring.bus_w - 1 downto 0) := (others => '0');
+ RinG_0_RX : in std_logic_vector(c_unb2c_board_tr_ring.bus_w - 1 downto 0) := (others => '0');
RING_0_TX : out std_logic_vector(c_unb2c_board_tr_ring.bus_w - 1 downto 0);
- RinG_1_RX : IN std_logic_vector(c_unb2c_board_tr_ring.bus_w - 1 downto 0) := (others => '0');
+ RinG_1_RX : in std_logic_vector(c_unb2c_board_tr_ring.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_ring.bus_w - 1 downto 0);
-- front transceivers
@@ -111,12 +111,12 @@ entity unb2c_test is
QSFP_5_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
-- SO-DIMM Memory Bank I
- MB_I_in : IN t_tech_ddr4_phy_in := c_tech_ddr4_phy_in_x;
+ MB_I_in : in t_tech_ddr4_phy_in := c_tech_ddr4_phy_in_x;
MB_I_IO : inout t_tech_ddr4_phy_io;
MB_I_OU : out t_tech_ddr4_phy_ou;
-- SO-DIMM Memory Bank II
- MB_II_in : IN t_tech_ddr4_phy_in := c_tech_ddr4_phy_in_x;
+ MB_II_in : in t_tech_ddr4_phy_in := c_tech_ddr4_phy_in_x;
MB_II_IO : inout t_tech_ddr4_phy_io;
MB_II_OU : out t_tech_ddr4_phy_ou;
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd
index a3d44bfaccd4378691452dd8f96ef0ed47af1a26..8ad028c17391a4c5b06e5eed319df52be22f10e7 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd
@@ -32,7 +32,7 @@ package unb2c_test_pkg is
-- dp_offload_tx (carried over from unb2a_test_pkg
--CONSTANT c_nof_hdr_fields : NATURAL := 1+3+12+4+2; -- Total header bits = 384 = 6 64b words
- constant c_nof_hdr_fields : natural := 3 +12 + 4 + 2; -- Total header bits = 384 = 6 64b words
+ constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 2; -- Total header bits = 384 = 6 64b words
constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( --( field_name_pad("align" ), " ", 16, field_default(0) ),
( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
@@ -57,7 +57,7 @@ package unb2c_test_pkg is
( field_name_pad("usr_bsn" ), " ", 47, field_default(0) ));
--CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "1001"&"111111111100"&"0011"&"00";
- constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "001" &"111111111100 " &"0011 " &"00 ";
+ constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "001" &"111111111100 " &"0011 " &"00 ";
-----------------------------------------------------------------------------
-- Revision control
-----------------------------------------------------------------------------
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
index d9b51b1692d9a29ca0343dee426264c1fc9c2e44..196feb597a669afc36e286d049216264ee5ea011 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
@@ -233,8 +233,8 @@ entity ctrl_unb2c_board is
-- 1GbE Control Interface
ETH_CLK : in std_logic; -- 125 MHz
- ETH_SGin : IN std_logic; -- _VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0) := (OTHERS=>'0');
- ETH_SGout : OUT std_logic -- _VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0)
+ ETH_SGin : in std_logic; -- _VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0) := (OTHERS=>'0');
+ ETH_SGout : out std_logic -- _VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0)
);
end ctrl_unb2c_board;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_board_system_info.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_board_system_info.vhd
index 20b99ac05d707666ebda4f87e3e7c18ff3f6f158..46d57818dc9eb21adeefc20ce53b30ad9e6cf03b 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_board_system_info.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_board_system_info.vhd
@@ -72,7 +72,7 @@ architecture str of mms_unb2c_board_system_info is
-- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
-- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
- constant c_mif_name : string := sel_a_b(g_sim, "UNUSED", sel_a_b((g_design_name ="UNUSED "), g_design_name, c_path_prefix & g_design_name & ".mif"));
+ constant c_mif_name : string := sel_a_b(g_sim, "UNUSED", sel_a_b((g_design_name ="UNUSED "), g_design_name, c_path_prefix & g_design_name & ".mif"));
constant c_rom_addr_w : natural := 13; -- 2^13 = 8192 addresses * 32 bits = 32 kiB
@@ -137,4 +137,4 @@ begin
rd_val => rom_miso.rdval
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_fpga_sens.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_fpga_sens.vhd
index d7cf5df6795f6a0c7cbb544bbe147f658f4b4f61..94371f7c5502dfc216da5e66bd1f0c321b43b0b1 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_fpga_sens.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_fpga_sens.vhd
@@ -78,4 +78,4 @@ begin
reg_voltage_store_miso => reg_voltage_miso
);
-end str;
+end str;
\ No newline at end of file
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_ring_io.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_ring_io.vhd
index b34e30223ba02c24eabd021e7f325dd4a91df9af..2afffa20676f546bf1d44e29782bbfde09362144 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_ring_io.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_ring_io.vhd
@@ -32,7 +32,7 @@ entity unb2c_board_ring_io is
serial_tx_arr : in std_logic_vector(g_nof_ring_bus * c_unb2c_board_tr_ring.bus_w - 1 downto 0) := (others => '0');
serial_rx_arr : out std_logic_vector(g_nof_ring_bus * c_unb2c_board_tr_ring.bus_w - 1 downto 0);
- RinG_RX : IN t_unb2c_board_ring_bus_2arr(g_nof_ring_bus - 1 downto 0) := (others => (others => '0'));
+ RinG_RX : in t_unb2c_board_ring_bus_2arr(g_nof_ring_bus - 1 downto 0) := (others => (others => '0'));
RING_TX : out t_unb2c_board_ring_bus_2arr(g_nof_ring_bus - 1 downto 0)
);
end unb2c_board_ring_io;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd
index 35a27efeacfcf69c01d449864372d2213647ed68..94926fa428fe3522be4d91d6a0c45afb43c0447a 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd
@@ -151,4 +151,4 @@ begin
end process;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_reg.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_reg.vhd
index a2d1867325c3967774bfd80c383eadda4cb71993..204120473c1708ac4d37cf5b5979d255f5f81fe4 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_reg.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_reg.vhd
@@ -86,4 +86,4 @@ begin
end if;
end process;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/base/axi4/src/vhdl/axi4_lite_mm_bridge.vhd b/libraries/base/axi4/src/vhdl/axi4_lite_mm_bridge.vhd
index 0c9c4274608acd6dd71d37e3a648be49505ce57e..4bf9fec2a8e2c53273ae9749ee935f94228c7697 100644
--- a/libraries/base/axi4/src/vhdl/axi4_lite_mm_bridge.vhd
+++ b/libraries/base/axi4/src/vhdl/axi4_lite_mm_bridge.vhd
@@ -31,7 +31,7 @@
-- . The read latency is not adapted. Ensure that the Controller and Peripheral use the same
-- read-latency.
-- . Both AXI4-lite and MM use ready latency = 0 for waitrequest/ready.
--- . AXI4-lite is assumed to use byte addressed registers while MM uses word addressed
+-- . AXI4-lite is assumed to use byte addressed registers while MM uses word addressed
-- registers.
library IEEE, common_lib;
@@ -115,4 +115,4 @@ begin
d_bvalid <= '0';
end if;
end process;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/axi4/src/vhdl/axi4_lite_pkg.vhd b/libraries/base/axi4/src/vhdl/axi4_lite_pkg.vhd
index 17446d08a949c69bd1a1d4cb1c2afb9c1845156a..5989261eab1d9f8459f87c63e4ec544b802ab66a 100644
--- a/libraries/base/axi4/src/vhdl/axi4_lite_pkg.vhd
+++ b/libraries/base/axi4/src/vhdl/axi4_lite_pkg.vhd
@@ -1,4 +1,3 @@
-<<<<<<< HEAD
-------------------------------------------------------------------------------
--
-- Copyright 2023
@@ -110,9 +109,9 @@ package body axi4_lite_pkg is
variable v_mm_copi : t_mem_copi := c_mem_copi_rst;
begin
if axi4_copi.awvalid = '1' then
- v_mm_copi.address := axi4_copi.awaddr;
+ v_mm_copi.address := "00" & axi4_copi.awaddr(c_axi4_lite_address_w - 1 downto 2); -- convert byte addressed to word addressed.
else
- v_mm_copi.address := axi4_copi.araddr;
+ v_mm_copi.address := "00" & axi4_copi.araddr(c_axi4_lite_address_w - 1 downto 2); -- convert byte addressed to word addressed.
end if;
v_mm_copi.wrdata(c_axi4_lite_data_w - 1 downto 0) := axi4_copi.wdata;
v_mm_copi.wr := axi4_copi.awvalid;
@@ -132,14 +131,14 @@ package body axi4_lite_pkg is
function func_axi4_lite_from_mm_copi(mm_copi : t_mem_copi) return t_axi4_lite_copi is
variable v_axi4_copi : t_axi4_lite_copi := c_axi4_lite_copi_rst;
begin
- v_axi4_copi.awaddr := mm_copi.address;
+ v_axi4_copi.awaddr := mm_copi.address(c_axi4_lite_address_w - 3 downto 0) & "00"; -- convert word addressed to byte addressed.
v_axi4_copi.awprot := (others => '0');
v_axi4_copi.awvalid := mm_copi.wr;
v_axi4_copi.wdata := mm_copi.wrdata(c_axi4_lite_data_w - 1 downto 0);
v_axi4_copi.wstrb := (others => '1'); -- Either ignored or all bytes selected.
v_axi4_copi.wvalid := mm_copi.wr;
v_axi4_copi.bready := '1'; -- Unsupported by MM, assuming always ready.
- v_axi4_copi.araddr := mm_copi.address;
+ v_axi4_copi.araddr := mm_copi.address(c_axi4_lite_address_w - 3 downto 0) & "00"; -- convert word addressed to byte addressed.
v_axi4_copi.arprot := (others => '0');
v_axi4_copi.arvalid := mm_copi.rd;
v_axi4_copi.rready := '1'; -- Unsupported by MM, assuming always ready.
@@ -160,168 +159,4 @@ package body axi4_lite_pkg is
return v_axi4_cipo;
end;
-end axi4_lite_pkg;
-=======
--------------------------------------------------------------------------------
---
--- Copyright 2023
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- Licensed under the Apache License, Version 2.0 (the "License");
--- you may not use this file except in compliance with the License.
--- You may obtain a copy of the License at
---
--- http://www.apache.org/licenses/LICENSE-2.0
---
--- Unless required by applicable law or agreed to in writing, software
--- distributed under the License is distributed on an "AS IS" BASIS,
--- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--- See the License for the specific language governing permissions and
--- limitations under the License.
---
--------------------------------------------------------------------------------
-
--------------------------------------------------------------------------------
--- Author : R vd Walle
--- Purpose:
--- Package containing usefull definitions for working with AXI4-Lite
--- Description:
--- Ported from:
--- https://git.astron.nl/desp/gemini/-/blob/master/libraries/base/axi4/src/vhdl/axi4_lite_pkg.vhd
--------------------------------------------------------------------------------
-
-LIBRARY IEEE, common_lib;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE std.textio.ALL;
-USE IEEE.STD_LOGIC_TEXTIO.ALL;
-USE common_lib.common_pkg.ALL;
-USE common_lib.common_mem_pkg.ALL;
-
-PACKAGE axi4_lite_pkg IS
-
- ------------------------------------------------------------------------------
- -- Simple AXI4 lite memory access (for MM control interface)
- ------------------------------------------------------------------------------
- CONSTANT c_axi4_lite_address_w : NATURAL := 32;
- CONSTANT c_axi4_lite_data_w : NATURAL := 32;
- CONSTANT c_axi4_lite_prot_w : NATURAL := 3;
- CONSTANT c_axi4_lite_resp_w : NATURAL := 2;
-
-
- TYPE t_axi4_lite_copi IS RECORD -- Controller Out Peripheral In
- -- write address channel
- awaddr : std_logic_vector(c_axi4_lite_address_w-1 downto 0); -- write address
- awprot : std_logic_vector(c_axi4_lite_prot_w-1 downto 0); -- access permission for write
- awvalid : std_logic; -- write address valid
- -- write data channel
- wdata : std_logic_vector(c_axi4_lite_data_w-1 downto 0); -- write data
- wstrb : std_logic_vector((c_axi4_lite_data_w/c_byte_w)-1 downto 0); -- write strobes
- wvalid : std_logic; -- write valid
- -- write response channel
- bready : std_logic; -- response ready
- -- read address channel
- araddr : std_logic_vector(c_axi4_lite_address_w-1 downto 0); -- read address
- arprot : std_logic_vector(c_axi4_lite_prot_w-1 downto 0); -- access permission for read
- arvalid : std_logic; -- read address valid
- -- read data channel
- rready : std_logic; -- read ready
- END RECORD;
-
- TYPE t_axi4_lite_cipo IS RECORD -- Controller In Peripheral Out
- -- write_address channel
- awready : std_logic; -- write address ready
- -- write data channel
- wready : std_logic; -- write ready
- -- write response channel
- bresp : std_logic_vector(c_axi4_lite_resp_w-1 downto 0); -- write response
- bvalid : std_logic; -- write response valid
- -- read address channel
- arready : std_logic; -- read address ready
- -- read data channel
- rdata : std_logic_vector(c_axi4_lite_data_w-1 downto 0); -- read data
- rresp : std_logic_vector(c_axi4_lite_resp_w-1 downto 0); -- read response
- rvalid : std_logic; -- read valid
- END RECORD;
-
- CONSTANT c_axi4_lite_copi_rst : t_axi4_lite_copi := ((OTHERS=>'0'), (OTHERS=>'0'), '0', (OTHERS=>'0'), (OTHERS=>'0'), '0', '0', (OTHERS=>'0'), (OTHERS=>'0'), '0', '0');
- CONSTANT c_axi4_lite_cipo_rst : t_axi4_lite_cipo := ('0', '0', (OTHERS=>'0'), '0', '0', (OTHERS=>'0'), (OTHERS=>'0'), '0');
-
- -- Multi port array for MM records
- TYPE t_axi4_lite_cipo_arr IS ARRAY (INTEGER RANGE <>) OF t_axi4_lite_cipo;
- TYPE t_axi4_lite_copi_arr IS ARRAY (INTEGER RANGE <>) OF t_axi4_lite_copi;
-
- CONSTANT c_axi4_lite_resp_okay : STD_LOGIC_VECTOR(c_axi4_lite_resp_w-1 DOWNTO 0) := "00"; -- normal access success
- CONSTANT c_axi4_lite_resp_exokay : STD_LOGIC_VECTOR(c_axi4_lite_resp_w-1 DOWNTO 0) := "01"; -- exclusive access okay
- CONSTANT c_axi4_lite_resp_slverr : STD_LOGIC_VECTOR(c_axi4_lite_resp_w-1 DOWNTO 0) := "10"; -- peripheral error
- CONSTANT c_axi4_lite_resp_decerr : STD_LOGIC_VECTOR(c_axi4_lite_resp_w-1 DOWNTO 0) := "11"; -- decode error
-
- -- Functions to convert axi4-lite to MM.
- FUNCTION func_axi4_lite_to_mm_copi(axi4_copi : t_axi4_lite_copi) RETURN t_mem_copi;
- FUNCTION func_axi4_lite_to_mm_cipo(axi4_cipo : t_axi4_lite_cipo) RETURN t_mem_cipo;
-
- -- Functions to convert MM to axi4-lite.
- FUNCTION func_axi4_lite_from_mm_copi(mm_copi : t_mem_copi) RETURN t_axi4_lite_copi;
- FUNCTION func_axi4_lite_from_mm_cipo(mm_cipo : t_mem_cipo; bvalid : STD_LOGIC) RETURN t_axi4_lite_cipo;
-
-END axi4_lite_pkg;
-
-PACKAGE BODY axi4_lite_pkg IS
-
- FUNCTION func_axi4_lite_to_mm_copi(axi4_copi : t_axi4_lite_copi) RETURN t_mem_copi IS
- VARIABLE v_mm_copi : t_mem_copi := c_mem_copi_rst;
- BEGIN
- IF axi4_copi.awvalid = '1' THEN
- v_mm_copi.address := "00" & axi4_copi.awaddr(c_axi4_lite_address_w-1 DOWNTO 2); -- convert byte addressed to word addressed.
- ELSE
- v_mm_copi.address := "00" & axi4_copi.araddr(c_axi4_lite_address_w-1 DOWNTO 2); -- convert byte addressed to word addressed.
- END IF;
- v_mm_copi.wrdata(c_axi4_lite_data_w-1 DOWNTO 0) := axi4_copi.wdata;
- v_mm_copi.wr := axi4_copi.awvalid;
- v_mm_copi.rd := axi4_copi.arvalid;
- RETURN v_mm_copi;
- END;
-
- FUNCTION func_axi4_lite_to_mm_cipo(axi4_cipo : t_axi4_lite_cipo) RETURN t_mem_cipo IS
- VARIABLE v_mm_cipo : t_mem_cipo := c_mem_cipo_rst;
- BEGIN
- v_mm_cipo.rddata(c_axi4_lite_data_w-1 DOWNTO 0) := axi4_cipo.rdata;
- v_mm_cipo.rdval := axi4_cipo.rvalid;
- v_mm_cipo.waitrequest := NOT (axi4_cipo.awready AND axi4_cipo.wready AND axi4_cipo.arready);
- RETURN v_mm_cipo;
- END;
-
- FUNCTION func_axi4_lite_from_mm_copi(mm_copi : t_mem_copi) RETURN t_axi4_lite_copi IS
- VARIABLE v_axi4_copi : t_axi4_lite_copi := c_axi4_lite_copi_rst;
- BEGIN
- v_axi4_copi.awaddr := mm_copi.address(c_axi4_lite_address_w-3 DOWNTO 0) & "00"; -- convert word addressed to byte addressed.
- v_axi4_copi.awprot := (OTHERS => '0');
- v_axi4_copi.awvalid := mm_copi.wr;
- v_axi4_copi.wdata := mm_copi.wrdata(c_axi4_lite_data_w-1 DOWNTO 0);
- v_axi4_copi.wstrb := (OTHERS => '1'); -- Either ignored or all bytes selected.
- v_axi4_copi.wvalid := mm_copi.wr;
- v_axi4_copi.bready := '1'; -- Unsupported by MM, assuming always ready.
- v_axi4_copi.araddr := mm_copi.address(c_axi4_lite_address_w-3 DOWNTO 0) & "00"; -- convert word addressed to byte addressed.
- v_axi4_copi.arprot := (OTHERS => '0');
- v_axi4_copi.arvalid := mm_copi.rd;
- v_axi4_copi.rready := '1'; -- Unsupported by MM, assuming always ready.
- RETURN v_axi4_copi;
- END;
-
- FUNCTION func_axi4_lite_from_mm_cipo(mm_cipo : t_mem_cipo; bvalid : STD_LOGIC) RETURN t_axi4_lite_cipo IS
- VARIABLE v_axi4_cipo : t_axi4_lite_cipo := c_axi4_lite_cipo_rst;
- BEGIN
- v_axi4_cipo.awready := NOT mm_cipo.waitrequest;
- v_axi4_cipo.wready := NOT mm_cipo.waitrequest;
- v_axi4_cipo.bresp := c_axi4_lite_resp_okay;
- v_axi4_cipo.bvalid := bvalid;
- v_axi4_cipo.arready := NOT mm_cipo.waitrequest;
- v_axi4_cipo.rdata := mm_cipo.rddata(c_axi4_lite_data_w-1 DOWNTO 0);
- v_axi4_cipo.rresp := c_axi4_lite_resp_okay;
- v_axi4_cipo.rvalid := mm_cipo.rdval;
- RETURN v_axi4_cipo;
- END;
-
-END axi4_lite_pkg;
->>>>>>> master
+end axi4_lite_pkg;
\ No newline at end of file
diff --git a/libraries/base/axi4/src/vhdl/axi4_stream_dp_bridge.vhd b/libraries/base/axi4/src/vhdl/axi4_stream_dp_bridge.vhd
index 7c3cd30902e3783bf579cbbdd2950dd663d322bd..3e7f15ec535ade746cebb3af500ece6338d14083 100644
--- a/libraries/base/axi4/src/vhdl/axi4_stream_dp_bridge.vhd
+++ b/libraries/base/axi4/src/vhdl/axi4_stream_dp_bridge.vhd
@@ -194,4 +194,4 @@ begin
src_in => dp_out_siso
);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd b/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd
index e8dee42daa763cea60bdcec10c0cb1b90dabd437..b099f464624c175339d60623d76b2b53bff1ec92 100644
--- a/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd
+++ b/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd
@@ -384,7 +384,7 @@ package body axi4_stream_pkg is
for I in axi4'range loop
if mask(I) = '1' then
v_any := '1';
- if str ="READY " then v_vec(I) := axi4(I).tready;
+ if str ="READY " then v_vec(I) := axi4(I).tready;
else report "Error in func_axi4_stream_arr_and for t_axi4_siso_arr";
end if;
end if;
@@ -405,7 +405,7 @@ package body axi4_stream_pkg is
for I in axi4'range loop
if mask(I) = '1' then
v_any := '1';
- if str ="VALID " then v_vec(I) := axi4(I).tvalid;
+ if str ="VALID " then v_vec(I) := axi4(I).tvalid;
else report "Error in func_axi4_stream_arr_and for t_axi4_sosi_arr";
end if;
end if;
@@ -438,7 +438,7 @@ package body axi4_stream_pkg is
for I in axi4'range loop
if mask(I) = '1' then
v_any := '1';
- if str ="READY " then v_vec(I) := axi4(I).tready;
+ if str ="READY " then v_vec(I) := axi4(I).tready;
else report "Error in func_axi4_stream_arr_or for t_axi4_siso_arr";
end if;
end if;
@@ -459,7 +459,7 @@ package body axi4_stream_pkg is
for I in axi4'range loop
if mask(I) = '1' then
v_any := '1';
- if str ="VALID " then v_vec(I) := axi4(I).tvalid;
+ if str ="VALID " then v_vec(I) := axi4(I).tvalid;
else report "Error in func_axi4_stream_arr_or for t_axi4_sosi_arr";
end if;
end if;
@@ -491,7 +491,7 @@ package body axi4_stream_pkg is
variable v_slv : std_logic_vector(axi4'range) := slv; -- map to ensure same range as for axi4
begin
for I in axi4'range loop
- if str ="READY " then v_axi4(I).tready := v_slv(I);
+ if str ="READY " then v_axi4(I).tready := v_slv(I);
else report "Error in func_axi4_stream_arr_set for t_axi4_siso_arr";
end if;
end loop;
@@ -503,7 +503,7 @@ package body axi4_stream_pkg is
variable v_slv : std_logic_vector(axi4'range) := slv; -- map to ensure same range as for axi4
begin
for I in axi4'range loop
- if str ="VALID " then v_axi4(I).tvalid := v_slv(I);
+ if str ="VALID " then v_axi4(I).tvalid := v_slv(I);
else report "Error in func_axi4_stream_arr_set for t_axi4_sosi_arr";
end if;
end loop;
@@ -526,7 +526,7 @@ package body axi4_stream_pkg is
variable v_ctrl : std_logic_vector(axi4'range);
begin
for I in axi4'range loop
- if str ="READY " then v_ctrl(I) := axi4(I).tready;
+ if str ="READY " then v_ctrl(I) := axi4(I).tready;
else report "Error in func_axi4_stream_arr_get for t_axi4_siso_arr";
end if;
end loop;
@@ -537,7 +537,7 @@ package body axi4_stream_pkg is
variable v_ctrl : std_logic_vector(axi4'range);
begin
for I in axi4'range loop
- if str ="VALID " then v_ctrl(I) := axi4(I).tvalid;
+ if str ="VALID " then v_ctrl(I) := axi4(I).tvalid;
else report "Error in func_axi4_stream_arr_get for t_axi4_sosi_arr";
end if;
end loop;
@@ -777,4 +777,4 @@ package body axi4_stream_pkg is
return(to_uvec(v_count, c_dp_stream_empty_w));
end func_axi4_stream_tkeep_to_dp_empty;
-end axi4_stream_pkg;
+end axi4_stream_pkg;
\ No newline at end of file
diff --git a/libraries/base/axi4/tb/vhdl/tb_axi4_stream_dp_bridge.vhd b/libraries/base/axi4/tb/vhdl/tb_axi4_stream_dp_bridge.vhd
index 6a064de793db5e96efa0e8afebfaf5c3c68edb2a..73895d772a042846335a9d55b4bf7884f6894825 100644
--- a/libraries/base/axi4/tb/vhdl/tb_axi4_stream_dp_bridge.vhd
+++ b/libraries/base/axi4/tb/vhdl/tb_axi4_stream_dp_bridge.vhd
@@ -75,7 +75,7 @@ architecture tb of tb_axi4_stream_dp_bridge is
signal cnt_en : std_logic;
signal tx_data : t_dp_data_arr(0 to g_dp_rl + c_tx_void);
- signal tx_val : std_logic_vector(0 TO g_dp_rl + c_tx_void);
+ signal tx_val : std_logic_vector(0 to g_dp_rl + c_tx_void);
signal in_ready : std_logic;
signal in_data : std_logic_vector(c_dp_data_w - 1 downto 0);
@@ -96,7 +96,7 @@ architecture tb of tb_axi4_stream_dp_bridge is
signal dut_out_sosi : t_dp_sosi := c_dp_sosi_rst;
signal out_ready : std_logic;
- signal prev_out_ready : std_logic_vector(0 TO g_dp_rl);
+ signal prev_out_ready : std_logic_vector(0 to g_dp_rl);
signal out_data : std_logic_vector(c_dp_data_w - 1 downto 0);
signal out_empty : std_logic_vector(c_dp_empty_w - 1 downto 0);
signal out_channel : std_logic_vector(c_dp_data_w - 1 downto 0);
diff --git a/libraries/base/common/src/vhdl/common_accumulate.vhd b/libraries/base/common/src/vhdl/common_accumulate.vhd
index b0fbd94d062c194eaf99195193918e30457093bf..86b7a5144683060e54e76bdbe0dd577826454a12 100644
--- a/libraries/base/common/src/vhdl/common_accumulate.vhd
+++ b/libraries/base/common/src/vhdl/common_accumulate.vhd
@@ -63,14 +63,14 @@ begin
if sload = '1' then
result <= (others => '0');
if in_val = '1' then
- if g_representation ="signed " then
+ if g_representation ="signed " then
result <= RESIZE_SVEC(in_dat, c_acc_w);
else
result <= RESIZE_UVEC(in_dat, c_acc_w);
end if;
end if;
elsif in_val = '1' then
- if g_representation ="signed " then
+ if g_representation ="signed " then
result <= std_logic_vector( signed(result) + signed(RESIZE_SVEC(in_dat, c_acc_w)));
else
result <= std_logic_vector(unsigned(result) + unsigned(RESIZE_UVEC(in_dat, c_acc_w)));
diff --git a/libraries/base/common/src/vhdl/common_add_sub.vhd b/libraries/base/common/src/vhdl/common_add_sub.vhd
index 99120e94b56dffc727a79bc6d5bf145ff4825853..83bb11742d6f3888f244a2f6e6f0f0fd7a7b01a4 100644
--- a/libraries/base/common/src/vhdl/common_add_sub.vhd
+++ b/libraries/base/common/src/vhdl/common_add_sub.vhd
@@ -56,7 +56,7 @@ architecture str of common_add_sub is
begin
- in_add <= '1' when g_direction ="ADD " or (g_direction ="BOTH " and sel_add = '1') else '0';
+ in_add <= '1' when g_direction ="ADD " or (g_direction ="BOTH " and sel_add = '1') else '0';
no_input_reg : if g_pipeline_input = 0 generate -- wired input
in_a_p <= in_a;
diff --git a/libraries/base/common/src/vhdl/common_adder_tree_a_recursive.vhd b/libraries/base/common/src/vhdl/common_adder_tree_a_recursive.vhd
index b92f0aa939361a371f21391ecc69efc4dfd66b2e..ff431c5670da265f10d87e3aa7c59edb17652527 100644
--- a/libraries/base/common/src/vhdl/common_adder_tree_a_recursive.vhd
+++ b/libraries/base/common/src/vhdl/common_adder_tree_a_recursive.vhd
@@ -182,6 +182,6 @@ begin
);
end generate;
- sum <= RESIZE_SVEC(result, g_sum_w) when g_representation ="signed " else RESIZE_UVEC(result, g_sum_w);
+ sum <= RESIZE_SVEC(result, g_sum_w) when g_representation ="signed " else RESIZE_UVEC(result, g_sum_w);
end recursive;
\ No newline at end of file
diff --git a/libraries/base/common/src/vhdl/common_adder_tree_a_str.vhd b/libraries/base/common/src/vhdl/common_adder_tree_a_str.vhd
index 806295b4a5e394e842731352951c02e150bdefea..6dd32b855e1c19c728bea92d073b53408dbc4c3a 100644
--- a/libraries/base/common/src/vhdl/common_adder_tree_a_str.vhd
+++ b/libraries/base/common/src/vhdl/common_adder_tree_a_str.vhd
@@ -131,7 +131,7 @@ begin
end generate;
-- Map final sum to larger output vector using sign extension or to smaller width output vector preserving the LS part
- sum <= RESIZE_SVEC(adds(c_nof_stages - 1)(c_sum_w - 1 downto 0), g_sum_w) when g_representation ="signed " else
+ sum <= RESIZE_SVEC(adds(c_nof_stages - 1)(c_sum_w - 1 downto 0), g_sum_w) when g_representation ="signed " else
RESIZE_UVEC(adds(c_nof_stages - 1)(c_sum_w - 1 downto 0), g_sum_w);
end generate; -- gen_tree
diff --git a/libraries/base/common/src/vhdl/common_async.vhd b/libraries/base/common/src/vhdl/common_async.vhd
index 8043970631ba477afeab991c171a630b8cf7f56d..786aff76b4119bd527f53a6a1bfd8cbdf1ac75ba 100644
--- a/libraries/base/common/src/vhdl/common_async.vhd
+++ b/libraries/base/common/src/vhdl/common_async.vhd
@@ -44,7 +44,7 @@ end;
architecture rtl of common_async is
- signal din_meta : std_logic_vector(0 TO g_delay_len - 1) := (others => g_rst_level);
+ signal din_meta : std_logic_vector(0 to g_delay_len - 1) := (others => g_rst_level);
-- Synthesis constraint to ensure that register is kept in this instance region
attribute preserve : boolean;
diff --git a/libraries/base/common/src/vhdl/common_clip.vhd b/libraries/base/common/src/vhdl/common_clip.vhd
index 22e45355a5ff8aa4daace8db5e6e33a4b67c5953..ad2f4d05a9e16269e18a12649853fb10ec7486d0 100644
--- a/libraries/base/common/src/vhdl/common_clip.vhd
+++ b/libraries/base/common/src/vhdl/common_clip.vhd
@@ -81,7 +81,7 @@ begin
nxt_clip_dat <= in_dat;
nxt_clip_ovr <= '0';
if enable = '1' then
- if g_representation ="signed " then
+ if g_representation ="signed " then
if signed(in_dat) > c_s_full_scale then
nxt_clip_dat <= std_logic_vector(RESIZE_NUM( c_s_full_scale, c_dat_w));
nxt_clip_ovr <= '1';
diff --git a/libraries/base/common/src/vhdl/common_debounce.vhd b/libraries/base/common/src/vhdl/common_debounce.vhd
index db0897f63522482a602cfa38a05a704b798b3549..850ce74fc0fe1135adbf04368073d9e105fb5970 100644
--- a/libraries/base/common/src/vhdl/common_debounce.vhd
+++ b/libraries/base/common/src/vhdl/common_debounce.vhd
@@ -57,7 +57,7 @@ architecture rtl of common_debounce is
signal cnt_en : std_logic;
signal stable_d : std_logic;
- signal d_dly : std_logic_vector(0 TO g_delay_len - 1) := (others => g_init_level);
+ signal d_dly : std_logic_vector(0 to g_delay_len - 1) := (others => g_init_level);
signal d_reg : std_logic := g_init_level;
signal prev_d : std_logic := g_init_level;
signal i_q_out : std_logic := g_init_level;
@@ -87,17 +87,17 @@ begin
stable_d <= '1' when unsigned(cnt) >= g_latency else '0';
cnt_en <= not stable_d;
- gen_both : if g_type ="BOTH " generate
+ gen_both : if g_type ="BOTH " generate
cnt_clr <= d_reg xor prev_d;
nxt_q_out <= prev_d when stable_d = '1' else i_q_out;
end generate;
- gen_high : if g_type ="HIGH " generate
+ gen_high : if g_type ="HIGH " generate
cnt_clr <= not d_reg;
nxt_q_out <= prev_d when stable_d = '1' else '0';
end generate;
- gen_low : if g_type ="LOW " generate
+ gen_low : if g_type ="LOW " generate
cnt_clr <= d_reg;
nxt_q_out <= prev_d when stable_d = '1' else '1';
end generate;
diff --git a/libraries/base/common/src/vhdl/common_duty_cycle.vhd b/libraries/base/common/src/vhdl/common_duty_cycle.vhd
index d3055550286b1528c233ab7c98dbb87124a43f31..3a6b04dda91a3245ac9d9c1a7725d73c7db47800 100644
--- a/libraries/base/common/src/vhdl/common_duty_cycle.vhd
+++ b/libraries/base/common/src/vhdl/common_duty_cycle.vhd
@@ -123,4 +123,4 @@ begin
dc_out <= r.dc_pulse when dc_out_en = '1' else g_dis_lvl when rst = '0' else g_rst_lvl;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/base/common/src/vhdl/common_evt.vhd b/libraries/base/common/src/vhdl/common_evt.vhd
index 40b1e7812aad5ebbd02859e2b1ea36bff561675d..e13a63f69bef089ed6906c3f95828f3175b16404 100644
--- a/libraries/base/common/src/vhdl/common_evt.vhd
+++ b/libraries/base/common/src/vhdl/common_evt.vhd
@@ -60,9 +60,9 @@ begin
end process;
-- Detect input event
- gen_rising : if g_evt_type ="RISING " generate sig_evt <= in_sig and not in_sig_prev; end generate;
- gen_falling : if g_evt_type ="FALLING " generate sig_evt <= not in_sig and in_sig_prev; end generate;
- gen_both : if g_evt_type ="BOTH " generate sig_evt <= in_sig xor in_sig_prev; end generate;
+ gen_rising : if g_evt_type ="RISING " generate sig_evt <= in_sig and not in_sig_prev; end generate;
+ gen_falling : if g_evt_type ="FALLING " generate sig_evt <= not in_sig and in_sig_prev; end generate;
+ gen_both : if g_evt_type ="BOTH " generate sig_evt <= in_sig xor in_sig_prev; end generate;
sig_evt_n <= not sig_evt;
diff --git a/libraries/base/common/src/vhdl/common_field_pkg.vhd b/libraries/base/common/src/vhdl/common_field_pkg.vhd
index 5a65a9b485e1c0339a3b7d9c09d72a92acd9b4ba..0ff6b9a72cb5cb0abe87975f464e61d7be5086f0 100644
--- a/libraries/base/common/src/vhdl/common_field_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_field_pkg.vhd
@@ -107,7 +107,7 @@ package body common_field_pkg is
variable v_slv_out : std_logic_vector(field_slv_out_len(field_arr) - 1 downto 0);
begin
for f in 0 to field_arr'high loop
- if field_arr(f).mode ="RW " then
+ if field_arr(f).mode ="RW " then
v_slv_out( field_hi(field_arr, field_arr(f).name) downto field_lo(field_arr, field_arr(f).name)) := field_arr(f).default(field_arr(f).size - 1 downto 0);
end if;
end loop;
@@ -213,7 +213,7 @@ package body common_field_pkg is
variable v_len : natural := 0;
begin
for f in 0 to field_arr'high loop
- if field_arr(f).mode ="RO " then
+ if field_arr(f).mode ="RO " then
v_len := v_len + field_arr(f).size;
end if;
end loop;
@@ -225,7 +225,7 @@ package body common_field_pkg is
variable v_len : natural := 0;
begin
for f in 0 to field_arr'high loop
- if field_arr(f).mode ="RW " then
+ if field_arr(f).mode ="RW " then
v_len := v_len + field_arr(f).size;
end if;
end loop;
@@ -271,7 +271,7 @@ package body common_field_pkg is
begin
for f in 0 to field_arr'high loop
-- Only extract the fields that are outputs
- if field_arr(f).mode ="RW " then
+ if field_arr(f).mode ="RW " then
-- Extract the field
v_slv_out( field_hi(field_arr, field_arr(f).name) downto field_lo(field_arr, field_arr(f).name)) := word_arr( v_word_cnt * word_w + field_arr(f).size - 1 downto v_word_cnt * word_w);
end if;
@@ -290,7 +290,7 @@ package body common_field_pkg is
v_word_arr := word_arr_in;
-- Now re-assign the words that need to be read back from word_arr_out
for f in 0 to field_arr'high loop
- if field_arr(f).mode ="RW " then
+ if field_arr(f).mode ="RW " then
v_word_arr( v_word_cnt * word_w + field_arr(f).size - 1 downto v_word_cnt * word_w) := word_arr_out( v_word_cnt * word_w + field_arr(f).size - 1 downto v_word_cnt * word_w);
end if;
-- Calculate the correct word offset for the next field
diff --git a/libraries/base/common/src/vhdl/common_flank_to_pulse.vhd b/libraries/base/common/src/vhdl/common_flank_to_pulse.vhd
index a0d6737630680fcb1516464b22a35f3a6edbdeb2..442e4f1c6a2a6057954b76e14e7b084221dbc985 100644
--- a/libraries/base/common/src/vhdl/common_flank_to_pulse.vhd
+++ b/libraries/base/common/src/vhdl/common_flank_to_pulse.vhd
@@ -50,5 +50,4 @@ begin
pulse_out <= flank_in and not(flank_in_dly);
-end str;
-
+end str;
\ No newline at end of file
diff --git a/libraries/base/common/src/vhdl/common_interface_layers_pkg.vhd b/libraries/base/common/src/vhdl/common_interface_layers_pkg.vhd
index 06088872c09e01e6958fe78d4478a2d364933c27..0138e26367525e34dfd59d055025abe1bb6778cc 100644
--- a/libraries/base/common/src/vhdl/common_interface_layers_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_interface_layers_pkg.vhd
@@ -150,4 +150,4 @@ package body common_interface_layers_pkg is
return ctrl_out;
end;
-end common_interface_layers_pkg;
+end common_interface_layers_pkg;
\ No newline at end of file
diff --git a/libraries/base/common/src/vhdl/common_math_pkg.vhd b/libraries/base/common/src/vhdl/common_math_pkg.vhd
index a4299a95cd00e769c179d75ea14c96ceccf85802..8b103986b96248914fb2131db784b4007ade4b4c 100644
--- a/libraries/base/common/src/vhdl/common_math_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_math_pkg.vhd
@@ -194,4 +194,4 @@ package body common_math_pkg is
end;
-end common_math_pkg;
+end common_math_pkg;
\ No newline at end of file
diff --git a/libraries/base/common/src/vhdl/common_mem_pkg.vhd b/libraries/base/common/src/vhdl/common_mem_pkg.vhd
index b12f0ccdd1d83d983e49927b3eada69dd9fceada..4de0f8a9a9c88d50b53fcafd6e4e6b55c56072d0 100644
--- a/libraries/base/common/src/vhdl/common_mem_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_mem_pkg.vhd
@@ -194,7 +194,7 @@ package common_mem_pkg is
constant c_mem_reg_rd_latency : natural := 1;
constant c_mem_reg : t_c_mem := (c_mem_reg_rd_latency, 1, 32, 1, 'x');
- constant c_mem_reg_init_w : natural := 1 *256 * 32; -- >= largest expected value of dat_w*nof_dat (256 * 32 bit = 1k byte)
+ constant c_mem_reg_init_w : natural := 1 * 256 * 32; -- >= largest expected value of dat_w*nof_dat (256 * 32 bit = 1k byte)
------------------------------------------------------------------------------
@@ -230,7 +230,7 @@ package body common_mem_pkg is
return v_copi_arr;
end;
- function RESET_MEM_MisO_CTRL(miso : t_mem_miso) return t_mem_miso IS
+ function RESET_MEM_MisO_CTRL(miso : t_mem_miso) return t_mem_miso is
variable v_miso : t_mem_miso := miso;
begin
v_miso.rdval := '0';
diff --git a/libraries/base/common/src/vhdl/common_operation.vhd b/libraries/base/common/src/vhdl/common_operation.vhd
index 03fefd29f0657eb8ddbf8bb346ca8d1d367ceb0f..30f1f2fca0bb929ab41c1bd23a3df9b9eaf9ac7b 100644
--- a/libraries/base/common/src/vhdl/common_operation.vhd
+++ b/libraries/base/common/src/vhdl/common_operation.vhd
@@ -53,12 +53,12 @@ architecture rtl of common_operation is
constant c_umax : std_logic_vector(w - 1 downto 0) := c_slv1(w - 1 downto 0);
begin
-- return don't care default value
- if representation ="signed " then
- if operation ="MIN " then return c_smax; end if;
- if operation ="MAX " then return c_smin; end if;
+ if representation ="signed " then
+ if operation ="MIN " then return c_smax; end if;
+ if operation ="MAX " then return c_smin; end if;
else
- if operation ="MIN " then return c_umax; end if;
- if operation ="MAX " then return c_umin; end if;
+ if operation ="MIN " then return c_umax; end if;
+ if operation ="MAX " then return c_umin; end if;
end if;
assert TRUE report "Operation not supported" severity FAILURE;
return c_umin; -- void return statement to avoid compiler warning on missing return
@@ -66,12 +66,12 @@ architecture rtl of common_operation is
function func_operation(operation, representation : string; a, b : std_logic_vector) return std_logic_vector is
begin
- if representation ="signed " then
- if operation ="MIN " then if signed(a) < signed(b) then return a; else return b; end if; end if;
- if operation ="MAX " then if signed(a) > signed(b) then return a; else return b; end if; end if;
+ if representation ="signed " then
+ if operation ="MIN " then if signed(a) < signed(b) then return a; else return b; end if; end if;
+ if operation ="MAX " then if signed(a) > signed(b) then return a; else return b; end if; end if;
else
- if operation ="MIN " then if unsigned(a) < unsigned(b) then return a; else return b; end if; end if;
- if operation ="MAX " then if unsigned(a) > unsigned(b) then return a; else return b; end if; end if;
+ if operation ="MIN " then if unsigned(a) < unsigned(b) then return a; else return b; end if; end if;
+ if operation ="MAX " then if unsigned(a) > unsigned(b) then return a; else return b; end if; end if;
end if;
assert TRUE report "Operation not supported" severity FAILURE;
return a; -- void return statement to avoid compiler warning on missing return
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd b/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd
index b1ca7b2080a26b710a16cb7ee0315579be02e801..4dcbd88c873be4efde278f41f7f4d396a615dea3 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd
@@ -139,17 +139,17 @@ architecture rtl of common_paged_ram_crw_crw is
-- >>> Access control
-- g_str = "use_mux" :
- signal page_wr_en_a : std_logic_vector(0 TO g_nof_pages - 1);
+ signal page_wr_en_a : std_logic_vector(0 to g_nof_pages - 1);
signal page_wr_dat_a : t_data_arr(0 to g_nof_pages - 1);
- signal page_rd_en_a : std_logic_vector(0 TO g_nof_pages - 1);
+ signal page_rd_en_a : std_logic_vector(0 to g_nof_pages - 1);
signal page_rd_dat_a : t_data_arr(0 to g_nof_pages - 1);
- signal page_rd_val_a : std_logic_vector(0 TO g_nof_pages - 1);
+ signal page_rd_val_a : std_logic_vector(0 to g_nof_pages - 1);
- signal page_wr_en_b : std_logic_vector(0 TO g_nof_pages - 1);
+ signal page_wr_en_b : std_logic_vector(0 to g_nof_pages - 1);
signal page_wr_dat_b : t_data_arr(0 to g_nof_pages - 1);
- signal page_rd_en_b : std_logic_vector(0 TO g_nof_pages - 1);
+ signal page_rd_en_b : std_logic_vector(0 to g_nof_pages - 1);
signal page_rd_dat_b : t_data_arr(0 to g_nof_pages - 1);
- signal page_rd_val_b : std_logic_vector(0 TO g_nof_pages - 1);
+ signal page_rd_val_b : std_logic_vector(0 to g_nof_pages - 1);
-- g_str = "use_adr" :
signal mem_adr_a : std_logic_vector(c_mem_addr_w - 1 downto 0);
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_ww_rr.vhd b/libraries/base/common/src/vhdl/common_paged_ram_ww_rr.vhd
index 798b4b6360d622f99ff313e0297aeb9784896f7d..aa5cac43a9d87ed92e4acb0c0416c9152efe29b6 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_ww_rr.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_ww_rr.vhd
@@ -90,8 +90,8 @@ architecture rtl of common_paged_ram_ww_rr is
-- Page select control
signal page_sel : std_logic;
signal nxt_page_sel : std_logic;
- signal page_sel_dly : std_logic_vector(0 TO c_sel_latency - 1);
- signal nxt_page_sel_dly : std_logic_vector(0 TO c_sel_latency - 1);
+ signal page_sel_dly : std_logic_vector(0 to c_sel_latency - 1);
+ signal nxt_page_sel_dly : std_logic_vector(0 to c_sel_latency - 1);
signal page_sel_in : std_logic;
signal page_sel_out : std_logic;
@@ -101,14 +101,14 @@ architecture rtl of common_paged_ram_ww_rr is
signal nxt_page_wr_dat_b : std_logic_vector(g_data_w - 1 downto 0);
signal page_wr_dat_a : std_logic_vector(g_data_w - 1 downto 0);
signal page_wr_dat_b : std_logic_vector(g_data_w - 1 downto 0);
- signal nxt_page_wr_en_a : std_logic_vector(0 TO c_nof_pages - 1);
- signal nxt_page_wr_en_b : std_logic_vector(0 TO c_nof_pages - 1);
- signal page_wr_en_a : std_logic_vector(0 TO c_nof_pages - 1);
- signal page_wr_en_b : std_logic_vector(0 TO c_nof_pages - 1);
- signal nxt_page_rd_en_a : std_logic_vector(0 TO c_nof_pages - 1);
- signal nxt_page_rd_en_b : std_logic_vector(0 TO c_nof_pages - 1);
- signal page_rd_en_a : std_logic_vector(0 TO c_nof_pages - 1);
- signal page_rd_en_b : std_logic_vector(0 TO c_nof_pages - 1);
+ signal nxt_page_wr_en_a : std_logic_vector(0 to c_nof_pages - 1);
+ signal nxt_page_wr_en_b : std_logic_vector(0 to c_nof_pages - 1);
+ signal page_wr_en_a : std_logic_vector(0 to c_nof_pages - 1);
+ signal page_wr_en_b : std_logic_vector(0 to c_nof_pages - 1);
+ signal nxt_page_rd_en_a : std_logic_vector(0 to c_nof_pages - 1);
+ signal nxt_page_rd_en_b : std_logic_vector(0 to c_nof_pages - 1);
+ signal page_rd_en_a : std_logic_vector(0 to c_nof_pages - 1);
+ signal page_rd_en_b : std_logic_vector(0 to c_nof_pages - 1);
signal nxt_page_adr_a : t_addr_arr(0 to c_nof_pages - 1);
signal nxt_page_adr_b : t_addr_arr(0 to c_nof_pages - 1);
signal page_adr_a : t_addr_arr(0 to c_nof_pages - 1);
@@ -116,9 +116,9 @@ architecture rtl of common_paged_ram_ww_rr is
-- . output
signal page_rd_dat_a : t_data_arr(0 to c_nof_pages - 1);
- signal page_rd_val_a : std_logic_vector(0 TO c_nof_pages - 1);
+ signal page_rd_val_a : std_logic_vector(0 to c_nof_pages - 1);
signal page_rd_dat_b : t_data_arr(0 to c_nof_pages - 1);
- signal page_rd_val_b : std_logic_vector(0 TO c_nof_pages - 1);
+ signal page_rd_val_b : std_logic_vector(0 to c_nof_pages - 1);
signal nxt_rd_dat_a : std_logic_vector(g_data_w - 1 downto 0);
signal nxt_rd_val_a : std_logic;
diff --git a/libraries/base/common/src/vhdl/common_pipeline.vhd b/libraries/base/common/src/vhdl/common_pipeline.vhd
index edd93455bb410854d5d7153ee36fb49384bd32e9..8a441547c1a2c99eb907a47e2e9a43b981e53591 100644
--- a/libraries/base/common/src/vhdl/common_pipeline.vhd
+++ b/libraries/base/common/src/vhdl/common_pipeline.vhd
@@ -71,7 +71,7 @@ begin
end generate;
out_dat_p(0) <= RESIZE_SVEC(in_dat, out_dat'length) when g_representation = "signed" else
- RESIZE_UVEC(in_dat, out_dat'length) when g_representation ="unsigned ";
+ RESIZE_UVEC(in_dat, out_dat'length) when g_representation ="unsigned ";
out_dat <= out_dat_p(g_pipeline);
diff --git a/libraries/base/common/src/vhdl/common_pipeline_integer.vhd b/libraries/base/common/src/vhdl/common_pipeline_integer.vhd
index a02c0ba9b813cfeb59af3d86c627c0876f630ed3..ec6b23e3bf6ab481d10c69021e924be4d36c50a0 100644
--- a/libraries/base/common/src/vhdl/common_pipeline_integer.vhd
+++ b/libraries/base/common/src/vhdl/common_pipeline_integer.vhd
@@ -49,8 +49,8 @@ architecture str of common_pipeline_integer is
begin
- in_dat_slv <= to_svec(in_dat, g_dat_w) when g_representation ="signed " else to_uvec(in_dat, g_dat_w);
- out_dat <= to_sint(out_dat_slv) when g_representation ="signed " else to_uint(out_dat_slv);
+ in_dat_slv <= to_svec(in_dat, g_dat_w) when g_representation ="signed " else to_uvec(in_dat, g_dat_w);
+ out_dat <= to_sint(out_dat_slv) when g_representation ="signed " else to_uint(out_dat_slv);
u_int : entity work.common_pipeline
generic map (
diff --git a/libraries/base/common/src/vhdl/common_pkg.vhd b/libraries/base/common/src/vhdl/common_pkg.vhd
index e6716dc8582813385c3cd2560642d13746ee1961..497894d715e2d20fa9b93dfccd41140f8d057720 100644
--- a/libraries/base/common/src/vhdl/common_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_pkg.vhd
@@ -410,10 +410,10 @@ package common_pkg is
function to_uvec(udec : real; w, resolution_w : integer) return std_logic_vector; -- REAL >= 0 to unsigned SLV fixed point number
function to_svec(sdec : real; w, resolution_w : integer) return std_logic_vector; -- REAL to signed SLV fixed point number
- function to_ureal(uvec : std_logic_vector) return REAL; -- convert unsigned slv of any length to REAL, fixed point number with resolution = 1
- function to_sreal(svec : std_logic_vector) return REAL; -- convert signed slv of any length to REAL, fixed point number with resolution = 1
- function to_ureal(uvec : std_logic_vector; resolution_w : integer) return REAL; -- convert unsigned fixed point slv of any length, and with resolution of 2**resolution_w, to REAL
- function to_sreal(svec : std_logic_vector; resolution_w : integer) return REAL; -- convert signed fixed point slv of any length, and with resolution of 2**resolution_w, to REAL
+ function to_ureal(uvec : std_logic_vector) return real; -- convert unsigned slv of any length to REAL, fixed point number with resolution = 1
+ function to_sreal(svec : std_logic_vector) return real; -- convert signed slv of any length to REAL, fixed point number with resolution = 1
+ function to_ureal(uvec : std_logic_vector; resolution_w : integer) return real; -- convert unsigned fixed point slv of any length, and with resolution of 2**resolution_w, to REAL
+ function to_sreal(svec : std_logic_vector; resolution_w : integer) return real; -- convert signed fixed point slv of any length, and with resolution of 2**resolution_w, to REAL
-- RESIZE_NUM() original description:
-- The RESIZE for SIGNED in IEEE.NUMERIC_STD extends the sign bit or it keeps the sign bit and LS part. This
@@ -916,18 +916,18 @@ package body common_pkg is
variable v_result : std_logic := '0';
begin
-- default any unused, the stage results will be kept in the LSBits and the last result in bit 0
- if operation ="and " then v_stage_arr := (others => (others => '1'));
- elsif operation ="or " then v_stage_arr := (others => (others => '0'));
- elsif operation ="xor " then v_stage_arr := (others => (others => '0'));
+ if operation ="and " then v_stage_arr := (others => (others => '1'));
+ elsif operation ="or " then v_stage_arr := (others => (others => '0'));
+ elsif operation ="xor " then v_stage_arr := (others => (others => '0'));
else
assert TRUE report "common_pkg: Unsupported vector_tree operation" severity FAILURE;
end if;
v_stage_arr(-1)(c_slv_w - 1 downto 0) := slv; -- any unused input c_w : c_slv_w bits have void default value
for J in 0 to c_nof_stages - 1 loop
for I in 0 to c_w / (2 ** (J + 1)) - 1 loop
- if operation ="and " then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) and v_stage_arr(J - 1)(2 * I + 1);
- elsif operation ="or " then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) or v_stage_arr(J - 1)(2 * I + 1);
- elsif operation ="xor " then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) xor v_stage_arr(J - 1)(2 * I + 1);
+ if operation ="and " then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) and v_stage_arr(J - 1)(2 * I + 1);
+ elsif operation ="or " then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) or v_stage_arr(J - 1)(2 * I + 1);
+ elsif operation ="xor " then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) xor v_stage_arr(J - 1)(2 * I + 1);
end if;
end loop;
end loop;
@@ -1150,7 +1150,7 @@ package body common_pkg is
variable vR : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
vR := R;
for I in vL'range loop
vP(I) := vL(I) + vR(I);
@@ -1163,7 +1163,7 @@ package body common_pkg is
variable vL : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
for I in vL'range loop
vP(I) := vL(I) + R;
end loop;
@@ -1181,7 +1181,7 @@ package body common_pkg is
variable vR : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
vR := R;
for I in vL'range loop
vP(I) := vL(I) - vR(I);
@@ -1195,7 +1195,7 @@ package body common_pkg is
variable vR : t_natural_arr(w - 1 downto 0);
variable vP : t_integer_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
vR := R;
for I in vL'range loop
vP(I) := vL(I) - vR(I);
@@ -1208,7 +1208,7 @@ package body common_pkg is
variable vL : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
for I in vL'range loop
vP(I) := vL(I) - R;
end loop;
@@ -1233,7 +1233,7 @@ package body common_pkg is
variable vR : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
vR := R;
for I in vL'range loop
vP(I) := vL(I) * vR(I);
@@ -1246,7 +1246,7 @@ package body common_pkg is
variable vL : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
for I in vL'range loop
vP(I) := vL(I) * R;
end loop;
@@ -1264,7 +1264,7 @@ package body common_pkg is
variable vR : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
vR := R;
for I in vL'range loop
vP(I) := vL(I) / vR(I);
@@ -1277,7 +1277,7 @@ package body common_pkg is
variable vL : t_natural_arr(w - 1 downto 0);
variable vP : t_natural_arr(w - 1 downto 0);
begin
- vl := L;
+ vl := l;
for I in vL'range loop
vP(I) := vL(I) / R;
end loop;
@@ -1575,7 +1575,7 @@ package body common_pkg is
function sel_n(sel : natural; a, b, c, d, e, f, g, h, i, j : string) return string is begin if sel < 9 then return sel_n(sel, a, b, c, d, e, f, g, h, i); else return j; end if; end;
function array_init(init : std_logic; nof : natural) return std_logic_vector is
- variable v_arr : std_logic_vector(0 TO nof - 1);
+ variable v_arr : std_logic_vector(0 to nof - 1);
begin
for I in v_arr'range loop
v_arr(I) := init;
@@ -2078,7 +2078,7 @@ package body common_pkg is
end if;
end;
- function to_ureal(uvec : std_logic_vector) return REAL is
+ function to_ureal(uvec : std_logic_vector) return real is
constant c_len : natural := uvec'length;
constant c_uvec : std_logic_vector(c_len - 1 downto 0) := uvec;
variable v_real : real := 0.0;
@@ -2092,7 +2092,7 @@ package body common_pkg is
return v_real;
end;
- function to_sreal(svec : std_logic_vector) return REAL is
+ function to_sreal(svec : std_logic_vector) return real is
-- Increase vector length by +1 so the c_uvec can also fit abs() of most negative is -1 * -2**(c_len-1)
constant c_len : natural := svec'length + 1;
constant c_svec : std_logic_vector(c_len - 1 downto 0) := RESIZE_SVEC(svec, c_len);
@@ -2109,14 +2109,14 @@ package body common_pkg is
-- Fixed point format
-- . https://support.astron.nl/confluence/display/L2M/L3+SDP+Decision%3A+Definition+of+fixed+point+numbers
- function to_ureal(uvec : std_logic_vector; resolution_w : integer) return REAL is
+ function to_ureal(uvec : std_logic_vector; resolution_w : integer) return real is
begin
-- First convert as unsigned integer, then scale to real. See TO_SREAL()
-- for interpretation of resolution_w
- return to_ureal(uvec) / 2.0 ** REAL(resolution_w);
+ return to_ureal(uvec) / 2.0 ** real(resolution_w);
end;
- function to_sreal(svec : std_logic_vector; resolution_w : integer) return REAL is
+ function to_sreal(svec : std_logic_vector; resolution_w : integer) return real is
begin
-- First convert as unsigned integer, then scale to real
-- . The resolution_w is the number of bits that LSbit 0 in svec(HIGH-1 DOWNTO 0) is after
@@ -2125,7 +2125,7 @@ package body common_pkg is
-- . resolution_w = 0 : scale by 2**0 = 1, so no scaling and the value is treated as an integer
-- . resolution_w < 0 : scale up
-- . resolution_w > 0 : scale down
- return to_sreal(svec) / 2.0 ** REAL(resolution_w);
+ return to_sreal(svec) / 2.0 ** real(resolution_w);
end;
@@ -2779,7 +2779,7 @@ package body common_pkg is
variable v_b : std_logic_vector(a'length - 1 downto 0);
begin
for I in v_a'range loop
- v_b(a'length - 1 -I) := v_a(I);
+ v_b(a'length - 1 - I) := v_a(I);
end loop;
return v_b;
end;
@@ -2794,7 +2794,7 @@ package body common_pkg is
variable v_b : t_slv_32_arr(a'length - 1 downto 0);
begin
for I in v_a'range loop
- v_b(a'length - 1 -I) := v_a(I);
+ v_b(a'length - 1 - I) := v_a(I);
end loop;
return v_b;
end;
@@ -2804,7 +2804,7 @@ package body common_pkg is
variable v_b : t_integer_arr(a'length - 1 downto 0);
begin
for I in v_a'range loop
- v_b(a'length - 1 -I) := v_a(I);
+ v_b(a'length - 1 - I) := v_a(I);
end loop;
return v_b;
end;
@@ -2814,7 +2814,7 @@ package body common_pkg is
variable v_b : t_natural_arr(a'length - 1 downto 0);
begin
for I in v_a'range loop
- v_b(a'length - 1 -I) := v_a(I);
+ v_b(a'length - 1 - I) := v_a(I);
end loop;
return v_b;
end;
@@ -2824,7 +2824,7 @@ package body common_pkg is
variable v_b : t_nat_natural_arr(a'length - 1 downto 0);
begin
for I in v_a'range loop
- v_b(a'length - 1 -I) := v_a(I);
+ v_b(a'length - 1 - I) := v_a(I);
end loop;
return v_b;
end;
@@ -2884,7 +2884,7 @@ package body common_pkg is
function slice_up(str : string; width : natural; i : natural; pad_char : character) return string is
variable padded_str : string(1 to width) := (others => '0');
begin
- padded_str := pad(str(i * width + 1 to (i +1) * width), width, '0');
+ padded_str := pad(str(i * width + 1 to (i + 1) * width), width, '0');
return padded_str;
end;
@@ -2981,7 +2981,7 @@ package body common_pkg is
-- Get the index K in the select setting array for the reorder2 cell on stage I and row J in a reorder network with N stages
function func_common_reorder2_get_select_index(I, J, N : natural) return integer is
- constant c_nof_reorder2_per_odd_stage : natural := N /2;
+ constant c_nof_reorder2_per_odd_stage : natural := N / 2;
constant c_nof_reorder2_per_even_stage : natural := (N - 1) / 2;
variable v_nof_odd_stages : natural;
variable v_nof_even_stages : natural;
@@ -3103,7 +3103,7 @@ package body common_pkg is
-- Create Pfactor SCLK periods within this DCLK period
SCLK <= '0';
if Pfactor > 1 then
- for I in 0 to 2 * Pfactor - 1 -2 loop
+ for I in 0 to 2 * Pfactor - 1 - 2 loop
wait for v_speriod / 2;
SCLK <= not SCLK;
end loop;
@@ -3115,4 +3115,4 @@ package body common_pkg is
wait;
end proc_common_dclk_generate_sclk;
-end common_pkg;
+end common_pkg;
\ No newline at end of file
diff --git a/libraries/base/common/src/vhdl/common_pulse_delay_reg.vhd b/libraries/base/common/src/vhdl/common_pulse_delay_reg.vhd
index dfcc6535ac61956c7c2f953e36bb456e369b7c2d..89f6c12293e961beb876d751aa2c28f5498b18f3 100644
--- a/libraries/base/common/src/vhdl/common_pulse_delay_reg.vhd
+++ b/libraries/base/common/src/vhdl/common_pulse_delay_reg.vhd
@@ -141,4 +141,4 @@ begin
end generate; -- gen_common_reg_cross_domain
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/base/common/src/vhdl/common_pulse_extend.vhd b/libraries/base/common/src/vhdl/common_pulse_extend.vhd
index 8fb2297fa62066d1c057d06fab3aa8f4f0565d68..6122bea2b70f95a4e56acddb33db88ffaeb16252 100644
--- a/libraries/base/common/src/vhdl/common_pulse_extend.vhd
+++ b/libraries/base/common/src/vhdl/common_pulse_extend.vhd
@@ -95,4 +95,4 @@ begin
end if;
end process;
-end architecture;
+end architecture;
\ No newline at end of file
diff --git a/libraries/base/common/src/vhdl/common_ram_r_w.vhd b/libraries/base/common/src/vhdl/common_ram_r_w.vhd
index 2a562b40153fd147083679847751d308959728d4..7f4bdacbf76e00e64506c2695b999936934508b6 100644
--- a/libraries/base/common/src/vhdl/common_ram_r_w.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_r_w.vhd
@@ -78,4 +78,4 @@ begin
rd_val_b => rd_val
);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/common/src/vhdl/common_reg_cross_domain.vhd b/libraries/base/common/src/vhdl/common_reg_cross_domain.vhd
index baa2ff26a09e8f3c85cee4c3846464df0eb95dc8..7012cbea091e1217e88710cc10c1fde87838a9b8 100644
--- a/libraries/base/common/src/vhdl/common_reg_cross_domain.vhd
+++ b/libraries/base/common/src/vhdl/common_reg_cross_domain.vhd
@@ -64,7 +64,7 @@ architecture rtl of common_reg_cross_domain is
------------------------------------------------------------------------------
-- in_clk domain
------------------------------------------------------------------------------
- signal reg_new : std_logic_vector(0 TO g_in_new_latency) := (others => '0');
+ signal reg_new : std_logic_vector(0 to g_in_new_latency) := (others => '0');
signal nxt_reg_new : std_logic_vector(reg_new'range);
signal in_buf : std_logic_vector(c_dat'range) := c_dat;
diff --git a/libraries/base/common/src/vhdl/common_requantize.vhd b/libraries/base/common/src/vhdl/common_requantize.vhd
index 368f76de1303dcdc8b19e12bb7528df1ff5eae87..17db12fb1972cd922800cf6dd67f867f40001fdb 100644
--- a/libraries/base/common/src/vhdl/common_requantize.vhd
+++ b/libraries/base/common/src/vhdl/common_requantize.vhd
@@ -137,6 +137,6 @@ begin
-- Output gain
gain_dat(g_out_dat_w + c_gain_w - 1 downto c_gain_w) <= res_dat;
- out_dat <= RESIZE_SVEC(gain_dat, out_dat'length) when g_representation ="signed " else RESIZE_UVEC(gain_dat, out_dat'length);
+ out_dat <= RESIZE_SVEC(gain_dat, out_dat'length) when g_representation ="signed " else RESIZE_UVEC(gain_dat, out_dat'length);
end str;
\ No newline at end of file
diff --git a/libraries/base/common/src/vhdl/common_resize.vhd b/libraries/base/common/src/vhdl/common_resize.vhd
index 9264e35c4444bb725a98a1cffc21e5b6b89d3473..1ce8d619812e9f23721f28cd86089cd9ea2a77e9 100644
--- a/libraries/base/common/src/vhdl/common_resize.vhd
+++ b/libraries/base/common/src/vhdl/common_resize.vhd
@@ -84,7 +84,7 @@ begin
no_clip : if c_clip = FALSE generate
-- Note that g_pipeline_input=0 AND g_clip=FALSE is equivalent to using RESIZE_SVEC or RESIZE_UVEC directly.
- gen_s : if g_representation ="signed " generate
+ gen_s : if g_representation ="signed " generate
-- If g_out_dat_w>g_in_dat_w then IEEE resize extends the sign bit,
-- else IEEE resize preserves the sign bit and keeps the low part.
wrap <= '1' when signed(reg_dat) > c_smax or signed(reg_dat) < c_smin_most else '0';
@@ -92,7 +92,7 @@ begin
res_ovr <= wrap;
end generate;
- gen_u : if g_representation ="unsigned " generate
+ gen_u : if g_representation ="unsigned " generate
-- If g_out_dat_w>g_in_dat_w then IEEE resize sign extends with '0',
-- else IEEE resize keeps the low part.
wrap <= '1' when unsigned(reg_dat) > c_umax else '0';
@@ -102,14 +102,14 @@ begin
end generate;
gen_clip : if c_clip = TRUE generate
- gen_s_clip : if g_representation ="signed " generate
+ gen_s_clip : if g_representation ="signed " generate
clip <= '1' when signed(reg_dat) > c_smax or signed(reg_dat) < c_smin else '0';
sign <= reg_dat(reg_dat'high);
res_dat <= reg_dat(out_dat'range) when clip = '0' else std_logic_vector( c_smax) when sign = '0' else std_logic_vector(c_smin);
res_ovr <= clip;
end generate;
- gen_u_clip : if g_representation ="unsigned " generate
+ gen_u_clip : if g_representation ="unsigned " generate
clip <= '1' when unsigned(reg_dat) > c_umax else '0';
res_dat <= reg_dat(out_dat'range) when clip = '0' else std_logic_vector(c_umax);
res_ovr <= clip;
diff --git a/libraries/base/common/src/vhdl/common_round.vhd b/libraries/base/common/src/vhdl/common_round.vhd
index d97e936113b28fbe7066bffb45ed7a9d03ac0811..60b8ec1d5c70ef9c6ba50283e5bc0a17aaa477f9 100644
--- a/libraries/base/common/src/vhdl/common_round.vhd
+++ b/libraries/base/common/src/vhdl/common_round.vhd
@@ -82,19 +82,19 @@ begin
);
-- Increase to out_dat width
- no_s : if c_remove_w <= 0 and g_representation ="signed " generate
+ no_s : if c_remove_w <= 0 and g_representation ="signed " generate
res_dat <= RESIZE_SVEC(reg_dat, g_out_dat_w);
end generate;
- no_u : if c_remove_w <= 0 and g_representation ="unsigned " generate
+ no_u : if c_remove_w <= 0 and g_representation ="unsigned " generate
res_dat <= RESIZE_UVEC(reg_dat, g_out_dat_w);
end generate;
-- Decrease to out_dat width by c_remove_w number of LSbits
-- . rounding
- gen_s : if c_remove_w > 0 and g_round = TRUE and g_representation ="signed " generate
+ gen_s : if c_remove_w > 0 and g_round = TRUE and g_representation ="signed " generate
res_dat <= s_round(reg_dat, c_remove_w, g_round_clip, g_round_even);
end generate;
- gen_u : if c_remove_w > 0 and g_round = TRUE and g_representation ="unsigned " generate
+ gen_u : if c_remove_w > 0 and g_round = TRUE and g_representation ="unsigned " generate
res_dat <= u_round(reg_dat, c_remove_w, g_round_clip, g_round_even);
end generate;
-- . truncating
diff --git a/libraries/base/common/src/vhdl/common_spulse.vhd b/libraries/base/common/src/vhdl/common_spulse.vhd
index c9d4ff971e6edf122e5ad0192afae2a77177596c..8d98c5407a895ec6577bb6561b963df444d9b036 100644
--- a/libraries/base/common/src/vhdl/common_spulse.vhd
+++ b/libraries/base/common/src/vhdl/common_spulse.vhd
@@ -54,10 +54,10 @@ end;
architecture rtl of common_spulse is
signal in_level : std_logic;
- signal meta_level : std_logic_vector(0 TO g_delay_len - 1);
+ signal meta_level : std_logic_vector(0 to g_delay_len - 1);
signal out_level : std_logic;
signal prev_out_level : std_logic;
- signal meta_ack : std_logic_vector(0 TO g_delay_len - 1);
+ signal meta_ack : std_logic_vector(0 to g_delay_len - 1);
signal pulse_ack : std_logic;
signal nxt_out_pulse : std_logic;
diff --git a/libraries/base/common/src/vhdl/common_str_pkg.vhd b/libraries/base/common/src/vhdl/common_str_pkg.vhd
index fdadcc5c62443d04a2dcbb2bf3741b0e290f4d05..0fe26a6709e1d0e896583fb55d0b75480e5a333e 100644
--- a/libraries/base/common/src/vhdl/common_str_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_str_pkg.vhd
@@ -111,7 +111,7 @@ package body common_str_pkg is
variable v_str : string(1 to c_max_len_bool) := (others => ' ');
begin
STD.TEXTIO.WRITE(v_line, bool);
- v_str(v_line.all'range) := v_line.ALL;
+ v_str(v_line.all'range) := v_line.all;
deallocate(v_line);
return v_str;
end;
@@ -122,7 +122,7 @@ package body common_str_pkg is
variable v_str : string(1 to c_max_len_time) := (others => ' ');
begin
write(v_line, in_time);
- v_str(v_line.all'range) := v_line.ALL;
+ v_str(v_line.all'range) := v_line.all;
deallocate(v_line);
return v_str;
end;
@@ -137,7 +137,7 @@ package body common_str_pkg is
variable v_str : string(1 to slv'length) := (others => ' ');
begin
write(v_line, slv);
- v_str(v_line.all'range) := v_line.ALL;
+ v_str(v_line.all'range) := v_line.all;
deallocate(v_line);
return v_str;
end;
@@ -235,7 +235,7 @@ package body common_str_pkg is
variable v_str : string(1 to nof_digits_int(int)) := (others => ' ');
begin
STD.TEXTIO.WRITE(v_line, int);
- v_str(v_line.all'range) := v_line.ALL;
+ v_str(v_line.all'range) := v_line.all;
deallocate(v_line);
return v_str;
end;
@@ -252,7 +252,7 @@ package body common_str_pkg is
variable v_len : natural;
begin
STD.TEXTIO.WRITE(v_line, re, right, width, digits);
- v_str(v_line.all'range) := v_line.ALL;
+ v_str(v_line.all'range) := v_line.all;
v_len := v_line.ALL'length;
deallocate(v_line);
if width > v_len then
@@ -325,4 +325,4 @@ package body common_str_pkg is
return r;
end;
-end common_str_pkg;
+end common_str_pkg;
\ No newline at end of file
diff --git a/libraries/base/common/src/vhdl/common_wideband_data_scope.vhd b/libraries/base/common/src/vhdl/common_wideband_data_scope.vhd
index d4c671017253c521bfe63e5a04fe4ab332a32269..8ffdd32ce174437c663f3f4de2e55ed068a575ed 100644
--- a/libraries/base/common/src/vhdl/common_wideband_data_scope.vhd
+++ b/libraries/base/common/src/vhdl/common_wideband_data_scope.vhd
@@ -84,7 +84,7 @@ begin
begin
if rising_edge(SCLKi) then
if g_wideband_big_endian = TRUE then
- vI := g_wideband_factor - 1 -scope_cnt;
+ vI := g_wideband_factor - 1 - scope_cnt;
else
vI := scope_cnt;
end if;
diff --git a/libraries/base/common/src/vhdl/mms_common_pulse_delay.vhd b/libraries/base/common/src/vhdl/mms_common_pulse_delay.vhd
index 3d18bd36912c289eaadd0391883f309a998ce138..dd728309f6e5f4cc68eff64f520654f9e4f9c9da 100644
--- a/libraries/base/common/src/vhdl/mms_common_pulse_delay.vhd
+++ b/libraries/base/common/src/vhdl/mms_common_pulse_delay.vhd
@@ -91,4 +91,4 @@ begin
sla_out => reg_miso
);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/common/src/vhdl/mms_common_reg.vhd b/libraries/base/common/src/vhdl/mms_common_reg.vhd
index 9e8c279c6cd66df217f9b801a2c0740b6d2519b2..6a513a735d7d13201d1be9128350683eb49b35d5 100644
--- a/libraries/base/common/src/vhdl/mms_common_reg.vhd
+++ b/libraries/base/common/src/vhdl/mms_common_reg.vhd
@@ -90,4 +90,4 @@ begin
out_reg => out_reg
);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/common/src/vhdl/mms_common_stable_monitor.vhd b/libraries/base/common/src/vhdl/mms_common_stable_monitor.vhd
index b495c6d3b598a97fc15c6c3924b959271a3f1169..1d255224f0d9664bd37875bc839ae76e04aa127a 100644
--- a/libraries/base/common/src/vhdl/mms_common_stable_monitor.vhd
+++ b/libraries/base/common/src/vhdl/mms_common_stable_monitor.vhd
@@ -112,4 +112,4 @@ begin
);
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/common/tb/vhdl/tb_common_add_sub.vhd b/libraries/base/common/tb/vhdl/tb_common_add_sub.vhd
index fa4be690c3e612ba5e2a81bd2b60c2282bb8e3b9..2ad71ee1038345341fec1d3ae64dc35f3be2e3a3 100644
--- a/libraries/base/common/tb/vhdl/tb_common_add_sub.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_add_sub.vhd
@@ -48,10 +48,10 @@ architecture tb of tb_common_add_sub is
-- Calculate expected result
v_a := to_sint(in_a);
v_b := to_sint(in_b);
- if g_direction ="ADD " then v_result := v_a + v_b; end if;
- if g_direction ="SUB " then v_result := v_a - v_b; end if;
- if g_direction ="BOTH " and g_sel_add = '1' then v_result := v_a + v_b; end if;
- if g_direction ="BOTH " and g_sel_add = '0' then v_result := v_a - v_b; end if;
+ if g_direction ="ADD " then v_result := v_a + v_b; end if;
+ if g_direction ="SUB " then v_result := v_a - v_b; end if;
+ if g_direction ="BOTH " and g_sel_add = '1' then v_result := v_a + v_b; end if;
+ if g_direction ="BOTH " and g_sel_add = '0' then v_result := v_a - v_b; end if;
-- Wrap to avoid warning: NUMERIC_STD.TO_SIGNED: vector truncated
if v_result > 2 ** (g_out_dat_w - 1) - 1 then v_result := v_result - 2 ** g_out_dat_w; end if;
if v_result < - 2 ** (g_out_dat_w - 1) then v_result := v_result + 2 ** g_out_dat_w; end if;
diff --git a/libraries/base/common/tb/vhdl/tb_common_adder_tree.vhd b/libraries/base/common/tb/vhdl/tb_common_adder_tree.vhd
index a0920315ba2e79aa1b32196e42e1f49e20ea5820..4c118458a26142534c71035194343a2ee0055d7a 100644
--- a/libraries/base/common/tb/vhdl/tb_common_adder_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_adder_tree.vhd
@@ -74,7 +74,7 @@ architecture tb of tb_common_adder_tree is
variable v_result : integer;
begin
v_result := 0;
- if g_representation ="signed " then
+ if g_representation ="signed " then
for I in 0 to g_nof_inputs - 1 loop
v_result := v_result + to_sint(data_vec((I + 1) * g_symbol_w - 1 downto I * g_symbol_w));
end loop;
diff --git a/libraries/base/common/tb/vhdl/tb_common_counter.vhd b/libraries/base/common/tb/vhdl/tb_common_counter.vhd
index b6c54ce1dd3716175389236fa5b1dc2cd3a67920..aed20f4311d9fc5e63fafeb645b6ce6e93d26a30 100644
--- a/libraries/base/common/tb/vhdl/tb_common_counter.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_counter.vhd
@@ -106,5 +106,4 @@ begin
count => count
);
-end tb;
-
+end tb;
\ No newline at end of file
diff --git a/libraries/base/common/tb/vhdl/tb_common_multiplexer.vhd b/libraries/base/common/tb/vhdl/tb_common_multiplexer.vhd
index 44c55a8e2727c55b7ad6f61e778a377f6f79763b..bdc169bff8f959b165bd69927b1e8f48773c963f 100644
--- a/libraries/base/common/tb/vhdl/tb_common_multiplexer.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_multiplexer.vhd
@@ -89,8 +89,8 @@ architecture tb of tb_common_multiplexer is
-- Verify
signal prev_out_dat : std_logic_vector(g_dat_w - 1 downto 0);
- signal pipe_dat_vec : std_logic_vector(0 TO (c_pipeline_total + 1) * g_dat_w - 1);
- signal pipe_val_vec : std_logic_vector(0 TO (c_pipeline_total + 1) * 1 - 1);
+ signal pipe_dat_vec : std_logic_vector(0 to (c_pipeline_total + 1) * g_dat_w - 1);
+ signal pipe_val_vec : std_logic_vector(0 to (c_pipeline_total + 1) * 1 - 1);
begin
diff --git a/libraries/base/common/tb/vhdl/tb_common_operation_tree.vhd b/libraries/base/common/tb/vhdl/tb_common_operation_tree.vhd
index bc19bb5eb158aed5e9b7f2f3e1404592d6b5aa4c..8f6b360bb3563a6aadd3ef0d31e653f06f157ae5 100644
--- a/libraries/base/common/tb/vhdl/tb_common_operation_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_operation_tree.vhd
@@ -83,26 +83,26 @@ architecture tb of tb_common_operation_tree is
variable v_result : integer := 0;
begin
-- Init v_result
- if representation ="signed " then
- if operation ="MIN " then v_result := c_smax; end if;
- if operation ="MAX " then v_result := c_smin; end if;
+ if representation ="signed " then
+ if operation ="MIN " then v_result := c_smax; end if;
+ if operation ="MAX " then v_result := c_smin; end if;
else
- if operation ="MIN " then v_result := c_umax; end if;
- if operation ="MAX " then v_result := c_umin; end if;
+ if operation ="MIN " then v_result := c_umax; end if;
+ if operation ="MAX " then v_result := c_umin; end if;
end if;
-- Find v_result
for I in 0 to g_nof_inputs - 1 loop
v_in := data_vec((I + 1) * c_dat_w - 1 downto I * c_dat_w);
- if representation ="signed " then
- if operation ="MIN " then if v_result > signed(v_in) then v_result := to_sint(v_in); end if; end if;
- if operation ="MAX " then if v_result < signed(v_in) then v_result := to_sint(v_in); end if; end if;
+ if representation ="signed " then
+ if operation ="MIN " then if v_result > signed(v_in) then v_result := to_sint(v_in); end if; end if;
+ if operation ="MAX " then if v_result < signed(v_in) then v_result := to_sint(v_in); end if; end if;
else
- if operation ="MIN " then if v_result > unsigned(v_in) then v_result := to_uint(v_in); end if; end if;
- if operation ="MAX " then if v_result < unsigned(v_in) then v_result := to_uint(v_in); end if; end if;
+ if operation ="MIN " then if v_result > unsigned(v_in) then v_result := to_uint(v_in); end if; end if;
+ if operation ="MAX " then if v_result < unsigned(v_in) then v_result := to_uint(v_in); end if; end if;
end if;
end loop;
-- Return v_result
- if representation ="signed " then
+ if representation ="signed " then
return to_svec(v_result, c_dat_w);
else
return to_uvec(v_result, c_dat_w);
diff --git a/libraries/base/common/tb/vhdl/tb_common_pkg.vhd b/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
index 2b2c1ff190ec24601210e774ff2cb9498be99361..14a183fc83d5a237720202244eef6b64f727fc04 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
@@ -1211,7 +1211,7 @@ package body tb_common_pkg is
variable v_string : string(1 to 80);
variable v_row_arr : t_integer_arr(0 to nof_col - 1);
begin
- if file_name /="UNUSED " and file_name /="unused " then
+ if file_name /="UNUSED " and file_name /="unused " then
-- Open the file for reading
proc_common_open_file(v_file_status, v_in_file, file_name, READ_MODE);
-- Read and skip the header
@@ -1333,7 +1333,7 @@ package body tb_common_pkg is
-- b) IEEE signed resizing preserves the MSbit so b0100000 = +64 becomes b0_00000 = 0
-- c) detect MSbits = "01" to clip max positive to get _b011111 = +63
-- Option a) seems to map best on the FPGA hardware multiplier IP.
- if str ="RE " then
+ if str ="RE " then
return std_logic_vector(RESIZE_NUM(v_result_re, g_out_dat_w)); -- conform option a)
else
return std_logic_vector(RESIZE_NUM(v_result_im, g_out_dat_w)); -- conform option a)
@@ -1442,4 +1442,4 @@ package body tb_common_pkg is
return(v_found_it);
end function func_find_string_in_string;
-end tb_common_pkg;
+end tb_common_pkg;
\ No newline at end of file
diff --git a/libraries/base/common/tb/vhdl/tb_common_pulse_delay.vhd b/libraries/base/common/tb/vhdl/tb_common_pulse_delay.vhd
index 86a4f28c99384d1e842d2fc746c90c5372bf93cf..0202e557fe8800995a5c36a482b258bec4c311de 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pulse_delay.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pulse_delay.vhd
@@ -165,4 +165,4 @@ begin
end if;
end process;
-end tb;
+end tb;
\ No newline at end of file
diff --git a/libraries/base/common/tb/vhdl/tb_common_switch.vhd b/libraries/base/common/tb/vhdl/tb_common_switch.vhd
index 59639c448bb5163f5cb601556fd9b3a8d27daa8a..5c133a7699e9d990fcaebac2e5eb0738fb3b4098 100644
--- a/libraries/base/common/tb/vhdl/tb_common_switch.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_switch.vhd
@@ -76,7 +76,7 @@ architecture tb of tb_common_switch is
signal dbg_prio_hi_or : std_logic;
signal dbg_prio_hi_or_and : std_logic;
- signal out_level : std_logic_vector(0 TO c_nof_dut - 1);
+ signal out_level : std_logic_vector(0 to c_nof_dut - 1);
begin
diff --git a/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd b/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd
index c4cae7c24745430f8b78a1774c05909fc24bdec0..2a70f88e12090c0a7c6143834a0df828d0e46551 100644
--- a/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd
@@ -119,5 +119,4 @@ begin
out_pulse => trigger_dly
);
-end tb;
-
+end tb;
\ No newline at end of file
diff --git a/libraries/base/common/tb/vhdl/tb_common_zip.vhd b/libraries/base/common/tb/vhdl/tb_common_zip.vhd
index 632aabac1c45fb4d5b0ec6166e924421e4c195a9..c5370bafe79d3dc680fea15660f3c572cfd9d6b4 100644
--- a/libraries/base/common/tb/vhdl/tb_common_zip.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_zip.vhd
@@ -93,4 +93,4 @@ begin
out_dat => out_dat
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd b/libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd
index 52d6ed10293eb157d8bfe166d63fda142986538e..dbf61fdee304b7980a62c1e8c0698e2a94aa77fb 100644
--- a/libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd
+++ b/libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd
@@ -107,4 +107,4 @@ begin
trigger_dly => trigger_dly
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/libraries/base/common_mult/src/vhdl/common_complex_mult_add.vhd b/libraries/base/common_mult/src/vhdl/common_complex_mult_add.vhd
index f47451536ee4c0b430aef85dacd95cd58de5217c..97c25e2d754a93ee031a3cfa9a455a3711686933 100644
--- a/libraries/base/common_mult/src/vhdl/common_complex_mult_add.vhd
+++ b/libraries/base/common_mult/src/vhdl/common_complex_mult_add.vhd
@@ -193,4 +193,4 @@ begin
out_sumr <= std_logic_vector(sumr);
out_sumi <= std_logic_vector(sumi);
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/base/common_mult/tb/vhdl/tb_common_mult_add2.vhd b/libraries/base/common_mult/tb/vhdl/tb_common_mult_add2.vhd
index 2d776b88cfb807894040d11e239e7b0b6f840b24..c4f9d30892e58c4b98b18846e982ad743cf232dc 100644
--- a/libraries/base/common_mult/tb/vhdl/tb_common_mult_add2.vhd
+++ b/libraries/base/common_mult/tb/vhdl/tb_common_mult_add2.vhd
@@ -76,8 +76,8 @@ architecture tb of tb_common_mult_add2 is
v_b0 := RESIZE_NUM(signed(in_b0), c_in_w);
v_a1 := RESIZE_NUM(signed(in_a1), c_in_w);
v_b1 := RESIZE_NUM(signed(in_b1), c_in_w);
- if g_add_sub ="ADD " then v_result := RESIZE_NUM(v_a0 * v_b0, c_res_w) + v_a1 * v_b1; end if;
- if g_add_sub ="SUB " then v_result := RESIZE_NUM(v_a0 * v_b0, c_res_w) - v_a1 * v_b1; end if;
+ if g_add_sub ="ADD " then v_result := RESIZE_NUM(v_a0 * v_b0, c_res_w) + v_a1 * v_b1; end if;
+ if g_add_sub ="SUB " then v_result := RESIZE_NUM(v_a0 * v_b0, c_res_w) - v_a1 * v_b1; end if;
-- Wrap to avoid warning: NUMERIC_STD.TO_SIGNED: vector truncated
if v_result > 2 ** (g_out_dat_w - 1) - 1 then v_result := v_result - 2 ** g_out_dat_w; end if;
if v_result < - 2 ** (g_out_dat_w - 1) then v_result := v_result + 2 ** g_out_dat_w; end if;
diff --git a/libraries/base/diag/src/vhdl/diag_data_buffer.vhd b/libraries/base/diag/src/vhdl/diag_data_buffer.vhd
index c50653ad928baaa813ec04b0e67a1871722b19c6..c9999b397a5d5156cd4fe06de6edba42d8e6956b 100644
--- a/libraries/base/diag/src/vhdl/diag_data_buffer.vhd
+++ b/libraries/base/diag/src/vhdl/diag_data_buffer.vhd
@@ -262,4 +262,4 @@ begin
count => sync_cnt
);
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd b/libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd
index 2ddb68171ccb67c664d729a73d9a370515f32994..3c8c1cf0cde1c8e7299681f13ea37ba3ae83865b 100644
--- a/libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd
+++ b/libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd
@@ -373,5 +373,4 @@ begin
count => valid_cnt
);
-end rtl;
-
+end rtl;
\ No newline at end of file
diff --git a/libraries/base/diag/src/vhdl/diag_rx_seq.vhd b/libraries/base/diag/src/vhdl/diag_rx_seq.vhd
index f54744f4cd061dec38a23614f81c5d7038b323c8..b140cd5e9bd6b1c52ef7beeaf2aae27e4231ae7d 100644
--- a/libraries/base/diag/src/vhdl/diag_rx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/diag_rx_seq.vhd
@@ -162,7 +162,7 @@ architecture rtl of diag_rx_seq is
signal in_val_1 : std_logic;
signal in_val_act : std_logic;
signal in_val_2 : std_logic;
- signal in_val_2_dly : std_logic_vector(0 TO c_diag_res_latency - 1) := (others => '0');
+ signal in_val_2_dly : std_logic_vector(0 to c_diag_res_latency - 1) := (others => '0');
signal in_val_2_act : std_logic;
signal ref_dat : std_logic_vector(in_dat'range);
diff --git a/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd b/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd
index 46f8aebd6381134ea24a77fb26943cc190f8c4e3..718e647e111a084cbbebf7ae98417d04075e8d2f 100644
--- a/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd
+++ b/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd
@@ -93,17 +93,17 @@ architecture str of diag_wg_wideband is
signal st_mon_ctrl_arr : t_diag_wg_arr(0 to g_wideband_factor - 1);
-- Use same address and data widths for both MM side and ST side memory ports
- signal buf_rdval : std_logic_vector(0 TO g_wideband_factor - 1);
+ signal buf_rdval : std_logic_vector(0 to g_wideband_factor - 1);
signal buf_rddata : t_buf_dat_arr(0 to g_wideband_factor - 1);
signal st_address : t_buf_adr_arr(0 to g_wideband_factor - 1);
- signal st_rd : std_logic_vector(0 TO g_wideband_factor - 1);
- signal st_rdval : std_logic_vector(0 TO g_wideband_factor - 1);
+ signal st_rd : std_logic_vector(0 to g_wideband_factor - 1);
+ signal st_rdval : std_logic_vector(0 to g_wideband_factor - 1);
signal st_rddata : t_buf_dat_arr(0 to g_wideband_factor - 1);
begin
- assert c_buf_file /="UNUSED " report "diag_wg_wideband : no buffer waveform file available" severity FAILURE;
+ assert c_buf_file /="UNUSED " report "diag_wg_wideband : no buffer waveform file available" severity FAILURE;
-- MM write same to all g_wideband_factor waveform buffers
-- MM read only from waveform buffer 0
diff --git a/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd b/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd
index 86cfbd0fe4ec4f30f045a033e38f9ba18a685e77..b1c858b2d6ee8da849d3cbefab03b2bab80e2bc6 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd
@@ -317,6 +317,3 @@ end str;
-
-
-
diff --git a/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd b/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd
index 7ddf93cc0222922b406de43cabaec69995b0a70a..1a2c2fdf58714c64381ced90be127826f297202a 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd
@@ -395,6 +395,3 @@ end str;
-
-
-
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_block_gen.vhd b/libraries/base/diag/tb/vhdl/tb_diag_block_gen.vhd
index 17eba40fd9d745c9894cebeae8933e7a5aad2027..9479645c7896e3728850c494df877654d6a458ae 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_block_gen.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_block_gen.vhd
@@ -280,4 +280,4 @@ begin
random(random'high) when g_flow_control_verify = e_random else
toggle when g_flow_control_verify = e_pulse;
-end tb;
+end tb;
\ No newline at end of file
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_frm_generator.vhd b/libraries/base/diag/tb/vhdl/tb_diag_frm_generator.vhd
index 7315464ed13a4500c2a7a3ab8668cf039d180bbc..7244a460fb09bea115fa8d7e48815c835fa77110 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_frm_generator.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_frm_generator.vhd
@@ -179,4 +179,4 @@ begin
end if;
end process;
-end tb;
+end tb;
\ No newline at end of file
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_frm_monitor.vhd b/libraries/base/diag/tb/vhdl/tb_diag_frm_monitor.vhd
index 445b5524f16aef06c526002dbebcd41efe7c78fa..0a048e5e2c9dd3ba7cf354b6d234b148e5a6fb7d 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_frm_monitor.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_frm_monitor.vhd
@@ -200,4 +200,4 @@ begin
end if;
end process;
-end tb;
+end tb;
\ No newline at end of file
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd b/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd
index af2f8bf2831b6831e1629ae65d96bdfc14209dea..d44322cf0009893c14d7de55f9075758d468a5b3 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd
@@ -269,7 +269,7 @@ package body tb_diag_pkg is
variable v_sel : natural;
variable v_ctlr : natural;
begin
- if c_pattern ="PSRG " then
+ if c_pattern ="PSRG " then
v_sel := 0; -- pseudo random data
else
v_sel := 1; -- counter data
@@ -297,7 +297,7 @@ package body tb_diag_pkg is
variable v_sel : natural;
variable v_ctlr : natural;
begin
- if c_pattern ="PSRG " then
+ if c_pattern ="PSRG " then
v_sel := 0; -- pseudo random data
else
v_sel := 1; -- counter data
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd b/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd
index 08692db3ae4838b09c25cda57e045a69e39e329e..1a8c64424dfc0dbd4b067af6b01f1833ebb6d1ce 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd
@@ -301,4 +301,4 @@ begin
end if;
end process;
-end tb;
+end tb;
\ No newline at end of file
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_tx_frm.vhd b/libraries/base/diag/tb/vhdl/tb_diag_tx_frm.vhd
index 0e24df89c32f3a40e496d696e1ee7df3a5d1106a..1b4ef172d17d2ac4bbe2e7c7e1ac6ccefaaf5127 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_tx_frm.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_tx_frm.vhd
@@ -198,4 +198,4 @@ begin
end if;
end process;
-end tb;
+end tb;
\ No newline at end of file
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_tx_seq.vhd b/libraries/base/diag/tb/vhdl/tb_diag_tx_seq.vhd
index 4589534ec9eccd741f1d585c7931db24e420cdcf..fa6fac04a921162570f02128bf5d2d2236e160e6 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_tx_seq.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_tx_seq.vhd
@@ -120,4 +120,4 @@ begin
out_val => seq_val
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_wg.vhd b/libraries/base/diag/tb/vhdl/tb_diag_wg.vhd
index d746c0173f07f172e28af5c181d839ecdad37948..586d0de477b45118c9cc9ce4b725474e348a8d2a 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_wg.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_wg.vhd
@@ -259,4 +259,4 @@ begin
out_sync => wg_sync
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd b/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd
index 7cffdd45c127367c93e696856cc41a86a01bedfc..6e0cf952eb3554dcc908ef52e9f17242abeadd4f 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd
@@ -96,10 +96,10 @@ architecture tb of tb_diag_wg_wideband is
signal out_val : std_logic_vector(g_wideband_factor - 1 downto 0);
signal out_sync : std_logic_vector(g_wideband_factor - 1 downto 0);
- signal wg_ovr : std_logic_vector(0 TO g_wideband_factor - 1);
+ signal wg_ovr : std_logic_vector(0 to g_wideband_factor - 1);
signal wg_dat : t_buf_dat_arr(0 to g_wideband_factor - 1);
- signal wg_val : std_logic_vector(0 TO g_wideband_factor - 1);
- signal wg_sync : std_logic_vector(0 TO g_wideband_factor - 1);
+ signal wg_val : std_logic_vector(0 to g_wideband_factor - 1);
+ signal wg_sync : std_logic_vector(0 to g_wideband_factor - 1);
signal sample_clk : std_logic := '1';
signal sample_cnt : natural range 0 to g_wideband_factor - 1;
@@ -325,4 +325,4 @@ begin
end if;
end process;
-end tb;
+end tb;
\ No newline at end of file
diff --git a/libraries/base/diagnostics/src/vhdl/diagnostics.vhd b/libraries/base/diagnostics/src/vhdl/diagnostics.vhd
index 4950b096a584b08895470bc242c9ff9983b82f00..73e2b553b71f09a4e0761ffe1dbd4d045a753df7 100644
--- a/libraries/base/diagnostics/src/vhdl/diagnostics.vhd
+++ b/libraries/base/diagnostics/src/vhdl/diagnostics.vhd
@@ -284,4 +284,4 @@ begin
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/diagnostics/src/vhdl/mm_rx_logger.vhd b/libraries/base/diagnostics/src/vhdl/mm_rx_logger.vhd
index 89faabf28f1de022a57f51c26c7e183d68776985..018ab6c11a909855a996023fbae5f8c63a367f74 100644
--- a/libraries/base/diagnostics/src/vhdl/mm_rx_logger.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mm_rx_logger.vhd
@@ -261,5 +261,4 @@ begin
-end str;
-
+end str;
\ No newline at end of file
diff --git a/libraries/base/diagnostics/src/vhdl/mm_rx_logger_reg.vhd b/libraries/base/diagnostics/src/vhdl/mm_rx_logger_reg.vhd
index 230444c1383a21c297f1a5266dfcc4ff431e2f49..60c1db393471334ad522260037615337512c6c9d 100644
--- a/libraries/base/diagnostics/src/vhdl/mm_rx_logger_reg.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mm_rx_logger_reg.vhd
@@ -210,4 +210,4 @@ begin
mm_trig_nof_logged_words <= rx_trig_nof_logged_words;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/base/diagnostics/src/vhdl/mm_rx_logger_trig.vhd b/libraries/base/diagnostics/src/vhdl/mm_rx_logger_trig.vhd
index 0b5dbf623691ca68bd451892af4e704cffc6f949..9dcb3182762c9f67e37b0dbcdb3ea866cb258019 100644
--- a/libraries/base/diagnostics/src/vhdl/mm_rx_logger_trig.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mm_rx_logger_trig.vhd
@@ -110,4 +110,4 @@ begin
end case;
end process;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/diagnostics/src/vhdl/mm_tx_framer.vhd b/libraries/base/diagnostics/src/vhdl/mm_tx_framer.vhd
index 6e70a08f79e8068174f44ccd015cb22f166d08ed..35582fc9dbafe77f55633ce8e4fe96e9e8f002f0 100644
--- a/libraries/base/diagnostics/src/vhdl/mm_tx_framer.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mm_tx_framer.vhd
@@ -137,4 +137,4 @@ begin
);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/diagnostics/src/vhdl/mm_tx_framer_reg.vhd b/libraries/base/diagnostics/src/vhdl/mm_tx_framer_reg.vhd
index 62cf1450c8a152927f8c5770a74c832f1e2d2990..3b4d842cc5fe73978b875b21af0ea864fb868715 100644
--- a/libraries/base/diagnostics/src/vhdl/mm_tx_framer_reg.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mm_tx_framer_reg.vhd
@@ -132,4 +132,4 @@ begin
dout => tx_release
);
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/base/diagnostics/src/vhdl/mms_diagnostics.vhd b/libraries/base/diagnostics/src/vhdl/mms_diagnostics.vhd
index ddd0426b466eb5b18807de12744de20cf527ba9f..15b829de6fa0e8c73f045faa0e8cfef4c33d4850 100644
--- a/libraries/base/diagnostics/src/vhdl/mms_diagnostics.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mms_diagnostics.vhd
@@ -159,4 +159,4 @@ begin
);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/diagnostics/tb/vhdl/tb_diagnostics.vhd b/libraries/base/diagnostics/tb/vhdl/tb_diagnostics.vhd
index a2e20b599689c78d1eabc635a2d7ec3423db4862..040b6eb296967230e750ea0a7b096cf9e64bed84 100644
--- a/libraries/base/diagnostics/tb/vhdl/tb_diagnostics.vhd
+++ b/libraries/base/diagnostics/tb/vhdl/tb_diagnostics.vhd
@@ -130,5 +130,4 @@ architecture str of tb_diagnostics is
);
-end architecture str;
-
+end architecture str;
\ No newline at end of file
diff --git a/libraries/base/diagnostics/tb/vhdl/tb_mm_tx_framer.vhd b/libraries/base/diagnostics/tb/vhdl/tb_mm_tx_framer.vhd
index 4a1946c70b6f3451d6783bda2f77cfe1d9126894..cee0f2d5777d58421deb52e2b42a352aa87d086e 100644
--- a/libraries/base/diagnostics/tb/vhdl/tb_mm_tx_framer.vhd
+++ b/libraries/base/diagnostics/tb/vhdl/tb_mm_tx_framer.vhd
@@ -177,4 +177,4 @@ begin
slave_release => mst_release
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
index b15587402caa3cb2b1447089cc12f989c89442e1..bd39d5c34d6a6add4cabf266315ca37b22de0b4a 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
+++ b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
@@ -156,7 +156,7 @@ architecture str of mmm_unb1_dp_offload is
constant c_dp_clk_period : time := 5 ns;
constant c_sim_node_type : string(1 to 2) := sel_a_b(g_sim_node_nr <4, "FN", "BN");
- constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type ="BN ", g_sim_node_nr -4, g_sim_node_nr);
+ constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type ="BN ", g_sim_node_nr -4, g_sim_node_nr);
constant c_sim_eth_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := x"00228608" & to_uvec(g_sim_unb_nr, c_byte_w) & to_uvec(g_sim_node_nr, c_byte_w);
constant c_sim_eth_control_rx_en : natural := 2 ** c_eth_mm_reg_control_bi.rx_en;
diff --git a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/unb1_dp_offload.vhd b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/unb1_dp_offload.vhd
index e99064d5e9054e1e2c2b9342ffe0b76c0f319254..c5b27efdee81a35e4a82822473aab34a4471af6e 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/unb1_dp_offload.vhd
+++ b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/unb1_dp_offload.vhd
@@ -69,8 +69,8 @@ entity unb1_dp_offload is
-- 1GbE Control Interface
ETH_clk : in std_logic;
- ETH_SGin : IN std_logic;
- ETH_SGout : OUT std_logic
+ ETH_SGin : in std_logic;
+ ETH_SGout : out std_logic
);
end unb1_dp_offload;
@@ -95,7 +95,7 @@ architecture str of unb1_dp_offload is
to_uvec( 0, c_diag_bg_bsn_init_w));
-- dp_offload_tx
- constant c_nof_hdr_fields : natural := 4 +12 + 4 + 9; -- Total header bits = 512
+ constant c_nof_hdr_fields : natural := 4 + 12 + 4 + 9; -- Total header bits = 512
constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( ( field_name_pad("eth_word_align" ), " ", 16, field_default(0) ),
( field_name_pad("eth_dst_mac" ), " ", 48, field_default(x"002286080000") ),
( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
@@ -126,7 +126,7 @@ architecture str of unb1_dp_offload is
( field_name_pad("usr_hdr_field_5" ), " ", 8, field_default(0) ),
( field_name_pad("usr_hdr_field_6" ), " ", 27, field_default(0) ) );
- constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "1101" &"111111111100 " &"1111 " &"001111111 ";
+ constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "1101" &"111111111100 " &"1111 " &"001111111 ";
constant c_nof_words_per_block : natural := 11;
constant c_nof_blocks_per_packet : natural := 2;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_align_reg.vhd b/libraries/base/dp/src/vhdl/dp_bsn_align_reg.vhd
index 8cac283e02ec8d00288708f2207d3dc8adeec7f6..08e91bb91ef3dcf61c28a0fe4f0c3dc66a80b26f 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_align_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_align_reg.vhd
@@ -118,4 +118,4 @@ begin
out_en_arr(I) <= out_en_arr_reg(I * c_word_w);
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_delay.vhd b/libraries/base/dp/src/vhdl/dp_bsn_delay.vhd
index fc12b7c15a884a98360d35cf12d9415197521eb1..177308b4072d5647aca62540097e63607d5db4d9 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_delay.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_delay.vhd
@@ -87,8 +87,8 @@ architecture rtl of dp_bsn_delay is
type t_bsn_arr is array (integer range <> ) of std_logic_vector(g_bsn_w - 1 downto 0);
signal hold_sync : std_logic;
- signal sync_dly : std_logic_vector(0 TO g_nof_block_latency); -- [0] is hold_sync, the combinatorial in_sync is not delayed, because the DP latency must be > 0
- signal nxt_sync_dly : std_logic_vector(1 TO g_nof_block_latency);
+ signal sync_dly : std_logic_vector(0 to g_nof_block_latency); -- [0] is hold_sync, the combinatorial in_sync is not delayed, because the DP latency must be > 0
+ signal nxt_sync_dly : std_logic_vector(1 to g_nof_block_latency);
signal bsn_dly : t_bsn_arr(0 to g_nof_block_latency); -- [0] is combinatorial in_bsn
signal nxt_bsn_dly : t_bsn_arr(1 to g_nof_block_latency);
@@ -138,4 +138,4 @@ begin
nxt_bsn_reg <= bsn_dly(g_nof_block_latency) when out_release = '1' else bsn_reg; -- register the BSN to hold it during the output block
out_bsn <= bsn_reg;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_monitor.vhd b/libraries/base/dp/src/vhdl/dp_bsn_monitor.vhd
index 839dd961b552ed2e5e67f6da8872c73a8492bb81..b846dfe2daa3c7dc71c349ccde28bad643ba5966 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_monitor.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_monitor.vhd
@@ -339,6 +339,4 @@ begin
count => cnt_cycle
);
-end rtl;
-
-
+end rtl;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_monitor_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_monitor_v2.vhd
index 8d29a312fcc6b7b3851a74de74a234391d589913..4097d6175a2b22948e120f74eca9b97147365ac8 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_monitor_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_monitor_v2.vhd
@@ -341,6 +341,4 @@ begin
count => cnt_latency
);
-end rtl;
-
-
+end rtl;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_scheduler.vhd b/libraries/base/dp/src/vhdl/dp_bsn_scheduler.vhd
index d9fa9bb5cd3be02dfc38d0fa8fcbdf4e060b37f7..68c39b9d759957551c9a6a51a3f52c3c90218e06 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_scheduler.vhd
@@ -75,4 +75,4 @@ begin
end if;
end process;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_source.vhd b/libraries/base/dp/src/vhdl/dp_bsn_source.vhd
index 421394103c18f7823173c55c45a67c6709974957..3657984be33bf702078ca82512086657b53abe87 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_source.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_source.vhd
@@ -178,5 +178,4 @@ begin
end if;
end process;
-end rtl;
-
+end rtl;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd b/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd
index 56cea15ccc722cf908968311af39e416e3a53cf0..03838e6111a0c147b32426a7d3cdef279a5ddaff 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd
@@ -452,5 +452,4 @@ begin
out_enable <= output_enable;
end generate;
-end rtl;
-
+end rtl;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/dp_components_pkg.vhd b/libraries/base/dp/src/vhdl/dp_components_pkg.vhd
index 4cfdb85797564de1f634a56ff9fa9500469081c1..656bd599110b0286ba4b172c706ca3e5e385e297 100644
--- a/libraries/base/dp/src/vhdl/dp_components_pkg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_components_pkg.vhd
@@ -47,4 +47,4 @@ end dp_components_pkg;
package body dp_components_pkg is
-end dp_components_pkg;
+end dp_components_pkg;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/dp_counter_func_single.vhd b/libraries/base/dp/src/vhdl/dp_counter_func_single.vhd
index 96f60a53ed7de092c740f3f54ce8e3269c52e0c1..fb43680f8342b28dbac6f103eb19ba5adf6e426f 100644
--- a/libraries/base/dp/src/vhdl/dp_counter_func_single.vhd
+++ b/libraries/base/dp/src/vhdl/dp_counter_func_single.vhd
@@ -67,7 +67,7 @@ architecture rtl of dp_counter_func_single is
-- . range(0,7,2) = [0, 2, 4, 6]
-- . range(1,7,2) = [1, 3, 5]
-- . The maximum value is: start+((stop-1-start)/step)*step
- constant c_nof_count : natural := (g_range_stop - 1 -g_range_start)/g_range_step + 1;
+ constant c_nof_count : natural := (g_range_stop - 1 - g_range_start) / g_range_step + 1;
constant c_count_max : natural := g_range_start + (c_nof_count - 1) * g_range_step;
constant c_count_w : natural := ceil_log2(c_count_max + 1);
diff --git a/libraries/base/dp/src/vhdl/dp_demux.vhd b/libraries/base/dp/src/vhdl/dp_demux.vhd
index 726125b9505d36ee6b593c7ec7577ad736011582..d3a4a6599f6dce91825e776e91594d9421947122 100644
--- a/libraries/base/dp/src/vhdl/dp_demux.vhd
+++ b/libraries/base/dp/src/vhdl/dp_demux.vhd
@@ -150,7 +150,7 @@ begin
if g_sel_ctrl_invert = FALSE then
output_select <= sel_ctrl;
else
- output_select <= g_nof_output - 1 -sel_ctrl;
+ output_select <= g_nof_output - 1 - sel_ctrl;
end if;
end if;
end process;
@@ -169,7 +169,7 @@ begin
if g_sel_ctrl_invert = FALSE then
output_select <= sel_ctrl;
else
- output_select <= g_nof_output - 1 -sel_ctrl;
+ output_select <= g_nof_output - 1 - sel_ctrl;
end if;
-- User might need this status port to indicate if/when the output has actually been switched
sel_stat <= output_select;
diff --git a/libraries/base/dp/src/vhdl/dp_dummy_source.vhd b/libraries/base/dp/src/vhdl/dp_dummy_source.vhd
index 00527a59f21c8542759accaef1e683ab0e4708a3..036d016d24988fb33278e363f892eede2b093a9f 100644
--- a/libraries/base/dp/src/vhdl/dp_dummy_source.vhd
+++ b/libraries/base/dp/src/vhdl/dp_dummy_source.vhd
@@ -85,4 +85,4 @@ begin
en => '1'
);
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd
index ddc117c5f578e403f70074b3f03b66242eff9aaa..32811197168912d576a2a685e723b75e499bb9ad 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd
@@ -149,4 +149,4 @@ begin
);
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_from_mm_reg.vhd b/libraries/base/dp/src/vhdl/dp_fifo_from_mm_reg.vhd
index b289cf2f6ea2caf6c0fff5e89857806c8e60c199..f2c27e1b2c7022af8a7d5938d74043417fe80957 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_from_mm_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_from_mm_reg.vhd
@@ -77,4 +77,4 @@ begin
end if;
end process;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_monitor.vhd b/libraries/base/dp/src/vhdl/dp_fifo_monitor.vhd
index 387dc60362c780ec1380be5e9e9e7700e0d54025..b34b2bf55524382c9b8e526e72bd381c0dd16fde 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_monitor.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_monitor.vhd
@@ -97,4 +97,4 @@ begin
rd_fill_32b <= mm_fields_out(field_hi(c_field_arr, "rd_fill") downto field_lo(c_field_arr, "rd_fill"));
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_monitor_arr.vhd b/libraries/base/dp/src/vhdl/dp_fifo_monitor_arr.vhd
index 9a1f6c71fac0d2487b2b51ed50626c02c1279db6..b04eef3b277943eb8546283b6a5fb7e0eed53427 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_monitor_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_monitor_arr.vhd
@@ -99,4 +99,4 @@ begin
);
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_to_mm_reg.vhd b/libraries/base/dp/src/vhdl/dp_fifo_to_mm_reg.vhd
index fb0a4f1a4f3182bad1b9159146e5b4c689fed24d..ecfac21b77370b1dc4bd6fb2dac3e3a4b43b3560 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_to_mm_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_to_mm_reg.vhd
@@ -75,4 +75,4 @@ begin
end if;
end process;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/dp_flush.vhd b/libraries/base/dp/src/vhdl/dp_flush.vhd
index 685ce0c7ccbb4d6b9081d6798237482d6b44ba4e..62cf66d5b5ff82f33d766213d7d1fe79cb7e23ba 100644
--- a/libraries/base/dp/src/vhdl/dp_flush.vhd
+++ b/libraries/base/dp/src/vhdl/dp_flush.vhd
@@ -88,7 +88,7 @@ end dp_flush;
architecture rtl of dp_flush is
- signal flush_dly : std_logic_vector(0 TO g_ready_latency); -- use 0 TO high for delay lines, rather than high DOWNTO 0
+ signal flush_dly : std_logic_vector(0 to g_ready_latency); -- use 0 TO high for delay lines, rather than high DOWNTO 0
signal snk_flush : std_logic;
signal snk_flush_hi : std_logic;
signal snk_flush_lo : std_logic;
@@ -210,4 +210,4 @@ begin
out_level => snk_flush
);
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/dp_folder.vhd b/libraries/base/dp/src/vhdl/dp_folder.vhd
index e75a507ae77d6a09033307516915ad37e3a04d1e..f9d14e1b8ea45286610178e0bd99e644923fb7b4 100644
--- a/libraries/base/dp/src/vhdl/dp_folder.vhd
+++ b/libraries/base/dp/src/vhdl/dp_folder.vhd
@@ -252,4 +252,4 @@ begin
dp_block_gen_snk_in_arr <= snk_in_arr;
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/dp_gap.vhd b/libraries/base/dp/src/vhdl/dp_gap.vhd
index 817c17963b8fe2027af300c383adb15b8ffd0524..3cbb863de8f2dc9bead78ea148df4e52e243f2e9 100644
--- a/libraries/base/dp/src/vhdl/dp_gap.vhd
+++ b/libraries/base/dp/src/vhdl/dp_gap.vhd
@@ -150,4 +150,4 @@ begin
snk_out <= src_in;
end generate;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/dp_mon.vhd b/libraries/base/dp/src/vhdl/dp_mon.vhd
index 4e482c8d880a7aa0a3ca75399701c71a063e7038..bf24ad24e1496c07054afad90978aa864f5b654e 100644
--- a/libraries/base/dp/src/vhdl/dp_mon.vhd
+++ b/libraries/base/dp/src/vhdl/dp_mon.vhd
@@ -76,4 +76,4 @@ begin
count => word_cnt
);
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/dp_mux.vhd b/libraries/base/dp/src/vhdl/dp_mux.vhd
index 56d43f2642f3939608fca8fb85aca1f27f80b8be..ab7ce249462f270cfc29ae67fea288286a53232a 100644
--- a/libraries/base/dp/src/vhdl/dp_mux.vhd
+++ b/libraries/base/dp/src/vhdl/dp_mux.vhd
@@ -134,7 +134,7 @@ architecture rtl of dp_mux is
constant c_sel_w : natural := true_log2(g_nof_input);
constant c_rl : natural := 1;
- signal tb_ready_reg : std_logic_vector(0 TO g_nof_input * (1 + c_rl) - 1);
+ signal tb_ready_reg : std_logic_vector(0 to g_nof_input * (1 + c_rl) - 1);
type state_type is (s_idle, s_output);
@@ -154,14 +154,14 @@ architecture rtl of dp_mux is
signal rd_siso_arr : t_dp_siso_arr(0 to g_nof_input - 1);
signal rd_sosi_arr : t_dp_sosi_arr(0 to g_nof_input - 1);
- signal rd_sosi_busy_arr : std_logic_vector(0 TO g_nof_input - 1);
+ signal rd_sosi_busy_arr : std_logic_vector(0 to g_nof_input - 1);
signal hold_src_in_arr : t_dp_siso_arr(0 to g_nof_input - 1);
signal next_src_out_arr : t_dp_sosi_arr(0 to g_nof_input - 1);
signal pend_src_out_arr : t_dp_sosi_arr(0 to g_nof_input - 1); -- SOSI control
- signal in_xon_arr : std_logic_vector(0 TO g_nof_input - 1);
- signal nxt_in_xon_arr : std_logic_vector(0 TO g_nof_input - 1);
+ signal in_xon_arr : std_logic_vector(0 to g_nof_input - 1);
+ signal nxt_in_xon_arr : std_logic_vector(0 to g_nof_input - 1);
signal prev_src_in : t_dp_siso;
signal src_out_hi : t_dp_sosi; -- snk_in_arr().channel as high part of src_out.channel
@@ -264,7 +264,7 @@ begin
end generate;
-- Register and adjust external MM sel_ctrl for g_sel_ctrl_invert
- nxt_sel_ctrl_reg <= sel_ctrl when g_sel_ctrl_invert = FALSE else g_nof_input - 1 -sel_ctrl;
+ nxt_sel_ctrl_reg <= sel_ctrl when g_sel_ctrl_invert = FALSE else g_nof_input - 1 - sel_ctrl;
-- Detect change in sel_ctrl
nxt_sel_ctrl_evt <= '1' when nxt_sel_ctrl_reg /= sel_ctrl_reg else '0';
diff --git a/libraries/base/dp/src/vhdl/dp_offload_tx_legacy.vhd b/libraries/base/dp/src/vhdl/dp_offload_tx_legacy.vhd
index b57259be8e58439fd802f719075a71bf9e86fccf..8b34a2cd886be25eb211767233f5dc4b4b5f2e8e 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_tx_legacy.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_tx_legacy.vhd
@@ -76,7 +76,7 @@ end dp_offload_tx_legacy;
architecture str of dp_offload_tx_legacy is
constant c_fifo_margin : natural := 10;
- constant c_dp_pkt_overhead_nof_words : natural := 4 +1;
+ constant c_dp_pkt_overhead_nof_words : natural := 4 + 1;
constant c_hdr_insert_reg_addr_w : natural := 1; -- Only 1 register used. A width of 1 still yields 2 addresses/instance though.
constant c_hdr_insert_ram_addr_w : natural := ceil_log2( g_hdr_nof_words * (g_data_w / c_word_w) );
diff --git a/libraries/base/dp/src/vhdl/dp_packet_dec.vhd b/libraries/base/dp/src/vhdl/dp_packet_dec.vhd
index 0ababd0db7807b9cc135ad899ec87502edee0b00..59f9ada3ae400323ae92499c6e62f19ec803c1dc 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_dec.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_dec.vhd
@@ -338,4 +338,4 @@ begin
end if;
end process;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/dp_packet_dec_channel_lo.vhd b/libraries/base/dp/src/vhdl/dp_packet_dec_channel_lo.vhd
index bcdc5040f90bc6a888d295f686410c2a5b5a7cae..c48813e86edc4b654137c181d1be0730c0886afd 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_dec_channel_lo.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_dec_channel_lo.vhd
@@ -87,10 +87,10 @@ begin
src_out.channel(g_channel_lo - 1 downto 0) <= channel_lo_hold; -- default combinatorially assign the held channel_lo bits to the sosi.channel field after the sop
if snk_in.sop = '1' then
-- clear the channel_lo bits in the MSWord of the CHAN field
- src_out.data(g_data_w - 2 downto g_data_w - 1 -g_channel_lo) <= (others=>'0');
+ src_out.data(g_data_w - 2 downto g_data_w - 1 - g_channel_lo) <= (others => '0');
-- extract the channel_lo bits from the MSWord of the CHAN field
- v_channel_lo := snk_in.data(g_data_w - 2 downto g_data_w - 1 -g_channel_lo);
+ v_channel_lo := snk_in.data(g_data_w - 2 downto g_data_w - 1 - g_channel_lo);
src_out.channel(g_channel_lo - 1 downto 0) <= v_channel_lo; -- combinatorially assign the channel_lo bits to the sosi.channel field at the sop
nxt_channel_lo_hold <= v_channel_lo; -- register the channel_lo bits so they can be assigned to the rest of the frame as well
end if;
diff --git a/libraries/base/dp/src/vhdl/dp_packet_enc.vhd b/libraries/base/dp/src/vhdl/dp_packet_enc.vhd
index 1d871798ae0d8c17c14247076f7c97a8f8eff879..38a935dd9f2c6a49fc1f51da44baa33a20d4f5dc 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_enc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_enc.vhd
@@ -102,7 +102,7 @@ architecture rtl of dp_packet_enc is
constant c_error_vec_w : natural := c_error_len * g_data_w;
constant c_rl : natural := 1;
- signal tb_ready_reg : std_logic_vector(0 TO c_rl);
+ signal tb_ready_reg : std_logic_vector(0 to c_rl);
type t_state is (s_channel, s_bsn, s_data, s_error);
diff --git a/libraries/base/dp/src/vhdl/dp_packet_enc_channel_lo.vhd b/libraries/base/dp/src/vhdl/dp_packet_enc_channel_lo.vhd
index eb439bf48a8f26c472ba2a8448973d03de3ebe25..29b2d8fc87a271804206b8ec51c795ca2cae3f7f 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_enc_channel_lo.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_enc_channel_lo.vhd
@@ -78,7 +78,7 @@ begin
src_out <= snk_in;
if g_channel_lo > 0 then
if snk_in.sop = '1' then
- src_out.data(g_data_w - 2 downto g_data_w - 1 -g_channel_lo) <= snk_in.channel(g_channel_lo-1 downto 0);
+ src_out.data(g_data_w - 2 downto g_data_w - 1 - g_channel_lo) <= snk_in.channel(g_channel_lo - 1 downto 0);
end if;
end if;
end process;
diff --git a/libraries/base/dp/src/vhdl/dp_packet_pkg.vhd b/libraries/base/dp/src/vhdl/dp_packet_pkg.vhd
index e33d1b464906106cce1309b64d7439b3997829b0..cbba6dd3385f774b6b2dec3cf9950c8f64c2356d 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_pkg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_pkg.vhd
@@ -69,4 +69,4 @@ package body dp_packet_pkg is
ceil_div(c_dp_packet_error_w, c_data_w);
end;
-end dp_packet_pkg;
+end dp_packet_pkg;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/dp_packetizing_pkg.vhd b/libraries/base/dp/src/vhdl/dp_packetizing_pkg.vhd
index d915d603310d9264a981f53bd10949600b6bce34..b2aa9a73d0720adf90ba9e869d7ba91fedf23b6d 100644
--- a/libraries/base/dp/src/vhdl/dp_packetizing_pkg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packetizing_pkg.vhd
@@ -142,4 +142,4 @@ package body dp_packetizing_pkg is
return nxt_crc;
end func_dp_next_crc;
-end dp_packetizing_pkg;
+end dp_packetizing_pkg;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/dp_ram_from_mm.vhd b/libraries/base/dp/src/vhdl/dp_ram_from_mm.vhd
index de8a354e6f905944fb16b9666c73fd5495934f10..8ae7c6b704fbbb4390d7048f151681c6a0e13122 100644
--- a/libraries/base/dp/src/vhdl/dp_ram_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_ram_from_mm.vhd
@@ -177,4 +177,4 @@ begin
rd_val => open
);
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/dp_ram_from_mm_reg.vhd b/libraries/base/dp/src/vhdl/dp_ram_from_mm_reg.vhd
index 56b965fad20cbab79ca7b74bd44a886ccd663ee6..fbe11f2a01ff7315b6ee951c2e80832c0360fe25 100644
--- a/libraries/base/dp/src/vhdl/dp_ram_from_mm_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_ram_from_mm_reg.vhd
@@ -82,4 +82,4 @@ begin
dout => dp_on
);
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/dp_ram_to_mm.vhd b/libraries/base/dp/src/vhdl/dp_ram_to_mm.vhd
index 070245f9b4aff9b590a80b0856bf6c091890a8d1..75a694f9a06bc6aeaf0e69181d3a2469a22469a2 100644
--- a/libraries/base/dp/src/vhdl/dp_ram_to_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_ram_to_mm.vhd
@@ -155,4 +155,4 @@ begin
rd_val => sla_out.rdval
);
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/dp_ready.vhd b/libraries/base/dp/src/vhdl/dp_ready.vhd
index 98da6b2a07fa6ec5802b895554f56317f53cf32a..a8a286d06deb4985f4d73db784455a476b38cbf0 100644
--- a/libraries/base/dp/src/vhdl/dp_ready.vhd
+++ b/libraries/base/dp/src/vhdl/dp_ready.vhd
@@ -83,4 +83,4 @@ begin
src_out.eop <= snk_in.eop and reg_val;
end process;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/dp_repack_data.vhd b/libraries/base/dp/src/vhdl/dp_repack_data.vhd
index d0dd31a629057a0a5a78311a78ce71e40eb9a909..67bbc6603005bfe15853aa57eb558f807ed2658c 100644
--- a/libraries/base/dp/src/vhdl/dp_repack_data.vhd
+++ b/libraries/base/dp/src/vhdl/dp_repack_data.vhd
@@ -680,8 +680,8 @@ architecture str of dp_repack_data is
signal i_src_out : t_dp_sosi;
signal src_out_data : std_logic_vector(g_out_dat_w - 1 downto 0);
- signal snk_out_ready_reg : std_logic_vector(0 TO c_dp_stream_rl);
- signal pack_ready_reg : std_logic_vector(0 TO c_dp_stream_rl);
+ signal snk_out_ready_reg : std_logic_vector(0 to c_dp_stream_rl);
+ signal pack_ready_reg : std_logic_vector(0 to c_dp_stream_rl);
begin
diff --git a/libraries/base/dp/src/vhdl/dp_requantize.vhd b/libraries/base/dp/src/vhdl/dp_requantize.vhd
index 5c1d280df3a9e73986966599a24cbfbc3c896187..26032c4c8c6c25f8734817bb9ef6f39776dc11d4 100644
--- a/libraries/base/dp/src/vhdl/dp_requantize.vhd
+++ b/libraries/base/dp/src/vhdl/dp_requantize.vhd
@@ -176,7 +176,7 @@ begin
begin
src_out <= snk_in_piped;
if g_complex = FALSE then
- if g_representation ="unsigned " then
+ if g_representation ="unsigned " then
src_out.data <= RESIZE_DP_DATA( quantized_data);
else
src_out.data <= RESIZE_DP_SDATA(quantized_data);
diff --git a/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd b/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd
index e75488ab153c79db1a0ce8a696d3a18b39a3e449..0bdf701eb616a642e530cd64601b9a36a1882563 100644
--- a/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd
@@ -270,7 +270,7 @@ package dp_stream_pkg is
function REPLICATE_DP_DATA( seq : std_logic_vector ) return std_logic_vector; -- replicate seq as often as fits in c_dp_stream_data_w
function UNREPLICATE_DP_DATA(data : std_logic_vector; seq_w : natural) return std_logic_vector; -- unreplicate data to width seq_w, return low seq_w bits and set mismatch MSbits bits to '1'
- function TO_DP_SOSI_unsigned(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : UNSIGNED) return t_dp_sosi_unsigned;
+ function TO_DP_SOSI_unsigned(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned;
-- Map between array and single element
function TO_DP_ARR(sosi : t_dp_sosi) return t_dp_sosi_arr;
@@ -627,7 +627,7 @@ package body dp_stream_pkg is
return v_vec(c_data_w - 1 downto 0);
end UNREPLICATE_DP_DATA;
- function TO_DP_SOSI_unsigned(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : UNSIGNED) return t_dp_sosi_unsigned is
+ function TO_DP_SOSI_unsigned(sync, valid, sop, eop : std_logic; bsn, data, re, im, empty, channel, err : unsigned) return t_dp_sosi_unsigned is
variable v_sosi_unsigned : t_dp_sosi_unsigned;
begin
v_sosi_unsigned.sync := sync;
@@ -798,8 +798,8 @@ package body dp_stream_pkg is
for I in dp'range loop
if mask(I) = '1' then
v_any := '1';
- if str ="READY " then v_vec(I) := dp(I).ready;
- elsif str ="XON " then v_vec(I) := dp(I).xon;
+ if str ="READY " then v_vec(I) := dp(I).ready;
+ elsif str ="XON " then v_vec(I) := dp(I).xon;
else report "Error in func_dp_stream_arr_and for t_dp_siso_arr";
end if;
end if;
@@ -820,10 +820,10 @@ package body dp_stream_pkg is
for I in dp'range loop
if mask(I) = '1' then
v_any := '1';
- if str ="VALID " then v_vec(I) := dp(I).valid;
- elsif str ="SOP " then v_vec(I) := dp(I).sop;
- elsif str ="EOP " then v_vec(I) := dp(I).eop;
- elsif str ="SYNC " then v_vec(I) := dp(I).sync;
+ if str ="VALID " then v_vec(I) := dp(I).valid;
+ elsif str ="SOP " then v_vec(I) := dp(I).sop;
+ elsif str ="EOP " then v_vec(I) := dp(I).eop;
+ elsif str ="SYNC " then v_vec(I) := dp(I).sync;
else report "Error in func_dp_stream_arr_and for t_dp_sosi_arr";
end if;
end if;
@@ -856,8 +856,8 @@ package body dp_stream_pkg is
for I in dp'range loop
if mask(I) = '1' then
v_any := '1';
- if str ="READY " then v_vec(I) := dp(I).ready;
- elsif str ="XON " then v_vec(I) := dp(I).xon;
+ if str ="READY " then v_vec(I) := dp(I).ready;
+ elsif str ="XON " then v_vec(I) := dp(I).xon;
else report "Error in func_dp_stream_arr_or for t_dp_siso_arr";
end if;
end if;
@@ -878,10 +878,10 @@ package body dp_stream_pkg is
for I in dp'range loop
if mask(I) = '1' then
v_any := '1';
- if str ="VALID " then v_vec(I) := dp(I).valid;
- elsif str ="SOP " then v_vec(I) := dp(I).sop;
- elsif str ="EOP " then v_vec(I) := dp(I).eop;
- elsif str ="SYNC " then v_vec(I) := dp(I).sync;
+ if str ="VALID " then v_vec(I) := dp(I).valid;
+ elsif str ="SOP " then v_vec(I) := dp(I).sop;
+ elsif str ="EOP " then v_vec(I) := dp(I).eop;
+ elsif str ="SYNC " then v_vec(I) := dp(I).sync;
else report "Error in func_dp_stream_arr_or for t_dp_sosi_arr";
end if;
end if;
@@ -913,8 +913,8 @@ package body dp_stream_pkg is
variable v_slv : std_logic_vector(dp'range) := slv; -- map to ensure same range as for dp
begin
for I in dp'range loop
- if str ="READY " then v_dp(I).ready := v_slv(I);
- elsif str ="XON " then v_dp(I).xon := v_slv(I);
+ if str ="READY " then v_dp(I).ready := v_slv(I);
+ elsif str ="XON " then v_dp(I).xon := v_slv(I);
else report "Error in func_dp_stream_arr_set for t_dp_siso_arr";
end if;
end loop;
@@ -927,15 +927,15 @@ package body dp_stream_pkg is
begin
for I in dp'range loop
-- use v_slv(I) to set individual sl field
- if str ="VALID " then v_dp(I).valid := v_slv(I);
- elsif str ="SOP " then v_dp(I).sop := v_slv(I);
- elsif str ="EOP " then v_dp(I).eop := v_slv(I);
- elsif str ="SYNC " then v_dp(I).sync := v_slv(I);
+ if str ="VALID " then v_dp(I).valid := v_slv(I);
+ elsif str ="SOP " then v_dp(I).sop := v_slv(I);
+ elsif str ="EOP " then v_dp(I).eop := v_slv(I);
+ elsif str ="SYNC " then v_dp(I).sync := v_slv(I);
-- use slv to set individual slv field
- elsif str ="BSN " then v_dp(I).bsn := RESIZE_DP_BSN(slv);
- elsif str ="CHANNEL " then v_dp(I).channel := RESIZE_DP_CHANNEL(slv);
- elsif str ="EMPTY " then v_dp(I).empty := RESIZE_DP_EMPTY(slv);
- elsif str ="ERR " then v_dp(I).err := RESIZE_DP_ERROR(slv);
+ elsif str ="BSN " then v_dp(I).bsn := RESIZE_DP_BSN(slv);
+ elsif str ="CHANNEL " then v_dp(I).channel := RESIZE_DP_CHANNEL(slv);
+ elsif str ="EMPTY " then v_dp(I).empty := RESIZE_DP_EMPTY(slv);
+ elsif str ="ERR " then v_dp(I).err := RESIZE_DP_ERROR(slv);
else report "Error in func_dp_stream_arr_set for t_dp_sosi_arr";
end if;
end loop;
@@ -958,8 +958,8 @@ package body dp_stream_pkg is
variable v_ctrl : std_logic_vector(dp'range);
begin
for I in dp'range loop
- if str ="READY " then v_ctrl(I) := dp(I).ready;
- elsif str ="XON " then v_ctrl(I) := dp(I).xon;
+ if str ="READY " then v_ctrl(I) := dp(I).ready;
+ elsif str ="XON " then v_ctrl(I) := dp(I).xon;
else report "Error in func_dp_stream_arr_get for t_dp_siso_arr";
end if;
end loop;
@@ -970,10 +970,10 @@ package body dp_stream_pkg is
variable v_ctrl : std_logic_vector(dp'range);
begin
for I in dp'range loop
- if str ="VALID " then v_ctrl(I) := dp(I).valid;
- elsif str ="SOP " then v_ctrl(I) := dp(I).sop;
- elsif str ="EOP " then v_ctrl(I) := dp(I).eop;
- elsif str ="SYNC " then v_ctrl(I) := dp(I).sync;
+ if str ="VALID " then v_ctrl(I) := dp(I).valid;
+ elsif str ="SOP " then v_ctrl(I) := dp(I).sop;
+ elsif str ="EOP " then v_ctrl(I) := dp(I).eop;
+ elsif str ="SYNC " then v_ctrl(I) := dp(I).sync;
else report "Error in func_dp_stream_arr_get for t_dp_sosi_arr";
end if;
end loop;
@@ -1312,12 +1312,12 @@ package body dp_stream_pkg is
function func_dp_stream_set_data(dp : t_dp_sosi; slv : std_logic_vector; str : string) return t_dp_sosi is
variable v_dp : t_dp_sosi := dp;
begin
- if str ="DATA " then v_dp.data := RESIZE_DP_DATA(slv);
- elsif str ="DSP " then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ if str ="DATA " then v_dp.data := RESIZE_DP_DATA(slv);
+ elsif str ="DSP " then v_dp.re := RESIZE_DP_DSP_DATA(slv);
v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str ="RE " then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- elsif str ="IM " then v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str ="all " then v_dp.data := RESIZE_DP_DATA(slv);
+ elsif str ="RE " then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ elsif str ="IM " then v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str ="all " then v_dp.data := RESIZE_DP_DATA(slv);
v_dp.re := RESIZE_DP_DSP_DATA(slv);
v_dp.im := RESIZE_DP_DSP_DATA(slv);
else report "Error in func_dp_stream_set_data for t_dp_sosi";
@@ -1487,10 +1487,10 @@ package body dp_stream_pkg is
v_src_out.im := (others => '0');
for i in 0 to nof_data - 1 loop
v_in_data := snk_in.data((i + 1) * in_w - 1 downto i * in_w);
- if data_representation ="unsigned " then -- treat data as unsigned
+ if data_representation ="unsigned " then -- treat data as unsigned
v_out_data := RESIZE_UVEC(v_in_data, out_w);
else
- if data_representation ="signed " then -- treat data as signed
+ if data_representation ="signed " then -- treat data as signed
v_out_data := RESIZE_SVEC(v_in_data, out_w);
else
-- treat data as complex
@@ -1573,4 +1573,4 @@ package body dp_stream_pkg is
end;
-end dp_stream_pkg;
+end dp_stream_pkg;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/dp_sync_checker.vhd b/libraries/base/dp/src/vhdl/dp_sync_checker.vhd
index e3e2b432ba69608490d1aee1f6be1d93c58ae6a2..55fc67e7fb200bd79ed0f6debb8d4dec537bb4d6 100644
--- a/libraries/base/dp/src/vhdl/dp_sync_checker.vhd
+++ b/libraries/base/dp/src/vhdl/dp_sync_checker.vhd
@@ -175,5 +175,4 @@ begin
nof_early_syncs <= to_uvec(r.nof_early_syncs, c_word_w);
nof_late_syncs <= to_uvec(r.nof_late_syncs, c_word_w);
-end str;
-
+end str;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/dp_throttle.vhd b/libraries/base/dp/src/vhdl/dp_throttle.vhd
index 771e73e043d34e52d21777dcb9686e8d580185be..14731017260dfe76f803c998667fc3c262285d77 100644
--- a/libraries/base/dp/src/vhdl/dp_throttle.vhd
+++ b/libraries/base/dp/src/vhdl/dp_throttle.vhd
@@ -82,4 +82,4 @@ begin
);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/dp_throttle_sop.vhd b/libraries/base/dp/src/vhdl/dp_throttle_sop.vhd
index f22852e30fd248c36a23f51bb82c1b34aba4da07..01f5978c4b0fc601245b69050035ae0ea4d2437b 100644
--- a/libraries/base/dp/src/vhdl/dp_throttle_sop.vhd
+++ b/libraries/base/dp/src/vhdl/dp_throttle_sop.vhd
@@ -93,4 +93,4 @@ begin
switch_low <= snk_in.eop;
snk_out.ready <= switch_out;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/dp_throttle_xon.vhd b/libraries/base/dp/src/vhdl/dp_throttle_xon.vhd
index 5320736f79e0fd2d4f0fae06f2f155340922eb92..89c91007893f4346ef092d463ab6e34bee06df3d 100644
--- a/libraries/base/dp/src/vhdl/dp_throttle_xon.vhd
+++ b/libraries/base/dp/src/vhdl/dp_throttle_xon.vhd
@@ -121,4 +121,4 @@ begin
end if;
end process;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/dp_unfolder.vhd b/libraries/base/dp/src/vhdl/dp_unfolder.vhd
index 7ac3de9cc8a3ebf682094a91e7ccc362bc0a6d84..0c6e03b93bb3ba6a322b178741a63bc2a7aa8f3e 100644
--- a/libraries/base/dp/src/vhdl/dp_unfolder.vhd
+++ b/libraries/base/dp/src/vhdl/dp_unfolder.vhd
@@ -266,4 +266,4 @@ begin
dp_block_gen_snk_in_arr <= snk_in_arr;
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/dp_wideband_sp_arr_scope.vhd b/libraries/base/dp/src/vhdl/dp_wideband_sp_arr_scope.vhd
index 919ca488238c67cb2f94bcff33481e46c8f3ef05..7dda12cee4fc4553b3eab77ca7b02d146e7b6417 100644
--- a/libraries/base/dp/src/vhdl/dp_wideband_sp_arr_scope.vhd
+++ b/libraries/base/dp/src/vhdl/dp_wideband_sp_arr_scope.vhd
@@ -102,7 +102,7 @@ begin
begin
if rising_edge(SCLKi) then
if g_wideband_big_endian = TRUE then
- vI := g_wideband_factor - 1 -scope_cnt_arr(I);
+ vI := g_wideband_factor - 1 - scope_cnt_arr(I);
else
vI := scope_cnt_arr(I);
end if;
diff --git a/libraries/base/dp/src/vhdl/dp_wideband_wb_arr_scope.vhd b/libraries/base/dp/src/vhdl/dp_wideband_wb_arr_scope.vhd
index eae5439074be6302eb22d1a07d73572d68256309..e43612e520308ee01db8fea2eb82566d33e1dca0 100644
--- a/libraries/base/dp/src/vhdl/dp_wideband_wb_arr_scope.vhd
+++ b/libraries/base/dp/src/vhdl/dp_wideband_wb_arr_scope.vhd
@@ -90,7 +90,7 @@ begin
begin
if rising_edge(SCLKi) then
if g_wideband_big_endian = TRUE then
- st_sosi <= wb_sosi_arr(g_wideband_factor - 1 -sample_cnt);
+ st_sosi <= wb_sosi_arr(g_wideband_factor - 1 - sample_cnt);
else
st_sosi <= wb_sosi_arr(sample_cnt);
end if;
diff --git a/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd b/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd
index 3414a80eb6fe2e8ab3999de048283f8c84727559..6ef9f7eaaff55500d2a56aadd6d3d6e27cae8f48 100644
--- a/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd
@@ -253,4 +253,4 @@ begin
out_sosi_arr => i_out_sosi_arr
);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
index cf83fd83303ff3f7d01a6ce1abb0cf662c1352b9..c8b57e1ab10997d9b146a1d9f62a8c749660747d 100644
--- a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
@@ -220,4 +220,4 @@ begin
out_enable => out_enable
);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/mms_dp_block_select.vhd b/libraries/base/dp/src/vhdl/mms_dp_block_select.vhd
index 83c1afe55ba39cace1927459bf548ff10842be01..eb50b9afed2877b54ad559604bfb378ea3eeb760 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_block_select.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_block_select.vhd
@@ -118,4 +118,4 @@ begin
);
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_align.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_align.vhd
index fb1745fd7eda0142c4e87853167c562844dac15c..9e194beaf0ee99097f5bd256410f6ae6d18bd77a 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_align.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_align.vhd
@@ -112,4 +112,4 @@ begin
out_en_arr => en_arr
);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor.vhd
index e9a144a368ad8551ba524c34949370cdccc9f887..4c3aea5d9fa47efd7e900bc5f2b68e1fe674fd93 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor.vhd
@@ -165,4 +165,4 @@ begin
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor_v2.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor_v2.vhd
index 526fa616399aac0c1e39fb504f3d28459bdcede9..808c2ebfd42fe17a8e4e1af86eb9e92410f47ea1 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor_v2.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor_v2.vhd
@@ -162,4 +162,4 @@ begin
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_scheduler.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_scheduler.vhd
index cbd78e4795195e316dacab78f8c0db9001d8a18f..70d12fb2ab99dccf1cfda86b606d960bf8940d89 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_scheduler.vhd
@@ -92,4 +92,4 @@ begin
trigger_out => trigger_out
);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_source.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_source.vhd
index cc7578a622672ff537d592ca8e2993553ec353d0..eeeb045731989f1b4f29263fb00c353e26a7435b 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_source.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_source.vhd
@@ -120,4 +120,4 @@ begin
--capture_bsn <= i_bs_sosi.bsn WHEN rising_edge(dp_clk) AND dp_pps='1'; -- capture BSN at external PPS
capture_bsn <= i_bs_sosi.bsn when rising_edge(dp_clk) and i_bs_sosi.sync = '1'; -- capture BSN at internal sync
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd
index 7d60537ccf0aa2bfc39cf95fc985a06097f95d4d..fecab0a6dd84c6de7d5ba79204ec7f43db510c29 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd
@@ -129,4 +129,4 @@ begin
capture_bsn <= i_bs_sosi.bsn when rising_edge(dp_clk) and i_bs_sosi.sync = '1'; -- capture BSN at internal sync
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/mms_dp_fifo_from_mm.vhd b/libraries/base/dp/src/vhdl/mms_dp_fifo_from_mm.vhd
index 1770cf6369af4a521485d9054d1c2e6f397ddbdb..ff81df4f98f03de9b21207ae467f2122ab924990 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_fifo_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_fifo_from_mm.vhd
@@ -89,4 +89,4 @@ begin
mm_wr_data <= data_mosi.wrdata(c_word_w - 1 downto 0);
mm_wr <= data_mosi.wr;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/mms_dp_fifo_to_mm.vhd b/libraries/base/dp/src/vhdl/mms_dp_fifo_to_mm.vhd
index d0e26d647b65fbd80f111c71e62f4b2670e7436e..4827f94deea14e5962d83efa9f49bf942c2027c2 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_fifo_to_mm.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_fifo_to_mm.vhd
@@ -92,4 +92,4 @@ begin
data_miso.rdval <= mm_rd_val;
mm_rd <= data_mosi.rd;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel.vhd b/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel.vhd
index 78e35a98305c7c828d04452a749133d0b8f3df5a..4dc09a8f6eec2d13dcf7b4f532852056c05beb7f 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel.vhd
@@ -161,4 +161,4 @@ begin
src_in => src_in,
src_out => src_out
);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel_arr.vhd
index e8b50f898a2603963503842baaa421b4fc9583bf..0050c8c20c5eb2c67b911c8af05e4c58e4750e4e 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel_arr.vhd
@@ -130,4 +130,4 @@ begin
src_out => src_out_arr(I)
);
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/mms_dp_force_data_serial.vhd b/libraries/base/dp/src/vhdl/mms_dp_force_data_serial.vhd
index a9ee0579de5f9d0cbd31a68ee2c4a86e3c5a08ef..252f607e6351da556df50db762dfe62409ecbf46 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_force_data_serial.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_force_data_serial.vhd
@@ -170,4 +170,4 @@ begin
src_out => src_out
);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/mms_dp_force_data_serial_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_force_data_serial_arr.vhd
index a0df780adabecbe0bb1bbd09918c1e8c75b3bc33..ef06ebcb5887545fc7cabd6c3ce9779daf7f7e05 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_force_data_serial_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_force_data_serial_arr.vhd
@@ -111,4 +111,4 @@ begin
src_out => src_out_arr(I)
);
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/mms_dp_gain.vhd b/libraries/base/dp/src/vhdl/mms_dp_gain.vhd
index 55337351d005eabfb089c0f0df4e112d2a88eb3d..0e38a22c98015765ab17fb9fe8438595239df656 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_gain.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_gain.vhd
@@ -132,4 +132,4 @@ begin
out_sosi_arr => out_sosi_arr
);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/mms_dp_gain_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_gain_arr.vhd
index a026b896e32ee443f939dec6939dcb948607448b..2b94d221666ac5c0b9fdec68f53f1901153fcc76 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_gain_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_gain_arr.vhd
@@ -286,4 +286,4 @@ begin
end generate gen_nof_streams;
end generate gen_complex_multiply;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/mms_dp_gain_serial.vhd b/libraries/base/dp/src/vhdl/mms_dp_gain_serial.vhd
index 6b9a5c5c7a8fe0e581b24d46de5c474d91b2a95c..f0eea0b206161c0238e806f3820affe2c282dfd7 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_gain_serial.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_gain_serial.vhd
@@ -129,4 +129,4 @@ begin
out_sosi_arr => out_sosi_arr
);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/mms_dp_packet_merge.vhd b/libraries/base/dp/src/vhdl/mms_dp_packet_merge.vhd
index 6e12b88af01a892cd02aa7a790b8834415a2db1d..652fc69c39b03f681802398f1fa9a1f3f2c5fde1 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_packet_merge.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_packet_merge.vhd
@@ -122,4 +122,4 @@ begin
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/mms_dp_split.vhd b/libraries/base/dp/src/vhdl/mms_dp_split.vhd
index c1ddf3f2cd689dcca9a33362089fc11697e1380c..26358026fd41bff2cbb44037b2d38c0881b78124 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_split.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_split.vhd
@@ -120,4 +120,4 @@ begin
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/mms_dp_sync_checker.vhd b/libraries/base/dp/src/vhdl/mms_dp_sync_checker.vhd
index 36b60d53872296968d1f89ed5bcdff45c554a21f..14a4faca1a287205aa32f51a59cc68dc4ceb8be1 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_sync_checker.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_sync_checker.vhd
@@ -143,5 +143,4 @@ begin
out_new => open
);
-end str;
-
+end str;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/mms_dp_sync_checker_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_sync_checker_arr.vhd
index 7ce857589d16bc94645f080ce1f46938b7e48db5..b16ca9183d453ddf80e13a1f034cbd2df5585b73 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_sync_checker_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_sync_checker_arr.vhd
@@ -123,5 +123,4 @@ begin
end loop;
end process;
-end str;
-
+end str;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/mms_dp_throttle.vhd b/libraries/base/dp/src/vhdl/mms_dp_throttle.vhd
index 857630f0775485a34c8b2da370f658d75f3fabd7..2da8ae77c45e99a5b542abfaa82deeed4e6893f4 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_throttle.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_throttle.vhd
@@ -92,4 +92,4 @@ begin
throttle => throttle
);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/dp/src/vhdl/mms_dp_xonoff.vhd b/libraries/base/dp/src/vhdl/mms_dp_xonoff.vhd
index 3515f37623a809ce9ea7c1d263249ac1ac3906c0..917227a89df1fe789da3908f4bddb795388e5c88 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_xonoff.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_xonoff.vhd
@@ -158,5 +158,4 @@ begin
);
end generate;
-end str;
-
+end str;
\ No newline at end of file
diff --git a/libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd b/libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd
index 82ad52425c2d405c91f4e75b421e58cbca021462..7065cc7014db06f176c922d7016c449105c00376 100644
--- a/libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd
@@ -112,7 +112,7 @@ architecture tb of tb2_dp_mux is
type t_ctrl_2arr is array (0 to c_nof_type -1, 0 to c_nof_input - 1) of std_logic;
type t_data_2arr is array (0 to c_nof_type -1, 0 to c_nof_input - 1) of std_logic_vector(c_data_w - 1 downto 0);
- type t_rl_vec_2arr is array (0 to c_nof_type -1, 0 to c_nof_input - 1) of std_logic_vector(0 TO c_rl);
+ type t_rl_vec_2arr is array (0 to c_nof_type -1, 0 to c_nof_input - 1) of std_logic_vector(0 to c_rl);
signal tb_end_vec : std_logic_vector(c_nof_streams - 1 downto 0) := (others => '0');
signal tb_end : std_logic;
diff --git a/libraries/base/dp/tb/vhdl/tb3_dp_demux.vhd b/libraries/base/dp/tb/vhdl/tb3_dp_demux.vhd
index 4c987504136eaf9a7a9c77725252e2f3e200e5f9..264fece062305c972701f353ce374e3879e5664e 100644
--- a/libraries/base/dp/tb/vhdl/tb3_dp_demux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb3_dp_demux.vhd
@@ -97,7 +97,7 @@ architecture tb of tb3_dp_demux is
signal verify_done : std_logic := '0';
signal count_eop : natural := 0;
- signal prev_out_ready : std_logic_vector(0 TO c_rl);
+ signal prev_out_ready : std_logic_vector(0 to c_rl);
signal prev_out_data : std_logic_vector(c_data_w - 1 downto 0) := to_svec(c_data_init -1, c_data_w);
signal out_data : std_logic_vector(c_data_w - 1 downto 0);
signal out_val : std_logic;
diff --git a/libraries/base/dp/tb/vhdl/tb3_dp_mux.vhd b/libraries/base/dp/tb/vhdl/tb3_dp_mux.vhd
index 69fe45e141a83d3b89b63b7ab21bd33faf4a855f..3b8b782d58e91117f4177c88c7d5f5947a087026 100644
--- a/libraries/base/dp/tb/vhdl/tb3_dp_mux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb3_dp_mux.vhd
@@ -92,7 +92,7 @@ architecture tb of tb3_dp_mux is
signal verify_done : std_logic := '0';
signal count_eop : natural := 0;
- signal prev_out_ready : std_logic_vector(0 TO c_rl);
+ signal prev_out_ready : std_logic_vector(0 to c_rl);
signal prev_out_data : std_logic_vector(c_data_w - 1 downto 0) := to_svec(c_data_init -1, c_data_w);
signal out_data : std_logic_vector(c_data_w - 1 downto 0);
signal out_val : std_logic;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_gen.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_gen.vhd
index e58c331ffe9e25247cfc11d4a3ef955e66df2493..2670d0c3dcf016d453897defe15fea7f9146d5e8 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_gen.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_gen.vhd
@@ -72,7 +72,7 @@ architecture tb of tb_dp_block_gen is
signal out_siso : t_dp_siso := c_dp_siso_rdy;
signal out_sosi : t_dp_sosi;
signal prev_out_sosi : t_dp_sosi;
- signal prev_out_ready : std_logic_vector(0 TO c_rl);
+ signal prev_out_ready : std_logic_vector(0 to c_rl);
signal out_gap : std_logic := '0';
signal hold_sop : std_logic := '0';
signal exp_size : natural := g_nof_data_per_block;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_align.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_align.vhd
index 2bb90c68ee8363cb3351ca77669a07c324d6166b..d8a4df2ca7f26ffaeecd21054b26aa47e246ce1b 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_align.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_align.vhd
@@ -83,7 +83,7 @@ architecture tb of tb_dp_bsn_align is
type t_bsn_arr is array (g_nof_input - 1 downto 0) of std_logic_vector(c_bsn_w - 1 downto 0);
type t_err_arr is array (g_nof_input - 1 downto 0) of std_logic_vector(c_dp_stream_error_w - 1 downto 0);
type t_channel_arr is array (g_nof_input - 1 downto 0) of std_logic_vector(c_dp_stream_channel_w - 1 downto 0);
- type t_rl_vec_arr is array (g_nof_input - 1 downto 0) of std_logic_vector(0 TO c_rl);
+ type t_rl_vec_arr is array (g_nof_input - 1 downto 0) of std_logic_vector(0 to c_rl);
type t_tb_state is (s_idle, s_bsn_mis_aligned, s_bsn_aligned, s_small_bsn_diff, s_large_bsn_diff, s_restore_bsn, s_disable_one_input, s_enable_inputs);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor.vhd
index ddaa5f01f9dd45bc310e31a5662ab4d662ea29ff..be3300b52aee1e63483bdb63cc805fda7b4905a6 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor.vhd
@@ -98,7 +98,7 @@ architecture tb of tb_dp_bsn_monitor is
signal verify_done : std_logic := '0';
signal count_eop : natural := 0;
- signal prev_in_ready : std_logic_vector(0 TO c_rl);
+ signal prev_in_ready : std_logic_vector(0 to c_rl);
signal prev_in_data : std_logic_vector(c_data_w - 1 downto 0) := to_svec(c_data_init -1, c_data_w);
signal in_bsn : std_logic_vector(c_word_w - 1 downto 0);
signal in_data : std_logic_vector(c_data_w - 1 downto 0);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor_v2.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor_v2.vhd
index 3bd15ef4ae1e296a73879cc709379bc5fa10b030..03faa63c7763be556ceea1c619ce30180dbf0adf 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor_v2.vhd
@@ -100,7 +100,7 @@ architecture tb of tb_dp_bsn_monitor_v2 is
signal verify_done : std_logic := '0';
signal count_eop : natural := 0;
- signal prev_in_ready : std_logic_vector(0 TO c_rl);
+ signal prev_in_ready : std_logic_vector(0 to c_rl);
signal prev_in_data : std_logic_vector(c_data_w - 1 downto 0) := to_svec(c_data_init -1, c_data_w);
signal in_bsn : std_logic_vector(c_word_w - 1 downto 0);
signal in_data : std_logic_vector(c_data_w - 1 downto 0);
@@ -262,7 +262,7 @@ begin
ref_sync <= '0';
proc_common_wait_until_low(clk, rst);
proc_common_wait_until_hi_lo(clk, in_sosi.sync);
- proc_common_wait_some_cycles(clk, (c_sync_timeout - 2 -c_ref_sync_latency));
+ proc_common_wait_some_cycles(clk, (c_sync_timeout - 2 - c_ref_sync_latency));
for I in 0 to c_nof_repeat - 2 loop
ref_sync <= '1';
proc_common_wait_some_cycles(clk, 1);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_concat.vhd b/libraries/base/dp/tb/vhdl/tb_dp_concat.vhd
index 509926ce5c7aa78ca66fc2b2f32f4152d7e3f299..2f86c7500395bba9548726ed28cbaf5b1798c167 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_concat.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_concat.vhd
@@ -57,7 +57,7 @@ architecture tb of tb_dp_concat is
signal random_1 : std_logic_vector(15 downto 0) := (others => '0');
signal random_2 : std_logic_vector(17 downto 0) := (others => '0');
- signal in_en : std_logic_vector(0 TO 1) := (others => '1');
+ signal in_en : std_logic_vector(0 to 1) := (others => '1');
signal in_siso_arr : t_dp_siso_arr(0 to 1);
signal in_sosi_arr : t_dp_sosi_arr(0 to 1) := (others => c_dp_sosi_rst);
signal out_siso : t_dp_siso := c_dp_siso_rdy;
@@ -79,7 +79,7 @@ architecture tb of tb_dp_concat is
signal out_val : std_logic;
signal out_sop : std_logic;
signal out_eop : std_logic;
- signal prev_out_ready : std_logic_vector(0 TO c_rl);
+ signal prev_out_ready : std_logic_vector(0 to c_rl);
signal prev_out_data : std_logic_vector(g_data_w - 1 downto 0);
signal expected_data : std_logic_vector(g_data_w - 1 downto 0);
signal hold_out_sop : std_logic;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_concat_field_blk.vhd b/libraries/base/dp/tb/vhdl/tb_dp_concat_field_blk.vhd
index 52588b2667d526e5c7eb318b993a1f323a5e49cb..7c49e9242fa0c4aea94da85a937dc7bc6603104b 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_concat_field_blk.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_concat_field_blk.vhd
@@ -92,7 +92,7 @@ architecture tb of tb_dp_concat_field_blk is
-- Tx offload
-----------------------------------------------------------------------------
-- From apertif_udp_offload_pkg.vhd:
- constant c_udp_offload_nof_hdr_fields : natural := 3 +12 + 4 + 3; -- 448b; 7 64b words
+ constant c_udp_offload_nof_hdr_fields : natural := 3 + 12 + 4 + 3; -- 448b; 7 64b words
-- Notes:
-- . pre-calculated ip_header_checksum is valid only for UNB0, FN0 targeting IP 10.10.10.10
-- . udp_total_length = 176 beamlets * 64b / 8b = 1408B + 14 DP bytes + 8 UDP bytes = 1430B
@@ -122,7 +122,7 @@ architecture tb of tb_dp_concat_field_blk is
-- From apertif_unb1_fn_beamformer_udp_offload.vhd:
-- Override ('1') only the Ethernet fields so we can use MM defaults there.
- constant c_hdr_field_ovr_init : std_logic_vector(c_udp_offload_nof_hdr_fields - 1 downto 0) := "101" &"111111111111 " &"1111 " &"100 ";
+ constant c_hdr_field_ovr_init : std_logic_vector(c_udp_offload_nof_hdr_fields - 1 downto 0) := "101" &"111111111111 " &"1111 " &"100 ";
constant c_NODE_ID : std_logic_vector(7 downto 0) := to_uvec(0, 8);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_demux.vhd b/libraries/base/dp/tb/vhdl/tb_dp_demux.vhd
index 8f216ab7e5adb605af071e4d589e4321f4b2a937..f5180cc04304d05c4f283f495c54badec8c3023d 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_demux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_demux.vhd
@@ -66,36 +66,36 @@ architecture tb of tb_dp_demux is
constant c_random_w : natural := 19;
- signal tb_end_vec : std_logic_vector(0 TO g_dut_nof_output - 1) := (others => '0');
+ signal tb_end_vec : std_logic_vector(0 to g_dut_nof_output - 1) := (others => '0');
signal tb_end : std_logic := '0';
signal clk : std_logic := '0';
signal rst : std_logic;
signal sync : std_logic;
- signal sync_dly : std_logic_vector(0 TO g_dut_nof_output - 1);
+ signal sync_dly : std_logic_vector(0 to g_dut_nof_output - 1);
signal lfsr1 : t_dp_data_arr(0 to g_dut_nof_output - 1) := (others => (others => '0'));
signal lfsr2 : t_dp_data_arr(0 to g_dut_nof_output - 1) := (others => (others => '0'));
signal cnt_dat : t_dp_data_arr(0 to g_dut_nof_output - 1);
- signal cnt_val : std_logic_vector(0 TO g_dut_nof_output - 1);
- signal cnt_en : std_logic_vector(0 TO g_dut_nof_output - 1);
+ signal cnt_val : std_logic_vector(0 to g_dut_nof_output - 1);
+ signal cnt_en : std_logic_vector(0 to g_dut_nof_output - 1);
type t_dp_state_enum_arr is array (natural range <> ) of t_dp_state_enum;
type t_tx_data_arr_arr is array (natural range <> ) of t_dp_data_arr( 0 to c_tx_latency + c_tx_void);
- type t_tx_val_arr_arr is array (natural range <> ) of std_logic_vector(0 TO c_tx_latency + c_tx_void);
+ type t_tx_val_arr_arr is array (natural range <> ) of std_logic_vector(0 to c_tx_latency + c_tx_void);
- type t_prev_out_ready_arr_arr is array (natural range <> ) of std_logic_vector(0 TO c_rx_latency);
+ type t_prev_out_ready_arr_arr is array (natural range <> ) of std_logic_vector(0 to c_rx_latency);
signal tx_data : t_tx_data_arr_arr(0 to g_dut_nof_output - 1) := (others => (others => (others => '0')));
signal tx_val : t_tx_val_arr_arr( 0 to g_dut_nof_output - 1) := (others => (others => '0'));
- signal in_ready : std_logic_vector(0 TO g_dut_nof_output - 1);
+ signal in_ready : std_logic_vector(0 to g_dut_nof_output - 1);
signal in_data : t_dp_data_arr(0 to g_dut_nof_output - 1) := (others => (others => '0'));
signal in_empty : t_dp_data_arr(0 to g_dut_nof_output - 1) := (others => (others => '0'));
signal in_channel : t_dp_data_arr(0 to g_dut_nof_output - 1) := (others => (others => '0'));
- signal in_val : std_logic_vector(0 TO g_dut_nof_output - 1);
- signal in_sop : std_logic_vector(0 TO g_dut_nof_output - 1);
- signal in_eop : std_logic_vector(0 TO g_dut_nof_output - 1);
+ signal in_val : std_logic_vector(0 to g_dut_nof_output - 1);
+ signal in_sop : std_logic_vector(0 to g_dut_nof_output - 1);
+ signal in_eop : std_logic_vector(0 to g_dut_nof_output - 1);
signal in_data_vec : std_logic_vector(g_dut_nof_output * c_dp_data_w - 1 downto 0) := (others => '0');
signal in_empty_vec : std_logic_vector(g_dut_nof_output * c_dp_data_w - 1 downto 0) := (others => '0');
@@ -116,22 +116,22 @@ architecture tb of tb_dp_demux is
signal demux_eop : std_logic_vector(g_dut_nof_output - 1 downto 0);
signal demux_ready : std_logic_vector(g_dut_nof_output - 1 downto 0);
- signal out_ready : std_logic_vector( 0 TO g_dut_nof_output - 1);
+ signal out_ready : std_logic_vector( 0 to g_dut_nof_output - 1);
signal prev_out_ready : t_prev_out_ready_arr_arr(0 to g_dut_nof_output - 1);
signal out_data : t_dp_data_arr(0 to g_dut_nof_output - 1) := (others => (others => '0'));
signal out_empty : t_dp_data_arr(0 to g_dut_nof_output - 1) := (others => (others => '0'));
signal out_channel : t_dp_data_arr(0 to g_dut_nof_output - 1) := (others => (others => '0'));
- signal out_val : std_logic_vector(0 TO g_dut_nof_output - 1);
- signal out_sop : std_logic_vector(0 TO g_dut_nof_output - 1);
- signal out_eop : std_logic_vector(0 TO g_dut_nof_output - 1);
- signal hold_out_sop : std_logic_vector(0 TO g_dut_nof_output - 1);
+ signal out_val : std_logic_vector(0 to g_dut_nof_output - 1);
+ signal out_sop : std_logic_vector(0 to g_dut_nof_output - 1);
+ signal out_eop : std_logic_vector(0 to g_dut_nof_output - 1);
+ signal hold_out_sop : std_logic_vector(0 to g_dut_nof_output - 1);
signal prev_out_data : t_dp_data_arr(0 to g_dut_nof_output - 1) := (others => (others => '0'));
signal state : t_dp_state_enum_arr(0 to g_dut_nof_output - 1);
signal verify_en : std_logic;
- signal verify_done : std_logic_vector(0 TO g_dut_nof_output - 1);
+ signal verify_done : std_logic_vector(0 to g_dut_nof_output - 1);
signal exp_data : std_logic_vector(c_dp_data_w - 1 downto 0) := to_uvec(5000, c_dp_data_w);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_distribute.vhd b/libraries/base/dp/tb/vhdl/tb_dp_distribute.vhd
index e91bf2fe0e16c109375f3be3f6b72e4b5e7bbbd9..9137c6dbfe74dc14f881f642ccc116a629177bc3 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_distribute.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_distribute.vhd
@@ -92,9 +92,9 @@ architecture tb of tb_dp_distribute is
constant c_rx_use_fifo_link_channel_lo : boolean := not g_code_channel_lo; -- FALSE when the link_channel_lo is coded in the CHAN field of the DP packet data, else it needs to go in parallel through the Rx FIFO
subtype t_data_arr is t_slv_16_arr(0 to g_nof_input - 1); -- width 16 must match c_data_w
- type t_rl_vec_arr is array (0 to g_nof_input - 1) of std_logic_vector(0 TO c_rl);
+ type t_rl_vec_arr is array (0 to g_nof_input - 1) of std_logic_vector(0 to c_rl);
- signal tb_end_vec : std_logic_vector(0 TO g_nof_input - 1) := (others => '0');
+ signal tb_end_vec : std_logic_vector(0 to g_nof_input - 1) := (others => '0');
signal tb_end : std_logic;
signal clk : std_logic := '1';
signal rst : std_logic := '1';
@@ -116,9 +116,9 @@ architecture tb of tb_dp_distribute is
signal out_siso_arr : t_dp_siso_arr(0 to g_nof_input - 1);
signal out_sosi_arr : t_dp_sosi_arr(0 to g_nof_input - 1);
- signal verify_en : std_logic_vector(0 TO g_nof_input - 1) := (others => '0');
- signal verify_done : std_logic_vector(0 TO g_nof_input - 1) := (others => '0');
- signal verify_end : std_logic_vector(0 TO g_nof_input - 1) := (others => '0');
+ signal verify_en : std_logic_vector(0 to g_nof_input - 1) := (others => '0');
+ signal verify_done : std_logic_vector(0 to g_nof_input - 1) := (others => '0');
+ signal verify_end : std_logic_vector(0 to g_nof_input - 1) := (others => '0');
signal count_eop : t_integer_arr(0 to g_nof_input - 1) := (others => 0);
signal prev_count_eop : t_integer_arr(0 to g_nof_input - 1) := (others => 0);
@@ -126,11 +126,11 @@ architecture tb of tb_dp_distribute is
signal prev_out_data : t_data_arr := array_init(c_data_init -1, g_nof_input, g_data_init_offset);
signal out_bsn : t_data_arr;
signal out_data : t_data_arr;
- signal out_sync : std_logic_vector(0 TO g_nof_input - 1);
- signal out_val : std_logic_vector(0 TO g_nof_input - 1);
- signal out_sop : std_logic_vector(0 TO g_nof_input - 1);
- signal out_eop : std_logic_vector(0 TO g_nof_input - 1);
- signal hold_out_sop : std_logic_vector(0 TO g_nof_input - 1);
+ signal out_sync : std_logic_vector(0 to g_nof_input - 1);
+ signal out_val : std_logic_vector(0 to g_nof_input - 1);
+ signal out_sop : std_logic_vector(0 to g_nof_input - 1);
+ signal out_eop : std_logic_vector(0 to g_nof_input - 1);
+ signal hold_out_sop : std_logic_vector(0 to g_nof_input - 1);
signal expected_out_data : t_data_arr;
begin
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc.vhd
index cca72dc7059f4c61057f4515a210f5ae14dc7920..7a7ec5409cdb873c51f19d526b2acd8355f40685 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc.vhd
@@ -81,7 +81,7 @@ architecture tb of tb_dp_fifo_dc is
signal cnt_en : std_logic;
signal tx_data : t_dp_data_arr(0 to c_tx_latency + c_tx_void) := (others => (others => '0'));
- signal tx_val : std_logic_vector(0 TO c_tx_latency + c_tx_void) := (others => '0');
+ signal tx_val : std_logic_vector(0 to c_tx_latency + c_tx_void) := (others => '0');
signal in_ready : std_logic;
signal in_data : std_logic_vector(c_dp_data_w - 1 downto 0) := (others => '0');
@@ -99,7 +99,7 @@ architecture tb of tb_dp_fifo_dc is
signal out_sosi : t_dp_sosi;
signal out_ready : std_logic;
- signal prev_out_ready : std_logic_vector(0 TO c_rx_latency);
+ signal prev_out_ready : std_logic_vector(0 to c_rx_latency);
signal out_data : std_logic_vector(c_dp_data_w - 1 downto 0);
signal out_bsn : std_logic_vector(c_dp_data_w - 1 downto 0) := (others => '0');
signal out_empty : std_logic_vector(c_dp_data_w - 1 downto 0) := (others => '0');
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd
index 38e6f61b82ca3e28499598e1907970d45b90914a..085385952f72921e15cf713ac6da839a99914ce5 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd
@@ -88,7 +88,7 @@ architecture tb of tb_dp_fifo_dc_arr is
signal cnt_en : std_logic;
signal tx_data : t_dp_data_arr(0 to c_tx_latency + c_tx_void) := (others => (others => '0'));
- signal tx_val : std_logic_vector(0 TO c_tx_latency + c_tx_void) := (others => '0');
+ signal tx_val : std_logic_vector(0 to c_tx_latency + c_tx_void) := (others => '0');
signal in_ready : std_logic;
signal in_data : std_logic_vector(c_dp_data_w - 1 downto 0) := (others => '0');
@@ -107,7 +107,7 @@ architecture tb of tb_dp_fifo_dc_arr is
signal out_sosi_arr : t_dp_sosi_arr(g_dut_nof_streams - 1 downto 0);
signal out_ready : std_logic;
- signal prev_out_ready : std_logic_vector(0 TO c_rx_latency);
+ signal prev_out_ready : std_logic_vector(0 to c_rx_latency);
signal out_data : std_logic_vector(c_dp_data_w - 1 downto 0);
signal out_bsn : std_logic_vector(c_dp_data_w - 1 downto 0) := (others => '0');
signal out_empty : std_logic_vector(c_dp_data_w - 1 downto 0) := (others => '0');
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_mixed_widths.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_mixed_widths.vhd
index b1dc3ae01b545ae5ef297eecdd419be33381a494..7769cca6d05ea07300104652cb78a12817df449a 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_mixed_widths.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_mixed_widths.vhd
@@ -90,12 +90,12 @@ architecture tb of tb_dp_fifo_dc_mixed_widths is
signal verify_out_en : std_logic := '0';
signal verify_done : std_logic;
- signal prev_wide_ready : std_logic_vector(0 TO c_rl);
+ signal prev_wide_ready : std_logic_vector(0 to c_rl);
signal wide_data : std_logic_vector(c_wide_w - 1 downto 0);
signal prev_wide_data : std_logic_vector(c_wide_w - 1 downto 0);
signal wide_gap : std_logic;
- signal prev_out_ready : std_logic_vector(0 TO c_rl);
+ signal prev_out_ready : std_logic_vector(0 to c_rl);
signal out_data : std_logic_vector(g_narrow_w - 1 downto 0);
signal prev_out_data : std_logic_vector(g_narrow_w - 1 downto 0) := to_svec(-1, g_narrow_w);
signal out_gap : std_logic;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill.vhd
index 72d204118ff37c60fced4b963fe4374b635067d1..e182d71de08b8e920f3d6bc3fd1cea163313d69b 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill.vhd
@@ -94,7 +94,7 @@ architecture tb of tb_dp_fifo_fill is
signal cnt_en : std_logic;
signal tx_data : t_dp_data_arr(0 to c_tx_latency + c_tx_void) := (others => (others => '0'));
- signal tx_val : std_logic_vector(0 TO c_tx_latency + c_tx_void) := (others => '0');
+ signal tx_val : std_logic_vector(0 to c_tx_latency + c_tx_void) := (others => '0');
signal in_ready : std_logic;
signal in_data : std_logic_vector(c_dp_data_w - 1 downto 0) := (others => '0');
@@ -113,7 +113,7 @@ architecture tb of tb_dp_fifo_fill is
signal out_sosi : t_dp_sosi;
signal out_ready : std_logic;
- signal prev_out_ready : std_logic_vector(0 TO c_rx_latency);
+ signal prev_out_ready : std_logic_vector(0 to c_rx_latency);
signal out_data : std_logic_vector(c_dp_data_w - 1 downto 0);
signal out_bsn : std_logic_vector(c_dp_data_w - 1 downto 0) := (others => '0');
signal out_empty : std_logic_vector(c_dp_data_w - 1 downto 0) := (others => '0');
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd
index 3d2a2b566d4ce967a53f53ab5c41f9e449d7c9ee..99ce07696ee1fea41a56a9a838eed78bc43b9347 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd
@@ -104,7 +104,7 @@ architecture tb of tb_dp_fifo_fill_eop is
signal cnt_en : std_logic := '1'; -- default always active input control.
signal tx_data : t_dp_data_arr(0 to c_tx_latency + c_tx_void) := (others => (others => '0'));
- signal tx_val : std_logic_vector(0 TO c_tx_latency + c_tx_void) := (others => '0');
+ signal tx_val : std_logic_vector(0 to c_tx_latency + c_tx_void) := (others => '0');
signal in_ready : std_logic;
signal in_data : std_logic_vector(c_dp_data_w - 1 downto 0) := (others => '0');
@@ -125,7 +125,7 @@ architecture tb of tb_dp_fifo_fill_eop is
signal out_sosi : t_dp_sosi;
signal out_ready : std_logic := '1'; -- default always active output flow control.
- signal prev_out_ready : std_logic_vector(0 TO c_rx_latency);
+ signal prev_out_ready : std_logic_vector(0 to c_rx_latency);
signal out_data : std_logic_vector(c_dp_data_w - 1 downto 0);
signal out_bsn : std_logic_vector(c_dp_data_w - 1 downto 0) := (others => '0');
signal out_empty : std_logic_vector(c_dp_data_w - 1 downto 0) := (others => '0');
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_sc.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_sc.vhd
index ad02de6b6f11a3b3c9952238cedc486ddd3f8d61..e781ea0ff7b5b9d715f3e25c033a8baf813ba9d6 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_sc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_sc.vhd
@@ -97,7 +97,7 @@ architecture tb of tb_dp_fifo_fill_sc is
signal cnt_en : std_logic;
signal tx_data : t_dp_data_arr(0 to c_tx_latency + c_tx_void) := (others => (others => '0'));
- signal tx_val : std_logic_vector(0 TO c_tx_latency + c_tx_void) := (others => '0');
+ signal tx_val : std_logic_vector(0 to c_tx_latency + c_tx_void) := (others => '0');
signal in_ready : std_logic;
signal in_data : std_logic_vector(c_dp_data_w - 1 downto 0) := (others => '0');
@@ -118,7 +118,7 @@ architecture tb of tb_dp_fifo_fill_sc is
signal out_sosi : t_dp_sosi;
signal out_ready : std_logic;
- signal prev_out_ready : std_logic_vector(0 TO c_rx_latency);
+ signal prev_out_ready : std_logic_vector(0 to c_rx_latency);
signal out_data : std_logic_vector(c_dp_data_w - 1 downto 0);
signal out_bsn : std_logic_vector(c_dp_data_w - 1 downto 0) := (others => '0');
signal out_empty : std_logic_vector(c_dp_data_w - 1 downto 0) := (others => '0');
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_info.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_info.vhd
index 49eb627fa83233cb1f704a15ccebd0beb49ef7c3..ba8cb07ef97af7a1aaf6b28cbe04d786706a7c4f 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_info.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_info.vhd
@@ -97,7 +97,7 @@ architecture tb of tb_dp_fifo_info is
signal fifo_usedw : std_logic_vector(ceil_log2(g_info_fifo_size) - 1 downto 0);
signal fifo_rd_emp : std_logic;
- signal prev_verify_snk_out_ready : std_logic_vector(0 TO c_rl);
+ signal prev_verify_snk_out_ready : std_logic_vector(0 to c_rl);
signal verify_snk_out : t_dp_siso := c_dp_siso_rdy;
signal verify_snk_in : t_dp_sosi;
signal prev_verify_snk_in : t_dp_sosi;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_sc.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_sc.vhd
index f0c3da6869fd1f6d287ee76b415df3ddf6a9f057..8c0da8f37e85340236be2c1f81d3297fe3870f88 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_sc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_sc.vhd
@@ -80,7 +80,7 @@ architecture tb of tb_dp_fifo_sc is
signal cnt_en : std_logic;
signal tx_data : t_dp_data_arr(0 to c_tx_latency + c_tx_void) := (others => (others => '0'));
- signal tx_val : std_logic_vector(0 TO c_tx_latency + c_tx_void) := (others => '0');
+ signal tx_val : std_logic_vector(0 to c_tx_latency + c_tx_void) := (others => '0');
signal in_ready : std_logic;
signal in_data : std_logic_vector(c_dp_data_w - 1 downto 0) := (others => '0');
@@ -98,7 +98,7 @@ architecture tb of tb_dp_fifo_sc is
signal out_sosi : t_dp_sosi;
signal out_ready : std_logic;
- signal prev_out_ready : std_logic_vector(0 TO c_rx_latency);
+ signal prev_out_ready : std_logic_vector(0 to c_rx_latency);
signal out_data : std_logic_vector(c_dp_data_w - 1 downto 0);
signal out_bsn : std_logic_vector(c_dp_data_w - 1 downto 0) := (others => '0');
signal out_empty : std_logic_vector(c_dp_data_w - 1 downto 0) := (others => '0');
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_flush.vhd b/libraries/base/dp/tb/vhdl/tb_dp_flush.vhd
index 96927bcde932b8a51e18689068dd07f7de3855e3..91f7d7ed02934a3359cfebee4d6607a852e626b6 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_flush.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_flush.vhd
@@ -100,7 +100,7 @@ architecture tb of tb_dp_flush is
signal reg_m : t_mon := ('x', 'x', 'x', 'x', 'x', 'x', '0', 'x', 'x', 'x', 'x', 'x', 'x', '1');
signal flush_en : std_logic := '0';
- signal flush_en_dly : std_logic_vector(0 TO g_rl);
+ signal flush_en_dly : std_logic_vector(0 to g_rl);
signal reg_mode_flush_en_streaming : std_logic;
signal reg_mode_flush_en_framed : std_logic := '0';
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_folder.vhd b/libraries/base/dp/tb/vhdl/tb_dp_folder.vhd
index 659c28decedc8610a70812aa65ebba75d0e30101..386cc0f99be658a27dbdbc9b663693fe86d0d323 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_folder.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_folder.vhd
@@ -125,4 +125,4 @@ begin
src_out_arr => dp_folder_src_out_arr
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_frame_rd.vhd b/libraries/base/dp/tb/vhdl/tb_dp_frame_rd.vhd
index a9db573e7f94a9bbb1bce443f0c4f0e1f9ccfc78..414e0ed1fb51d67fbc19b9c065f404ca9b5c3751 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_frame_rd.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_frame_rd.vhd
@@ -48,7 +48,7 @@ architecture tb of tb_dp_frame_rd is
constant c_data_w : natural := 16;
constant c_fifo_nof_words : natural := 1024;
- constant c_fifo_dat_w : natural := 1 +1 + c_data_w; -- = 1+1+32=34
+ constant c_fifo_dat_w : natural := 1 + 1 + c_data_w; -- = 1+1+32=34
constant c_throttle_num : natural := 1; -- numerator <= g_throttle_den
constant c_throttle_den : natural := 4; -- denominator (use 1 for full speed, i.e no output throttling)
--CONSTANT c_throttle_sof : BOOLEAN := TRUE; -- when false immediately do request next data after sof
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_frame_scheduler.vhd b/libraries/base/dp/tb/vhdl/tb_dp_frame_scheduler.vhd
index e689c9267da620823d5ba055c5fb8a0b6308e1be..0287123494822716350e0f0c3d877b3de81cddab 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_frame_scheduler.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_frame_scheduler.vhd
@@ -396,8 +396,8 @@ begin
mark_out_data_x_0 <= mark_out_fsn_x_hld_d and lane_tx_val;
mark_out_data_b_0 <= mark_out_fsn_b_hld_d and lane_tx_val;
- mark_out_eof_x <= '1' when unsigned(lane_tx_dat) = c_packet_size_x - 1 -3 and mark_out_data_x='1' and lane_tx_val='1' else '0'; -- data 0..n-1 -3 to account for: idle, sfd, fsn
- mark_out_eof_b <= '1' when unsigned(lane_tx_dat) = c_packet_size_b - 1 -3 and mark_out_data_b='1' and lane_tx_val='1' else '0'; -- data 0..n-1 -3 to account for: idle, sfd, fsn
+ mark_out_eof_x <= '1' when unsigned(lane_tx_dat) = c_packet_size_x - 1 - 3 and mark_out_data_x = '1' and lane_tx_val = '1' else '0'; -- data 0..n-1 -3 to account for: idle, sfd, fsn
+ mark_out_eof_b <= '1' when unsigned(lane_tx_dat) = c_packet_size_b - 1 - 3 and mark_out_data_b = '1' and lane_tx_val = '1' else '0'; -- data 0..n-1 -3 to account for: idle, sfd, fsn
mark_out_eof <= mark_out_eof_x or mark_out_eof_b;
mark_out_eof_x_d <= mark_out_eof_x when rising_edge(clk);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_hdr_insert_remove.vhd b/libraries/base/dp/tb/vhdl/tb_dp_hdr_insert_remove.vhd
index 713d0418cced3797363f7fb0f3ca3d02b41c0eb4..1de95e7d8b8fa46e9d9f7ac3b1b0de1f76a2fc35 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_hdr_insert_remove.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_hdr_insert_remove.vhd
@@ -82,7 +82,7 @@ architecture tb of tb_dp_hdr_insert_remove is
signal verify_en : std_logic := '0';
signal verify_done : std_logic := '0';
- signal prev_out_ready : std_logic_vector(0 TO c_rl);
+ signal prev_out_ready : std_logic_vector(0 to c_rl);
signal prev_out_data : std_logic_vector(g_data_w - 1 downto 0);
signal prev_out_bsn : std_logic_vector(c_bsn_w - 1 downto 0) := (others => '1'); -- = -1
signal prev_out_channel : std_logic_vector(c_dp_stream_channel_w - 1 downto 0) := to_svec(c_channel_init -1, c_dp_stream_channel_w);
@@ -189,7 +189,7 @@ begin
proc_common_wait_some_cycles(mm_clk, 5);
proc_mem_mm_bus_wr(0, c_ram_header_start, mm_clk, ram_hdr_mosi);
- for i in 0 to c_hdr_nof_mm_words - 2 -1 loop
+ for i in 0 to c_hdr_nof_mm_words - 2 - 1 loop
proc_mem_mm_bus_wr(1 + i, i, mm_clk, ram_hdr_mosi);
end loop;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_latency_adapter.vhd b/libraries/base/dp/tb/vhdl/tb_dp_latency_adapter.vhd
index 8189445a42d6233d2e54c26b8cbc67096877f300..ff69a2562437facbb723534076bb6e406f7427c8 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_latency_adapter.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_latency_adapter.vhd
@@ -87,7 +87,7 @@ architecture tb of tb_dp_latency_adapter is
signal cnt_en : std_logic;
signal tx_data : t_dp_data_arr(0 to c_tx_latency + c_tx_void);
- signal tx_val : std_logic_vector(0 TO c_tx_latency + c_tx_void);
+ signal tx_val : std_logic_vector(0 to c_tx_latency + c_tx_void);
signal in_ready : std_logic;
signal in_data : std_logic_vector(c_dp_data_w - 1 downto 0);
@@ -110,7 +110,7 @@ architecture tb of tb_dp_latency_adapter is
signal dut_sosi : t_dp_sosi_arr(-1 to c_nof_dut - 1) := (others => c_dp_sosi_rst);
signal out_ready : std_logic;
- signal prev_out_ready : std_logic_vector(0 TO c_rx_latency);
+ signal prev_out_ready : std_logic_vector(0 to c_rx_latency);
signal out_data : std_logic_vector(c_dp_data_w - 1 downto 0);
signal out_empty : std_logic_vector(c_dp_data_w - 1 downto 0);
signal out_channel : std_logic_vector(c_dp_data_w - 1 downto 0);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_latency_fifo.vhd b/libraries/base/dp/tb/vhdl/tb_dp_latency_fifo.vhd
index cae5c3e805965ad026a49244d9f0e03e1a2ec8a7..875a08ce2f136519933bbb6df81ce0c7addfc448 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_latency_fifo.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_latency_fifo.vhd
@@ -86,7 +86,7 @@ architecture tb of tb_dp_latency_fifo is
signal verify_en : std_logic := '0';
signal verify_done : std_logic := '0';
- signal prev_out_ready : std_logic_vector(0 TO g_output_rl);
+ signal prev_out_ready : std_logic_vector(0 to g_output_rl);
signal prev_out_data : std_logic_vector(c_data_w - 1 downto 0);
signal expected_out_data : std_logic_vector(c_data_w - 1 downto 0);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_mux.vhd b/libraries/base/dp/tb/vhdl/tb_dp_mux.vhd
index 47f136033b1deb7a883fe0ddb466c02a4446cb04..9db77e91c4de77fd71e09bda2f4ebd05327f2529 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_mux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_mux.vhd
@@ -76,39 +76,39 @@ architecture tb of tb_dp_mux is
constant c_random_w : natural := 19;
- signal tb_end_vec : std_logic_vector(0 TO g_dut_nof_input - 1) := (others => '0');
+ signal tb_end_vec : std_logic_vector(0 to g_dut_nof_input - 1) := (others => '0');
signal tb_end : std_logic := '0';
signal clk : std_logic := '0';
signal rst : std_logic;
signal sync : std_logic;
- signal sync_dly : std_logic_vector(0 TO g_dut_nof_input - 1);
+ signal sync_dly : std_logic_vector(0 to g_dut_nof_input - 1);
signal lfsr1 : std_logic_vector(c_random_w - 1 downto 0) := (others => '0');
signal lfsr2 : std_logic_vector(c_random_w downto 0) := (others => '0');
signal cnt_dat : t_dp_data_arr(0 to g_dut_nof_input - 1);
- signal cnt_val : std_logic_vector(0 TO g_dut_nof_input - 1);
- signal cnt_en : std_logic_vector(0 TO g_dut_nof_input - 1);
+ signal cnt_val : std_logic_vector(0 to g_dut_nof_input - 1);
+ signal cnt_en : std_logic_vector(0 to g_dut_nof_input - 1);
type t_dp_state_enum_arr is array (natural range <> ) of t_dp_state_enum;
type t_tx_data_arr_arr is array (natural range <> ) of t_dp_data_arr( 0 to c_tx_latency + c_tx_void);
- type t_tx_val_arr_arr is array (natural range <> ) of std_logic_vector(0 TO c_tx_latency + c_tx_void);
+ type t_tx_val_arr_arr is array (natural range <> ) of std_logic_vector(0 to c_tx_latency + c_tx_void);
- type t_prev_out_ready_arr_arr is array (natural range <> ) of std_logic_vector(0 TO c_rx_latency);
+ type t_prev_out_ready_arr_arr is array (natural range <> ) of std_logic_vector(0 to c_rx_latency);
signal tx_data : t_tx_data_arr_arr(0 to g_dut_nof_input - 1) := (others => (others => (others => '0')));
signal tx_val : t_tx_val_arr_arr( 0 to g_dut_nof_input - 1) := (others => (others => '0'));
signal sel_ctrl : natural range 0 to g_dut_nof_input - 1 := 0; -- used by g_mode = 2, 3
- signal in_ready : std_logic_vector(0 TO g_dut_nof_input - 1);
+ signal in_ready : std_logic_vector(0 to g_dut_nof_input - 1);
signal in_data : t_dp_data_arr(0 to g_dut_nof_input - 1) := (others => (others => '0'));
signal in_empty : t_dp_data_arr(0 to g_dut_nof_input - 1) := (others => (others => '0'));
signal in_channel : t_dp_data_arr(0 to g_dut_nof_input - 1) := (others => (others => '0'));
- signal in_sync : std_logic_vector(0 TO g_dut_nof_input - 1);
- signal in_val : std_logic_vector(0 TO g_dut_nof_input - 1);
- signal in_sop : std_logic_vector(0 TO g_dut_nof_input - 1);
- signal in_eop : std_logic_vector(0 TO g_dut_nof_input - 1);
+ signal in_sync : std_logic_vector(0 to g_dut_nof_input - 1);
+ signal in_val : std_logic_vector(0 to g_dut_nof_input - 1);
+ signal in_sop : std_logic_vector(0 to g_dut_nof_input - 1);
+ signal in_eop : std_logic_vector(0 to g_dut_nof_input - 1);
signal in_data_vec : std_logic_vector(g_dut_nof_input * c_dp_data_w - 1 downto 0) := (others => '0');
signal in_empty_vec : std_logic_vector(g_dut_nof_input * c_dp_data_w - 1 downto 0) := (others => '0');
@@ -128,23 +128,23 @@ architecture tb of tb_dp_mux is
signal mux_eop : std_logic;
signal mux_ready : std_logic;
- signal out_ready : std_logic_vector( 0 TO g_dut_nof_input - 1);
+ signal out_ready : std_logic_vector( 0 to g_dut_nof_input - 1);
signal prev_out_ready : t_prev_out_ready_arr_arr(0 to g_dut_nof_input - 1);
signal out_data : t_dp_data_arr(0 to g_dut_nof_input - 1) := (others => (others => '0'));
signal out_empty : t_dp_data_arr(0 to g_dut_nof_input - 1) := (others => (others => '0'));
signal out_channel : t_dp_data_arr(0 to g_dut_nof_input - 1) := (others => (others => '0'));
- signal out_sync : std_logic_vector(0 TO g_dut_nof_input - 1);
- signal out_val : std_logic_vector(0 TO g_dut_nof_input - 1);
- signal out_sop : std_logic_vector(0 TO g_dut_nof_input - 1);
- signal out_eop : std_logic_vector(0 TO g_dut_nof_input - 1);
- signal hold_out_sop : std_logic_vector(0 TO g_dut_nof_input - 1);
+ signal out_sync : std_logic_vector(0 to g_dut_nof_input - 1);
+ signal out_val : std_logic_vector(0 to g_dut_nof_input - 1);
+ signal out_sop : std_logic_vector(0 to g_dut_nof_input - 1);
+ signal out_eop : std_logic_vector(0 to g_dut_nof_input - 1);
+ signal hold_out_sop : std_logic_vector(0 to g_dut_nof_input - 1);
signal prev_out_data : t_dp_data_arr(0 to g_dut_nof_input - 1) := (others => (others => '0'));
signal state : t_dp_state_enum_arr(0 to g_dut_nof_input - 1);
signal verify_en : std_logic;
- signal verify_done : std_logic_vector(0 TO g_dut_nof_input - 1);
+ signal verify_done : std_logic_vector(0 to g_dut_nof_input - 1);
signal exp_data : std_logic_vector(c_dp_data_w - 1 downto 0) := to_uvec(1000, c_dp_data_w);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_offload_rx_filter.vhd b/libraries/base/dp/tb/vhdl/tb_dp_offload_rx_filter.vhd
index 92e490507003ba6a6c60fd369d85912dbc46f284..a3d95d725f45ae15de3cee9d63cc4c1bb92c3cdc 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_offload_rx_filter.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_offload_rx_filter.vhd
@@ -68,7 +68,7 @@ architecture tb of tb_dp_offload_rx_filter is
constant c_nof_packets : natural := 5;
- constant c_nof_hdr_fields : natural := 3 +12 + 4 + 9 + 1;
+ constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 9 + 1;
constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd b/libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd
index a3aaa49218584223c87a30086046ecaed4c470dd..51715745918ba823fd3f8726a6fd7bfe6367beb1 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd
@@ -129,7 +129,7 @@ architecture tb of tb_dp_offload_tx_v3 is
-- Tx offload
-----------------------------------------------------------------------------
-- From apertif_udp_offload_pkg.vhd:
- constant c_udp_offload_nof_hdr_fields : natural := 3 +12 + 4 +3; -- 22, 448b; 7 64b words
+ constant c_udp_offload_nof_hdr_fields : natural := 3 + 12 + 4 +3; -- 22, 448b; 7 64b words
constant c_udp_offload_nof_hdr_words_default : natural := 26; -- 23 single word + 3 double word = 26 32b words
constant c_udp_offload_nof_hdr_words_shortened : natural := c_udp_offload_nof_hdr_words_default - 1;
constant c_udp_offload_nof_hdr_words : natural := sel_a_b(c_use_shortened_header, c_udp_offload_nof_hdr_words_shortened, c_udp_offload_nof_hdr_words_default);
@@ -276,7 +276,7 @@ architecture tb of tb_dp_offload_tx_v3 is
-- From apertif_unb1_fn_beamformer_udp_offload.vhd: 221 111111111000 0000 000
-- Override ('1') only the Ethernet fields so we can use MM defaults there. 109 876543210987 6543 210
- constant c_hdr_field_ovr_init : std_logic_vector(c_udp_offload_nof_hdr_fields - 1 downto 0) := "101" &"111111111111 " &"1111 " &"100 ";
+ constant c_hdr_field_ovr_init : std_logic_vector(c_udp_offload_nof_hdr_fields - 1 downto 0) := "101" &"111111111111 " &"1111 " &"100 ";
constant c_NODE_ID : std_logic_vector(7 downto 0) := to_uvec(0, 8);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_packet.vhd b/libraries/base/dp/tb/vhdl/tb_dp_packet.vhd
index 066b8002a13a09345d5a49721d714725fb4554e4..71714d44a0164f8d98640c7c8a35c30428cf8476 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_packet.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_packet.vhd
@@ -96,7 +96,7 @@ architecture tb of tb_dp_packet is
signal enc_siso : t_dp_siso := c_dp_siso_rdy;
signal enc_sosi : t_dp_sosi;
- signal prev_pkt_ready : std_logic_vector(0 TO c_rl);
+ signal prev_pkt_ready : std_logic_vector(0 to c_rl);
signal pkt_siso : t_dp_siso := c_dp_siso_rdy;
signal pkt_sosi : t_dp_sosi;
signal pkt_data : std_logic_vector(g_data_w - 1 downto 0);
@@ -105,7 +105,7 @@ architecture tb of tb_dp_packet is
signal pkt_eop : std_logic;
signal pkt_sync : std_logic;
- signal prev_rx_ready : std_logic_vector(0 TO c_rl);
+ signal prev_rx_ready : std_logic_vector(0 to c_rl);
signal rx_siso : t_dp_siso := c_dp_siso_rdy;
signal rx_sosi : t_dp_sosi;
signal prev_rx_data : std_logic_vector(g_data_w - 1 downto 0) := to_svec(c_data_init -1, g_data_w);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_pad_insert_remove.vhd b/libraries/base/dp/tb/vhdl/tb_dp_pad_insert_remove.vhd
index 66bf5d86374aa8624de9b5b941b02c8a36209073..0775b5c2a1a418fb9777d19581321d9aea94706d 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_pad_insert_remove.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_pad_insert_remove.vhd
@@ -82,7 +82,7 @@ architecture tb of tb_dp_pad_insert_remove is
signal verify_en : std_logic := '0';
signal verify_done : std_logic := '0';
- signal prev_out_ready : std_logic_vector(0 TO c_rl);
+ signal prev_out_ready : std_logic_vector(0 to c_rl);
signal prev_out_data : std_logic_vector(g_data_w - 1 downto 0);
signal prev_out_bsn : std_logic_vector(c_bsn_w - 1 downto 0) := (others => '1'); -- = -1
signal prev_out_channel : std_logic_vector(c_dp_stream_channel_w - 1 downto 0) := to_svec(c_channel_init -1, c_dp_stream_channel_w);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_pipeline.vhd b/libraries/base/dp/tb/vhdl/tb_dp_pipeline.vhd
index a34859f939951b6236ef261e8ce1da5daa776e3f..d9ec0cb8c1930b395a96ad8c1564918b2889a497 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_pipeline.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_pipeline.vhd
@@ -65,7 +65,7 @@ architecture tb of tb_dp_pipeline is
signal cnt_en : std_logic;
signal tx_data : t_dp_data_arr(0 to c_tx_latency + c_tx_void) := (others => (others => '0'));
- signal tx_val : std_logic_vector(0 TO c_tx_latency + c_tx_void) := (others => '0');
+ signal tx_val : std_logic_vector(0 to c_tx_latency + c_tx_void) := (others => '0');
signal in_ready : std_logic;
signal in_data : std_logic_vector(c_dp_data_w - 1 downto 0) := (others => '0');
@@ -80,7 +80,7 @@ architecture tb of tb_dp_pipeline is
signal out_sosi : t_dp_sosi;
signal out_ready : std_logic;
- signal prev_out_ready : std_logic_vector(0 TO c_rx_latency);
+ signal prev_out_ready : std_logic_vector(0 to c_rx_latency);
signal out_data : std_logic_vector(c_dp_data_w - 1 downto 0);
signal out_sync : std_logic;
signal out_val : std_logic;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_pipeline_ready.vhd b/libraries/base/dp/tb/vhdl/tb_dp_pipeline_ready.vhd
index 76cd02df871dbd3083c2e189c5def58278cc75e1..51beb322cec04d3170b46b12b3713fa11a0dd45e 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_pipeline_ready.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_pipeline_ready.vhd
@@ -84,7 +84,7 @@ architecture tb of tb_dp_pipeline_ready is
signal verify_done : std_logic := '0';
signal count_eop : natural := 0;
- signal prev_out_ready : std_logic_vector(0 TO g_out_latency);
+ signal prev_out_ready : std_logic_vector(0 to g_out_latency);
signal prev_out_data : std_logic_vector(c_data_w - 1 downto 0) := to_svec(c_data_init -1, c_data_w);
signal out_bsn : std_logic_vector(c_data_w - 1 downto 0);
signal out_data : std_logic_vector(c_data_w - 1 downto 0);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_pkg.vhd b/libraries/base/dp/tb/vhdl/tb_dp_pkg.vhd
index 3249061ac50a3a8991dad86c47200c3f7abda2d4..ff3008fe9caf78b329323806dd9a1fa7608c3644 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_pkg.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_pkg.vhd
@@ -2165,19 +2165,19 @@ package body tb_dp_pkg is
begin
if rising_edge(clk) then
if verify_en = '1' then
- if c_str ="bsn " then
+ if c_str ="bsn " then
if unsigned(c_exp_data(c_dp_bsn_w - 1 downto 0)) /= unsigned(res_data(c_dp_bsn_w - 1 downto 0)) then
report "DP : Wrong sosi.bsn value" severity ERROR;
end if;
- elsif c_str ="empty " then
+ elsif c_str ="empty " then
if unsigned(c_exp_data(c_dp_empty_w - 1 downto 0)) /= unsigned(res_data(c_dp_empty_w - 1 downto 0)) then
report "DP : Wrong sosi.empty value" severity ERROR;
end if;
- elsif c_str ="channel " then
+ elsif c_str ="channel " then
if unsigned(c_exp_data(c_dp_channel_user_w - 1 downto 0)) /= unsigned(res_data(c_dp_channel_user_w - 1 downto 0)) then
report "DP : Wrong sosi.channel value" severity ERROR;
end if;
- elsif c_str ="error " then
+ elsif c_str ="error " then
if unsigned(c_exp_data(c_dp_error_w - 1 downto 0)) /= unsigned(res_data(c_dp_error_w - 1 downto 0)) then
report "DP : Wrong sosi.error value" severity ERROR;
end if;
@@ -2204,51 +2204,51 @@ package body tb_dp_pkg is
if rising_edge(clk) then
if verify_en = '1' then
-- sosi ctrl fields
- if c_str ="sync " then
+ if c_str ="sync " then
if dut_sosi.sync /= exp_sosi.sync then
report "DP : Wrong dut_sosi.sync (" & sl_to_str(dut_sosi.sync) & " /= " & sl_to_str(exp_sosi.sync) & ")" severity ERROR;
end if;
- elsif c_str ="sop " then
+ elsif c_str ="sop " then
if dut_sosi.sop /= exp_sosi.sop then
report "DP : Wrong dut_sosi.sop (" & sl_to_str(dut_sosi.sop) & " /= " & sl_to_str(exp_sosi.sop) & ")" severity ERROR;
end if;
- elsif c_str ="eop " then
+ elsif c_str ="eop " then
if dut_sosi.eop /= exp_sosi.eop then
report "DP : Wrong dut_sosi.eop (" & sl_to_str(dut_sosi.eop) & " /= " & sl_to_str(exp_sosi.eop) & ")" severity ERROR;
end if;
- elsif c_str ="valid " then
+ elsif c_str ="valid " then
if dut_sosi.valid /= exp_sosi.valid then
report "DP : Wrong dut_sosi.valid (" & sl_to_str(dut_sosi.valid) & " /= " & sl_to_str(exp_sosi.valid) & ")" severity ERROR;
end if;
-- sosi info fields
- elsif c_str ="bsn " then
+ elsif c_str ="bsn " then
if dut_sosi.bsn /= exp_sosi.bsn then
report "DP : Wrong dut_sosi.bsn (" & int_to_str(dut_sosi.bsn) & " /= " & int_to_str(exp_sosi.bsn) & ")" severity ERROR;
end if;
- elsif c_str ="empty " then
+ elsif c_str ="empty " then
if dut_sosi.empty /= exp_sosi.empty then
report "DP : Wrong dut_sosi.empty (" & int_to_str(dut_sosi.empty) & " /= " & int_to_str(exp_sosi.empty) & ")" severity ERROR;
end if;
- elsif c_str ="channel " then
+ elsif c_str ="channel " then
if dut_sosi.channel /= exp_sosi.channel then
report "DP : Wrong dut_sosi.channel (" & int_to_str(dut_sosi.channel) & " /= " & int_to_str(exp_sosi.channel) & ")" severity ERROR;
end if;
- elsif c_str ="err " then
+ elsif c_str ="err " then
if dut_sosi.err /= exp_sosi.err then
report "DP : Wrong dut_sosi.err (" & int_to_str(dut_sosi.err) & " /= " & int_to_str(exp_sosi.err) & ")" severity ERROR;
end if;
-- sosi data fields
- elsif c_str ="data " then
+ elsif c_str ="data " then
if dut_sosi.data /= exp_sosi.data then
report "DP : Wrong dut_sosi.data (" & int_to_str(dut_sosi.data) & " /= " & int_to_str(exp_sosi.data) & ")" severity ERROR;
end if;
- elsif c_str ="re " then
+ elsif c_str ="re " then
if dut_sosi.re /= exp_sosi.re then
report "DP : Wrong dut_sosi.re (" & int_to_str(dut_sosi.re) & " /= " & int_to_str(exp_sosi.re) & ")" severity ERROR;
end if;
- elsif c_str ="im " then
+ elsif c_str ="im " then
if dut_sosi.im /= exp_sosi.im then
report "DP : Wrong dut_sosi.im (" & int_to_str(dut_sosi.im) & " /= " & int_to_str(exp_sosi.im) & ")" & ")" severity ERROR;
end if;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_selector_arr.vhd b/libraries/base/dp/tb/vhdl/tb_dp_selector_arr.vhd
index fc898090dc7cb034615e261ef8f2d9b5ebf151b5..59b4074b4943a2d47a7a3ef3ae577a72fe869b9b 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_selector_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_selector_arr.vhd
@@ -243,4 +243,4 @@ begin
wait;
end process;
-end tb;
+end tb;
\ No newline at end of file
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_shiftram.vhd b/libraries/base/dp/tb/vhdl/tb_dp_shiftram.vhd
index 38b9a8edd0feb94769a57cc78c7f72dde70ee635..62e457094300819393cba753041941d953977e9a 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_shiftram.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_shiftram.vhd
@@ -214,4 +214,4 @@ begin
src_out_arr => out_sosi_arr
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_shiftreg.vhd b/libraries/base/dp/tb/vhdl/tb_dp_shiftreg.vhd
index 8153137ba9c6c0de3c1739d07097cc36c32a33b0..036cf398585a7da61cfaa5cf94b2cb8043085b3f 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_shiftreg.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_shiftreg.vhd
@@ -66,7 +66,7 @@ architecture tb of tb_dp_shiftreg is
signal cnt_en : std_logic;
signal tx_data : t_dp_data_arr(0 to c_tx_latency + c_tx_void) := (others => (others => '0'));
- signal tx_val : std_logic_vector(0 TO c_tx_latency + c_tx_void) := (others => '0');
+ signal tx_val : std_logic_vector(0 to c_tx_latency + c_tx_void) := (others => '0');
signal in_ready : std_logic;
signal in_data : std_logic_vector(c_dp_data_w - 1 downto 0) := (others => '0');
@@ -82,7 +82,7 @@ architecture tb of tb_dp_shiftreg is
signal out_sosi : t_dp_sosi;
signal out_ready : std_logic;
- signal prev_out_ready : std_logic_vector(0 TO c_rx_latency);
+ signal prev_out_ready : std_logic_vector(0 to c_rx_latency);
signal out_data : std_logic_vector(c_dp_data_w - 1 downto 0);
signal out_val : std_logic;
signal out_sop : std_logic;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_split.vhd b/libraries/base/dp/tb/vhdl/tb_dp_split.vhd
index c29fbf49e3c53a6cb2a4f97fdb0ceec01253fae2..be90bb7ffac266e694e27f846a0d60d440235a13 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_split.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_split.vhd
@@ -74,8 +74,8 @@ architecture tb of tb_dp_split is
signal verify_en_1 : std_logic := '0';
signal verify_done : std_logic;
- signal prev_out_ready_0 : std_logic_vector(0 TO c_rl);
- signal prev_out_ready_1 : std_logic_vector(0 TO c_rl);
+ signal prev_out_ready_0 : std_logic_vector(0 to c_rl);
+ signal prev_out_ready_1 : std_logic_vector(0 to c_rl);
signal out_data_0 : std_logic_vector(g_data_w - 1 downto 0);
signal out_data_1 : std_logic_vector(g_data_w - 1 downto 0);
signal prev_out_data_0 : std_logic_vector(g_data_w - 1 downto 0);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_switch.vhd b/libraries/base/dp/tb/vhdl/tb_dp_switch.vhd
index 3f7f472017f30e1f7520f859634b336aba46c94b..92d42c34ae074325aa573c41ae21816682ad90f8 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_switch.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_switch.vhd
@@ -186,4 +186,4 @@ begin
reg_miso => reg_dp_switch_miso
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_sync_checker.vhd b/libraries/base/dp/tb/vhdl/tb_dp_sync_checker.vhd
index 5eb5c81bae8bd90a17e20ad903bc32bd552771d3..6fda3e75a8e556ea94a61f0dcdfdd48dc02a8779 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_sync_checker.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_sync_checker.vhd
@@ -285,5 +285,4 @@ begin
verify_snk_in_data <= verify_snk_in.data when verify_snk_in.valid = '1';
-end tb;
-
+end tb;
\ No newline at end of file
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_sync_insert.vhd b/libraries/base/dp/tb/vhdl/tb_dp_sync_insert.vhd
index 314888cdfb58d87e4d6ae10173d741ed4cfc51d7..4e1e08fb70ff51362b88ca7e6334be72d9c28f73 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_sync_insert.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_sync_insert.vhd
@@ -68,7 +68,7 @@ architecture tb of tb_dp_sync_insert is
signal out_sosi : t_dp_sosi;
-- Verification
- signal dly_valid_arr : std_logic_vector(0 TO c_dut_latency) := (others => '0');
+ signal dly_valid_arr : std_logic_vector(0 to c_dut_latency) := (others => '0');
signal out_hold_sop : std_logic := '0';
signal exp_size : natural := g_nof_data_per_block;
signal cnt_size : natural;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_sync_insert_v2.vhd b/libraries/base/dp/tb/vhdl/tb_dp_sync_insert_v2.vhd
index 40d4ec52d98fee53c812a6a08a6187b0cfc0ede1..2af84a3249e8946144fb1ea4f2d32b58ede94742 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_sync_insert_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_sync_insert_v2.vhd
@@ -82,7 +82,7 @@ architecture tb of tb_dp_sync_insert_v2 is
signal reg_miso : t_mem_miso := c_mem_miso_rst;
-- Verification
- signal dly_valid_arr : std_logic_vector(0 TO c_dut_latency) := (others => '0');
+ signal dly_valid_arr : std_logic_vector(0 to c_dut_latency) := (others => '0');
signal dly_ref_sosi_arr : t_dp_sosi_arr(0 to c_dut_latency) := (others => c_dp_sosi_rst);
signal exp_sync : std_logic := '0';
signal out_hold_sop : std_logic := '0';
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd b/libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd
index c87d8ffb79000594ad80ab4a21715bbf9820623d..adee78fa46b0f56480ed23e501b687958c518a63 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd
@@ -73,7 +73,7 @@ architecture tb of tb_dp_sync_recover is
signal restart : std_logic := '0';
-- Verification
- signal dly_valid_arr : std_logic_vector(0 TO g_dut_latency) := (others => '0');
+ signal dly_valid_arr : std_logic_vector(0 to g_dut_latency) := (others => '0');
signal dly_ref_sosi_arr : t_dp_sosi_arr(0 to g_dut_latency) := (others => c_dp_sosi_rst);
signal exp_sync : std_logic := '0';
signal out_hold_sop : std_logic := '0';
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_tail_remove.vhd b/libraries/base/dp/tb/vhdl/tb_dp_tail_remove.vhd
index 878797e08f412680e0e139154f7a160a0e843600..32f0e05121d2f4569e871c9848183346e72293de 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_tail_remove.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_tail_remove.vhd
@@ -49,7 +49,7 @@ architecture tb of tb_dp_tail_remove is
signal rst : std_logic;
signal clk : std_logic := '0';
- signal in_en : std_logic_vector(0 TO 1) := (others => '1');
+ signal in_en : std_logic_vector(0 to 1) := (others => '1');
signal in_siso_arr : t_dp_siso_arr(0 to 1) := (others => c_dp_siso_rdy);
signal in_sosi_arr : t_dp_sosi_arr(0 to 1) := (others => c_dp_sosi_rst);
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_align.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_align.vhd
index b9047aab44c7541c1584460847251877e4be4570..1c5db527f910b42b20d10630a4abe66eabb58122 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_align.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_align.vhd
@@ -86,7 +86,7 @@ architecture tb of tb_mms_dp_bsn_align is
type t_bsn_arr is array (g_nof_input - 1 downto 0) of std_logic_vector(c_bsn_w - 1 downto 0);
type t_err_arr is array (g_nof_input - 1 downto 0) of std_logic_vector(c_dp_stream_error_w - 1 downto 0);
type t_channel_arr is array (g_nof_input - 1 downto 0) of std_logic_vector(c_dp_stream_channel_w - 1 downto 0);
- type t_rl_vec_arr is array (g_nof_input - 1 downto 0) of std_logic_vector(0 TO c_rl);
+ type t_rl_vec_arr is array (g_nof_input - 1 downto 0) of std_logic_vector(0 to c_rl);
type t_tb_state is (s_idle, s_bsn_mis_aligned, s_bsn_aligned, s_small_bsn_diff, s_large_bsn_diff, s_restore_bsn, s_disable_one_input, s_enable_inputs);
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source.vhd
index 62ca04106ec8e70506415f064a52af17c9e7eb57..202297eeb03bd2c10144248443f23c93a5590e44 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source.vhd
@@ -180,4 +180,4 @@ begin
bs_sosi => bs_sosi
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source_v2.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source_v2.vhd
index 988ddf8a10cd7d28a512864204868a25307b3d50..c5106f6ec89035a5881f30828981e931cc416996 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source_v2.vhd
@@ -205,4 +205,4 @@ begin
bs_sosi => bs_sosi
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_arr.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_arr.vhd
index 253158a4424ade19bf69c32e6339cedc63f062ed..598a8cf54804a724f4e27e4cd3ce3971cc99d8e3 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_arr.vhd
@@ -152,7 +152,7 @@ begin
gain_re_arr(I) <= v_gain_re;
proc_mem_mm_bus_wr(I, v_gain_re, mm_clk, reg_gain_re_miso, reg_gain_re_mosi);
if g_complex_gain = TRUE then
- v_gain_im := 2 ** (g_nof_streams - 1 -I);
+ v_gain_im := 2 ** (g_nof_streams - 1 - I);
gain_im_arr(I) <= v_gain_im;
proc_mem_mm_bus_wr(I, v_gain_im, mm_clk, reg_gain_im_miso, reg_gain_im_mosi);
end if;
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_sync_checker.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_sync_checker.vhd
index e25b3eea37233cff49e85e76f25fd9978fdcb806..24f62772c1802f23bacb1503d6ba45a608855bba 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_sync_checker.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_sync_checker.vhd
@@ -306,5 +306,4 @@ begin
verify_snk_in_data <= verify_snk_in.data when verify_snk_in.valid = '1';
-end tb;
-
+end tb;
\ No newline at end of file
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_xonoff.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_xonoff.vhd
index 807f0484b2cfef7845338b6c879375968ccfb115..637690282f5689b9b7d6ebd5081428a5c62d8498 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_xonoff.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_xonoff.vhd
@@ -221,4 +221,4 @@ begin
wait;
end process;
-end tb;
+end tb;
\ No newline at end of file
diff --git a/libraries/base/dp/tb/vhdl/tb_tb2_dp_demux.vhd b/libraries/base/dp/tb/vhdl/tb_tb2_dp_demux.vhd
index 91ad92e1b1195832bf550b2533e4efada015cc28..b1b5cdb4d671d7de895ea7fbabd24c757039d938 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb2_dp_demux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb2_dp_demux.vhd
@@ -50,4 +50,4 @@ begin
u2_rnd_rnd_comb : entity work.tb2_dp_demux generic map (e_random, e_random, 1, 30, 3, 2, 2, FALSE, TRUE);
u2_rnd_pls : entity work.tb2_dp_demux generic map (e_random, e_pulse, 1, 30, 3, 2, 2, FALSE, FALSE);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_from_mm.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_from_mm.vhd
index 5e72c18e4d2b0730aa70de2e396bf1bb727f472d..a26f25c3552781af330a4b77e87ebf612c2b659a 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_from_mm.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_from_mm.vhd
@@ -50,4 +50,4 @@ begin
u5_tst_2_8_256 : entity work.tb_dp_block_from_mm generic map (2, 8, 256);
u6_tst_3_6_17 : entity work.tb_dp_block_from_mm generic map (3, 6, 17);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_source_v2.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_source_v2.vhd
index bbe0b1169358d5484d3144a22995314b73f43173..a50252a12c2d19b3f41ffb4f878781c838a8513c 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_source_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_source_v2.vhd
@@ -72,4 +72,4 @@ begin
u_17_3 : entity work.tb_dp_bsn_source_v2 generic map (17, 3); -- 17 // 3 = 5, 17 MOD 3 = 2, 17/3 = 5.66 block/sync
u_101_17 : entity work.tb_dp_bsn_source_v2 generic map (101, 17); -- 101 // 17 = 5, 101 MOD 17 = 16, 101/17 = 5.9411 block/sync
-end tb;
+end tb;
\ No newline at end of file
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_sync_scheduler.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_sync_scheduler.vhd
index 72e29a0a80cbbe0c02131b52a912b766fbe517b5..bcdb819699e308005ac2024aa3d421fae6fb5e7a 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_sync_scheduler.vhd
@@ -80,4 +80,4 @@ begin
u_fraction_0 : entity work.tb_dp_bsn_sync_scheduler generic map (c_nof_input_sync, 17, 10, 3, 50, P); -- 50/10 = 5 block/out_sync
end generate;
-end tb;
+end tb;
\ No newline at end of file
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_flush.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_flush.vhd
index edc1f56c9407e32092126f5e6d223b8e9ae26f5c..77a553624d10915b6518234006153613c49d06d8 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_flush.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_flush.vhd
@@ -61,4 +61,4 @@ begin
u_1_str_frm_act_act : entity work.tb_dp_flush generic map (1, FALSE, TRUE, e_active, e_active, c_nof_repeat);
u_1_str_frm_rnd_rnd : entity work.tb_dp_flush generic map (1, FALSE, TRUE, e_random, e_random, c_nof_repeat);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_rsn_source.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_rsn_source.vhd
index a35cf1c71f6dfd5ad209ee0fd9f7735918f51d35..1f52e0798558e310369c2da466107e4508bb5a6a 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_rsn_source.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_rsn_source.vhd
@@ -93,4 +93,4 @@ begin
u_17_3 : entity work.tb_dp_rsn_source generic map (17, 3, 3); -- 17 // 3 = 5, 17 MOD 3 = 2, 17/3 = 5.66 block/sync
u_101_17 : entity work.tb_dp_rsn_source generic map (101, 17, 17); -- 101 // 17 = 5, 101 MOD 17 = 16, 101/17 = 5.9411 block/sync
-end tb;
+end tb;
\ No newline at end of file
diff --git a/libraries/base/mm/tb/vhdl/mm_file.vhd b/libraries/base/mm/tb/vhdl/mm_file.vhd
index 10fae91a32adbd9c4865780464f9bc4f964324c8..8cf857f5bd42190ea7449fa334ba87f73432a080 100644
--- a/libraries/base/mm/tb/vhdl/mm_file.vhd
+++ b/libraries/base/mm/tb/vhdl/mm_file.vhd
@@ -179,4 +179,4 @@ begin
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/mm/tb/vhdl/mm_file_pkg.vhd b/libraries/base/mm/tb/vhdl/mm_file_pkg.vhd
index f2c34cd02c087d8dd3956a72928b9f09d3aefd30..e21882e1df2a7ce025f13ce75b80c913c7cc335f 100644
--- a/libraries/base/mm/tb/vhdl/mm_file_pkg.vhd
+++ b/libraries/base/mm/tb/vhdl/mm_file_pkg.vhd
@@ -307,7 +307,7 @@ package body mm_file_pkg is
hread(rd_line, v_addr_slv); -- read the string as HEX and assign to SLV.
-- Write only: The third line contains the data to write:
- if v_rd_wr_str ="WR " then
+ if v_rd_wr_str ="WR " then
readline(rd_file, rd_line);
hread(rd_line, v_data_slv); -- read the string as HEX and assign to SLV.
end if;
@@ -319,13 +319,13 @@ package body mm_file_pkg is
mmf_file_create(rd_filename);
-- Execute the MM request to the MM slave
- if v_rd_wr_str ="WR " then
+ if v_rd_wr_str ="WR " then
print_str("[" & time_to_str(now) & "] " & rd_filename & ": Writing 0x" & slv_to_hex(v_data_slv) & " to address 0x" & slv_to_hex(v_addr_slv));
-- Treat 32 bit hex data from file as 32 bit VHDL INTEGER, so need to use signed TO_SINT() to avoid out of NATURAL range
-- warning in simulation due to '1' sign bit, because unsigned VHDL NATURAL only fits 31 bits
proc_mem_mm_bus_wr(to_uint(v_addr_slv), to_sint(v_data_slv), mm_clk, mm_miso, mm_mosi);
- elsif v_rd_wr_str ="RD " then
+ elsif v_rd_wr_str ="RD " then
proc_mem_mm_bus_rd(to_uint(v_addr_slv), mm_clk, mm_miso, mm_mosi);
if rd_latency > 0 then
proc_mem_mm_bus_rd_latency(rd_latency, mm_clk);
@@ -389,7 +389,7 @@ package body mm_file_pkg is
mmf_file_create(rd_filename);
-- Execute the simulation request
- if v_rd_wr_str ="GET_SIM_TIME " then
+ if v_rd_wr_str ="GET_SIM_TIME " then
-- Write the GET_SIM_TIME response time NOW to the .stat file
file_open(open_status_wr, wr_file, wr_filename, write_mode);
write(wr_line, time_to_str(now));
@@ -411,7 +411,7 @@ package body mm_file_pkg is
end;
- procedure mmf_poll_sim_ctrl_file(rd_file_name : in string; wr_file_name : IN string) is
+ procedure mmf_poll_sim_ctrl_file(rd_file_name : in string; wr_file_name : in string) is
begin
-- Create the ctrl file that we're going to read from
print_str("[" & time_to_str(now) & "] " & rd_file_name & ": Created" );
@@ -426,7 +426,7 @@ package body mm_file_pkg is
procedure mmf_poll_sim_ctrl_file(signal mm_clk : in std_logic;
- rd_file_name : in string; wr_file_name : IN string) is
+ rd_file_name : in string; wr_file_name : in string) is
begin
-- Create the ctrl file that we're going to read from
print_str("[" & time_to_str(now) & "] " & rd_file_name & ": Created" );
@@ -611,20 +611,20 @@ package body mm_file_pkg is
while TRUE loop
-- Read current
mmf_mm_bus_rd(filename, rd_addr, rd_data, mm_clk); -- only read low part
- if c_representation ="signed " then
- if c_condition ="> " then if to_sint(rd_data) > c_rd_value then exit; else wait for c_rd_interval; end if;
- elsif c_condition =">= " then if to_sint(rd_data) >= c_rd_value then exit; else wait for c_rd_interval; end if;
- elsif c_condition ="/= " then if to_sint(rd_data) /= c_rd_value then exit; else wait for c_rd_interval; end if;
- elsif c_condition ="<= " then if to_sint(rd_data) <= c_rd_value then exit; else wait for c_rd_interval; end if;
- elsif c_condition ="< " then if to_sint(rd_data) < c_rd_value then exit; else wait for c_rd_interval; end if;
+ if c_representation ="signed " then
+ if c_condition ="> " then if to_sint(rd_data) > c_rd_value then exit; else wait for c_rd_interval; end if;
+ elsif c_condition =">= " then if to_sint(rd_data) >= c_rd_value then exit; else wait for c_rd_interval; end if;
+ elsif c_condition ="/= " then if to_sint(rd_data) /= c_rd_value then exit; else wait for c_rd_interval; end if;
+ elsif c_condition ="<= " then if to_sint(rd_data) <= c_rd_value then exit; else wait for c_rd_interval; end if;
+ elsif c_condition ="< " then if to_sint(rd_data) < c_rd_value then exit; else wait for c_rd_interval; end if;
else if to_sint(rd_data) = c_rd_value then exit; else wait for c_rd_interval; end if; -- default: "="
end if;
else -- default: UNSIGED
- if c_condition ="> " then if to_uint(rd_data) > c_rd_value then exit; else wait for c_rd_interval; end if;
- elsif c_condition =">= " then if to_uint(rd_data) >= c_rd_value then exit; else wait for c_rd_interval; end if;
- elsif c_condition ="/= " then if to_uint(rd_data) /= c_rd_value then exit; else wait for c_rd_interval; end if;
- elsif c_condition ="<= " then if to_uint(rd_data) <= c_rd_value then exit; else wait for c_rd_interval; end if;
- elsif c_condition ="< " then if to_uint(rd_data) < c_rd_value then exit; else wait for c_rd_interval; end if;
+ if c_condition ="> " then if to_uint(rd_data) > c_rd_value then exit; else wait for c_rd_interval; end if;
+ elsif c_condition =">= " then if to_uint(rd_data) >= c_rd_value then exit; else wait for c_rd_interval; end if;
+ elsif c_condition ="/= " then if to_uint(rd_data) /= c_rd_value then exit; else wait for c_rd_interval; end if;
+ elsif c_condition ="<= " then if to_uint(rd_data) <= c_rd_value then exit; else wait for c_rd_interval; end if;
+ elsif c_condition ="< " then if to_uint(rd_data) < c_rd_value then exit; else wait for c_rd_interval; end if;
else if to_uint(rd_data) = c_rd_value then exit; else wait for c_rd_interval; end if; -- default: "="
end if;
end if;
@@ -753,4 +753,4 @@ package body mm_file_pkg is
return c_mmf_local_dir_path & mmf_prefix(s0, i0) & mmf_prefix(s1, i1) & mmf_prefix(s2, i2) & mmf_prefix(s3, i3) & mmf_prefix(s4, i4);
end;
-end mm_file_pkg;
+end mm_file_pkg;
\ No newline at end of file
diff --git a/libraries/base/mm/tb/vhdl/mm_file_unb_pkg.vhd b/libraries/base/mm/tb/vhdl/mm_file_unb_pkg.vhd
index 9f9551d9607582a84444b960903d4db2861d42be..911da84c737a37f053f6cf4d5d416e807e3360f5 100644
--- a/libraries/base/mm/tb/vhdl/mm_file_unb_pkg.vhd
+++ b/libraries/base/mm/tb/vhdl/mm_file_unb_pkg.vhd
@@ -94,4 +94,4 @@ package body mm_file_unb_pkg is
return mmf_slave_prefix(c_mmf_unb_file_path, "TB", tb, "SUBRACK", subrack, "UNB", unb, c_node_type, c_node_nr);
end;
-end mm_file_unb_pkg;
+end mm_file_unb_pkg;
\ No newline at end of file
diff --git a/libraries/base/mm/tb/vhdl/tb_mm_file.vhd b/libraries/base/mm/tb/vhdl/tb_mm_file.vhd
index c5102b53c68df89fc13b9ee907578ea9373462e6..ec2630b4cfc8b6da6b933977871f7f188e89140e 100644
--- a/libraries/base/mm/tb/vhdl/tb_mm_file.vhd
+++ b/libraries/base/mm/tb/vhdl/tb_mm_file.vhd
@@ -74,7 +74,7 @@ architecture tb of tb_mm_file is
constant c_unb_nr : natural := 3; --unb
constant c_pn_nr : natural := 1; --gn = 0:7
constant c_node_type : string(1 to 2) := sel_a_b(c_pn_nr <4, "FN", "BN");
- constant c_node_nr : natural := sel_a_b(c_node_type ="BN ", c_pn_nr -4, c_pn_nr);
+ constant c_node_nr : natural := sel_a_b(c_node_type ="BN ", c_pn_nr -4, c_pn_nr);
-- Use local mmfiles/ subdirectory in mm project build directory
constant c_sim_file_pathname : string := mmf_slave_prefix("TB", g_tb_index) & "sim";
diff --git a/libraries/base/reorder/src/vhdl/reorder_col.vhd b/libraries/base/reorder/src/vhdl/reorder_col.vhd
index 9051be473b82e851ba864f531a5fa3527cdcb96e..0befb118c5c9984d82aef9bf740de7e7fcce1d43 100644
--- a/libraries/base/reorder/src/vhdl/reorder_col.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_col.vhd
@@ -283,4 +283,4 @@ begin
output_sosi <= func_dp_stream_combine_info_and_data(info_sosi, ss_sosi);
ss_siso <= output_siso;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/reorder/src/vhdl/reorder_col_select.vhd b/libraries/base/reorder/src/vhdl/reorder_col_select.vhd
index bd75c4b921861735d59452dd71df3b5c2121f3dd..faa949dc019901d3eb56d4119a47c179b1e54d4c 100644
--- a/libraries/base/reorder/src/vhdl/reorder_col_select.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_col_select.vhd
@@ -93,8 +93,8 @@ architecture str of reorder_col_select is
signal nxt_ch_cnt : integer;
signal retrieve_sosi : t_dp_sosi;
signal retrieve_en : std_logic;
- signal retrieve_sop_dly : std_logic_vector(0 TO c_retrieve_lat);
- signal retrieve_eop_dly : std_logic_vector(0 TO c_retrieve_lat);
+ signal retrieve_sop_dly : std_logic_vector(0 to c_retrieve_lat);
+ signal retrieve_eop_dly : std_logic_vector(0 to c_retrieve_lat);
begin
@@ -224,4 +224,4 @@ begin
output_sosi <= func_dp_stream_combine_info_and_data(info_sosi, retrieve_sosi);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/reorder/src/vhdl/reorder_col_wide.vhd b/libraries/base/reorder/src/vhdl/reorder_col_wide.vhd
index 98c0d7d5f6ec3bdc3724430e0f57be7fffe956da..461b57dd391874a433df427568377ce6e08adf6f 100644
--- a/libraries/base/reorder/src/vhdl/reorder_col_wide.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_col_wide.vhd
@@ -106,7 +106,7 @@ begin
g_dsp_data_w => g_dsp_data_w,
g_nof_ch_in => c_nof_ch_in,
g_nof_ch_sel => c_nof_ch_sel,
- g_select_file_name => sel_a_b(g_select_file_prefix ="UNUSED ", "UNUSED", g_select_file_prefix & "_" & natural'image(I) & ".hex"),
+ g_select_file_name => sel_a_b(g_select_file_prefix ="UNUSED ", "UNUSED", g_select_file_prefix & "_" & natural'image(I) & ".hex"),
g_use_complex => g_use_complex
)
port map (
@@ -128,4 +128,4 @@ begin
);
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/reorder/src/vhdl/reorder_col_wide_select.vhd b/libraries/base/reorder/src/vhdl/reorder_col_wide_select.vhd
index cba2123daed87b5176421d1376dbe9fa049ff21c..433801300973d81bc81b0c2bc20a13bd2d17acf5 100644
--- a/libraries/base/reorder/src/vhdl/reorder_col_wide_select.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_col_wide_select.vhd
@@ -96,4 +96,4 @@ begin
);
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/reorder/src/vhdl/reorder_matrix.vhd b/libraries/base/reorder/src/vhdl/reorder_matrix.vhd
index 8dfa4dd73407fb31bb421806369d0065bf514577..13f761277aa664593dc358dea75babb60e6ee703 100644
--- a/libraries/base/reorder/src/vhdl/reorder_matrix.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_matrix.vhd
@@ -201,4 +201,4 @@ begin
output_sosi_arr => output_sosi_arr
);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/reorder/src/vhdl/reorder_pkg.vhd b/libraries/base/reorder/src/vhdl/reorder_pkg.vhd
index 21c57c3ebce25c0fc066e2e9106d6b4fd4aac8b6..ccc687039236468d27525a2f2369f7b526c1d451 100644
--- a/libraries/base/reorder/src/vhdl/reorder_pkg.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_pkg.vhd
@@ -80,4 +80,4 @@ end reorder_pkg;
package body reorder_pkg is
-end reorder_pkg;
+end reorder_pkg;
\ No newline at end of file
diff --git a/libraries/base/reorder/src/vhdl/reorder_retreive.vhd b/libraries/base/reorder/src/vhdl/reorder_retreive.vhd
index 28ed184c0c741fdaaf6b97b6938210e028381475..3ee2fd873b58d26fe0e89bb0adcd4a3b218dcc71 100644
--- a/libraries/base/reorder/src/vhdl/reorder_retreive.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_retreive.vhd
@@ -85,8 +85,8 @@ architecture rtl of reorder_retrieve is
signal retrieve_ready : std_logic;
signal nxt_retrieve_done : std_logic;
- signal retrieve_sop_dly : std_logic_vector(0 TO c_retrieve_lat);
- signal retrieve_eop_dly : std_logic_vector(0 TO c_retrieve_lat);
+ signal retrieve_sop_dly : std_logic_vector(0 to c_retrieve_lat);
+ signal retrieve_eop_dly : std_logic_vector(0 to c_retrieve_lat);
begin
diff --git a/libraries/base/reorder/src/vhdl/reorder_rewire_reg.vhd b/libraries/base/reorder/src/vhdl/reorder_rewire_reg.vhd
index 48c0b307fe18779292a5254e92a99dec1071d098..0946d93b5f70d3457451b264c96cf69043252288 100644
--- a/libraries/base/reorder/src/vhdl/reorder_rewire_reg.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_rewire_reg.vhd
@@ -119,4 +119,4 @@ begin
sel_reg <= sel_in_reg(g_nof_streams * g_sel_in_w - 1 downto 0);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/reorder/src/vhdl/reorder_row.vhd b/libraries/base/reorder/src/vhdl/reorder_row.vhd
index 5b1f0ae17f06608c851819de15cdb3278bd51574..9a6485307fe058eb646afd0de8538d2a7c4e76c8 100644
--- a/libraries/base/reorder/src/vhdl/reorder_row.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_row.vhd
@@ -241,4 +241,4 @@ begin
output_sosi_arr <= r.output_sosi_arr;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/reorder/src/vhdl/reorder_row_select.vhd b/libraries/base/reorder/src/vhdl/reorder_row_select.vhd
index 4952c6d88d6b401154b380915fa8b9b5404caab3..359cc555789e70d81250f48df75a11bdb79ea7a9 100644
--- a/libraries/base/reorder/src/vhdl/reorder_row_select.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_row_select.vhd
@@ -149,4 +149,4 @@ begin
output_sosi_arr <= r.output_sosi_arr;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/reorder/src/vhdl/reorder_sequencer.vhd b/libraries/base/reorder/src/vhdl/reorder_sequencer.vhd
index 9680804ad34f88a56d85c8aba0125460cc745e95..91eaef3b264e27995d7f8adfb6390016c76f62d9 100644
--- a/libraries/base/reorder/src/vhdl/reorder_sequencer.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_sequencer.vhd
@@ -324,4 +324,4 @@ begin
address <= to_uvec(r.start_addr, address'length);
burstsize <= to_uvec(r.burstsize, burstsize'length);
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/base/reorder/src/vhdl/reorder_transpose.vhd b/libraries/base/reorder/src/vhdl/reorder_transpose.vhd
index 9049a8349b10fc012f9904318e57e5e31d16eca0..4d8c7bdc7aa7c1e9550c6e1b70bb7c2c0407d8b1 100644
--- a/libraries/base/reorder/src/vhdl/reorder_transpose.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_transpose.vhd
@@ -505,5 +505,4 @@ begin
src_out_arr => i_src_out_arr
);
-end str;
-
+end str;
\ No newline at end of file
diff --git a/libraries/base/reorder/tb/vhdl/tb_mms_reorder_rewire.vhd b/libraries/base/reorder/tb/vhdl/tb_mms_reorder_rewire.vhd
index e491f6ccda15459baaf04db1ffd8b94bfb10829b..55150ffbe0ef97ca706e167f78a472db76011f2b 100644
--- a/libraries/base/reorder/tb/vhdl/tb_mms_reorder_rewire.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_mms_reorder_rewire.vhd
@@ -291,4 +291,4 @@ begin
in_sosi_arr => out_sosi_arr
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/libraries/base/reorder/tb/vhdl/tb_reorder_transpose.vhd b/libraries/base/reorder/tb/vhdl/tb_reorder_transpose.vhd
index 3255e8127788443ece1fac6a19dcf7c593a0496e..d41779043517b8ecfaadd9790c949c85e1cc7656 100644
--- a/libraries/base/reorder/tb/vhdl/tb_reorder_transpose.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_reorder_transpose.vhd
@@ -466,4 +466,4 @@ begin
in_sosi_arr => out_sosi_arr
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/libraries/base/ring/src/vhdl/ring_info.vhd b/libraries/base/ring/src/vhdl/ring_info.vhd
index 2bc20275125032ddb4e911d4323fae12ff9f095d..929d15fbd60c2a5e216e67cd1022a0a56b871f85 100644
--- a/libraries/base/ring/src/vhdl/ring_info.vhd
+++ b/libraries/base/ring/src/vhdl/ring_info.vhd
@@ -89,6 +89,3 @@ begin
end str;
-
-
-
diff --git a/libraries/base/ring/src/vhdl/ring_pkg.vhd b/libraries/base/ring/src/vhdl/ring_pkg.vhd
index 6830d0a5120a80a3e7eb8ef7b936d2d00e611ce9..bfb22c140b18fd0676c4945ea3af250fc570df72 100644
--- a/libraries/base/ring/src/vhdl/ring_pkg.vhd
+++ b/libraries/base/ring/src/vhdl/ring_pkg.vhd
@@ -81,7 +81,7 @@ package ring_pkg is
constant c_ring_eth_hdr_field_size : natural := ceil_div(field_slv_len(c_ring_eth_hdr_field_arr), c_longword_w); -- = 14/8 = 2 longwords
constant c_ring_dp_nof_hdr_fields : natural := 6;
- constant c_ring_dp_hdr_field_sel : std_logic_vector(c_ring_dp_nof_hdr_fields - 1 downto 0) := "000" &"000 ";
+ constant c_ring_dp_hdr_field_sel : std_logic_vector(c_ring_dp_nof_hdr_fields - 1 downto 0) := "000" &"000 ";
constant c_ring_dp_hdr_field_arr : t_common_field_arr(c_ring_dp_nof_hdr_fields - 1 downto 0) := (
( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(c_ring_eth_dst_mac) ),
( field_name_pad("eth_src_mac" ), "RW", 48, field_default(c_ring_eth_src_mac) ),
@@ -127,4 +127,4 @@ package body ring_pkg is
return to_uvec(func_ring_nof_hops_to_source_rn(to_uint(hops), to_uint(this_rn), to_uint(N_rn), lane_dir),hops'length);
end;
-end ring_pkg;
+end ring_pkg;
\ No newline at end of file
diff --git a/libraries/base/sens/tb/vhdl/tb_sens.vhd b/libraries/base/sens/tb/vhdl/tb_sens.vhd
index b23d43025b7092e453ed1b8568606fe2fa921582..56cd3f0f47fb77b2b9067a6af46aa5186c25c580 100644
--- a/libraries/base/sens/tb/vhdl/tb_sens.vhd
+++ b/libraries/base/sens/tb/vhdl/tb_sens.vhd
@@ -81,7 +81,7 @@ begin
p_debug : process (sens_data)
begin
for i in 0 to c_sens_temp_volt_sz - 1 loop
- sens_data_bytes(c_sens_temp_volt_sz - 1 -i) <= sens_data((i+1)*c_bus_dat_w-1 downto i*c_bus_dat_w);
+ sens_data_bytes(c_sens_temp_volt_sz - 1 - i) <= sens_data((i + 1) * c_bus_dat_w - 1 downto i * c_bus_dat_w);
end loop;
end process;
@@ -194,4 +194,4 @@ begin
temp => c_temp_pcb
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/libraries/base/ss/src/vhdl/ss.vhd b/libraries/base/ss/src/vhdl/ss.vhd
index b8669f9949dd2d5907f9226d9317a2d938f9a7e9..f572da47242f3c905f5f27aaeb4b57ea7dd22015 100644
--- a/libraries/base/ss/src/vhdl/ss.vhd
+++ b/libraries/base/ss/src/vhdl/ss.vhd
@@ -283,4 +283,4 @@ begin
output_sosi <= func_dp_stream_combine_info_and_data(info_sosi, ss_sosi);
ss_siso <= output_siso;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/ss/src/vhdl/ss_parallel.vhd b/libraries/base/ss/src/vhdl/ss_parallel.vhd
index a1a166ce82a24af161d07fb6ce3ae969c9c53546..bc03fe5c64b151c0bbb36a5f34aeb507d8a85779 100644
--- a/libraries/base/ss/src/vhdl/ss_parallel.vhd
+++ b/libraries/base/ss/src/vhdl/ss_parallel.vhd
@@ -201,4 +201,4 @@ begin
output_sosi_arr => output_sosi_arr
);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/ss/src/vhdl/ss_reorder.vhd b/libraries/base/ss/src/vhdl/ss_reorder.vhd
index b564e6d04e57df32bc4c87187665a7bb90610566..646c7b09aed3deef017c96c7ac40e49e1e0e98f8 100644
--- a/libraries/base/ss/src/vhdl/ss_reorder.vhd
+++ b/libraries/base/ss/src/vhdl/ss_reorder.vhd
@@ -231,4 +231,4 @@ begin
output_sosi_arr <= r.output_sosi_arr;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/ss/src/vhdl/ss_retrieve.vhd b/libraries/base/ss/src/vhdl/ss_retrieve.vhd
index 58533be3fe79619b4928422571110422ef795a03..06d0184c5ff30ec0ad9811497c57518cb2d0cc83 100644
--- a/libraries/base/ss/src/vhdl/ss_retrieve.vhd
+++ b/libraries/base/ss/src/vhdl/ss_retrieve.vhd
@@ -85,8 +85,8 @@ architecture rtl of ss_retrieve is
signal retrieve_ready : std_logic;
signal nxt_retrieve_done : std_logic;
- signal retrieve_sop_dly : std_logic_vector(0 TO c_retrieve_lat);
- signal retrieve_eop_dly : std_logic_vector(0 TO c_retrieve_lat);
+ signal retrieve_sop_dly : std_logic_vector(0 to c_retrieve_lat);
+ signal retrieve_eop_dly : std_logic_vector(0 to c_retrieve_lat);
begin
diff --git a/libraries/base/ss/src/vhdl/ss_wide.vhd b/libraries/base/ss/src/vhdl/ss_wide.vhd
index 39b2c78bd26d7eb372da739f85686b23bb05055a..11b2a1f05586a3bed76ff1bcf6e5e934c7e1472e 100644
--- a/libraries/base/ss/src/vhdl/ss_wide.vhd
+++ b/libraries/base/ss/src/vhdl/ss_wide.vhd
@@ -106,7 +106,7 @@ begin
g_dsp_data_w => g_dsp_data_w,
g_nof_ch_in => c_nof_ch_in,
g_nof_ch_sel => c_nof_ch_sel,
- g_select_file_name => sel_a_b(g_select_file_prefix ="UNUSED ", "UNUSED", g_select_file_prefix & "_" & natural'image(I) & ".hex"),
+ g_select_file_name => sel_a_b(g_select_file_prefix ="UNUSED ", "UNUSED", g_select_file_prefix & "_" & natural'image(I) & ".hex"),
g_use_complex => g_use_complex
)
port map (
@@ -128,4 +128,4 @@ begin
);
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/base/uth/src/vhdl/uth_pkg.vhd b/libraries/base/uth/src/vhdl/uth_pkg.vhd
index f4c8ea3bb67db49f23169c60f11168dc1a1ea7a2..fa27a5ee8c2910b11d6af7c2fac5812e7eda8974 100644
--- a/libraries/base/uth/src/vhdl/uth_pkg.vhd
+++ b/libraries/base/uth/src/vhdl/uth_pkg.vhd
@@ -116,4 +116,4 @@ package body uth_pkg is
return nxt_crc;
end func_uth_next_crc;
-end uth_pkg;
+end uth_pkg;
\ No newline at end of file
diff --git a/libraries/base/uth/src/vhdl/uth_rx.vhd b/libraries/base/uth/src/vhdl/uth_rx.vhd
index 94bf92d967c8ad2eb3a08ab600725df366f49f3c..a49f7642ba46f125dfb1505e4bb91422e9053434 100644
--- a/libraries/base/uth/src/vhdl/uth_rx.vhd
+++ b/libraries/base/uth/src/vhdl/uth_rx.vhd
@@ -787,4 +787,4 @@ begin
nxt_state <= v_nxt_state;
end process;
-end rtl_hold;
+end rtl_hold;
\ No newline at end of file
diff --git a/libraries/base/uth/tb/vhdl/tb_uth.vhd b/libraries/base/uth/tb/vhdl/tb_uth.vhd
index a0aeef7c54f0ccaedef508e88d10a5d359330c69..cbc0e8de0b14a9f88f1f43c88841a3bd9b264b8a 100644
--- a/libraries/base/uth/tb/vhdl/tb_uth.vhd
+++ b/libraries/base/uth/tb/vhdl/tb_uth.vhd
@@ -100,7 +100,7 @@ architecture tb of tb_uth is
signal phy_link_sosi : t_dp_sosi;
signal phy_link_err : std_logic;
- signal prev_uth_rx_ready : std_logic_vector(0 TO c_rl);
+ signal prev_uth_rx_ready : std_logic_vector(0 to c_rl);
signal uth_rx_siso : t_dp_siso := c_dp_siso_rdy;
signal uth_rx_sosi : t_dp_sosi;
signal prev_uth_rx_data : std_logic_vector(c_data_w - 1 downto 0) := to_svec(c_data_init -1, c_data_w);
@@ -221,7 +221,7 @@ begin
------------------------------------------------------------------------------
-- Transmit the data block as a UTH frame
- use_tx_hold : if g_use_uth_tx_arch ="HOLD " generate
+ use_tx_hold : if g_use_uth_tx_arch ="HOLD " generate
u_uth_tx : entity work.uth_tx(rtl_hold)
generic map (
g_data_w => c_data_w,
@@ -241,7 +241,7 @@ begin
);
end generate;
- use_tx_delay : if g_use_uth_tx_arch ="DELAY " generate
+ use_tx_delay : if g_use_uth_tx_arch ="DELAY " generate
u_uth_tx : entity work.uth_tx(rtl_delay)
generic map (
g_data_w => c_data_w,
@@ -298,7 +298,7 @@ begin
-- RECEIVER
------------------------------------------------------------------------------
- use_rx_adapt : if g_use_uth_rx_arch ="ADAPT " generate
+ use_rx_adapt : if g_use_uth_rx_arch ="ADAPT " generate
u_uth_rx : entity work.uth_rx(rtl_adapt)
generic map (
g_data_w => c_data_w,
@@ -320,7 +320,7 @@ begin
);
end generate;
- use_rx_hold : if g_use_uth_rx_arch ="HOLD " generate
+ use_rx_hold : if g_use_uth_rx_arch ="HOLD " generate
u_uth_rx : entity work.uth_rx(rtl_hold)
generic map (
g_data_w => c_data_w,
diff --git a/libraries/base/uth/tb/vhdl/tb_uth_dp_packet.vhd b/libraries/base/uth/tb/vhdl/tb_uth_dp_packet.vhd
index 56ff6fbb177f10107d966bb729a2f1d70176aed4..4856877ff83515d21dec60480aea788de68a206a 100644
--- a/libraries/base/uth/tb/vhdl/tb_uth_dp_packet.vhd
+++ b/libraries/base/uth/tb/vhdl/tb_uth_dp_packet.vhd
@@ -94,7 +94,7 @@ architecture tb of tb_uth_dp_packet is
type t_sosi_2arr is array (integer range <> ) of t_dp_sosi_arr(0 to c_nof_input - 1);
type t_data_2arr is array (0 to c_nof_tlen -1, 0 to c_nof_input - 1) of std_logic_vector(g_data_w - 1 downto 0);
- type t_rl_vec_2arr is array (0 to c_nof_tlen -1, 0 to c_nof_input - 1) of std_logic_vector(0 TO c_rl);
+ type t_rl_vec_2arr is array (0 to c_nof_tlen -1, 0 to c_nof_input - 1) of std_logic_vector(0 to c_rl);
signal tb_end_vec : std_logic_vector(c_nof_streams - 1 downto 0) := (others => '0');
signal tb_end : std_logic;
diff --git a/libraries/base/uth/tb/vhdl/tb_uth_terminals.vhd b/libraries/base/uth/tb/vhdl/tb_uth_terminals.vhd
index 30367c7df3d32d0ac6185f96f4169a3cc946192a..cd28d6fde4d74b154b501d959e36602d8864cb50 100644
--- a/libraries/base/uth/tb/vhdl/tb_uth_terminals.vhd
+++ b/libraries/base/uth/tb/vhdl/tb_uth_terminals.vhd
@@ -111,7 +111,7 @@ architecture tb of tb_uth_terminals is
constant c_uth_len_arr : t_natural_arr := array_init(c_uth_frame_len, c_uth_nof_ch);
subtype t_data_arr is t_slv_16_arr(g_nof_input - 1 downto 0); -- width 16 must match c_data_w
- type t_rl_vec_arr is array (g_nof_input - 1 downto 0) of std_logic_vector(0 TO c_rl);
+ type t_rl_vec_arr is array (g_nof_input - 1 downto 0) of std_logic_vector(0 to c_rl);
signal tb_end_vec : std_logic_vector(g_nof_input - 1 downto 0) := (others => '0');
signal tb_end : std_logic;
diff --git a/libraries/base/util/src/vhdl/util_heater_pkg.vhd b/libraries/base/util/src/vhdl/util_heater_pkg.vhd
index 96deee95a837b16f9c5672a91eeea391333fb716..93b72ddaf0b399590c076ed910810085470361f9 100644
--- a/libraries/base/util/src/vhdl/util_heater_pkg.vhd
+++ b/libraries/base/util/src/vhdl/util_heater_pkg.vhd
@@ -57,4 +57,4 @@ end util_heater_pkg;
package body util_heater_pkg is
-end util_heater_pkg;
+end util_heater_pkg;
\ No newline at end of file
diff --git a/libraries/base/util/src/vhdl/util_logic.vhd b/libraries/base/util/src/vhdl/util_logic.vhd
index 374c79f111d9861ac6d1a97e9aa4b2833a66e0db..4d3f9425028439357e75a2e01eb82bcf715ab710 100644
--- a/libraries/base/util/src/vhdl/util_logic.vhd
+++ b/libraries/base/util/src/vhdl/util_logic.vhd
@@ -84,4 +84,4 @@ begin
out_dat <= out_dat_reg(g_nof_reg);
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/dsp/beamformer/src/vhdl/beamformer.vhd b/libraries/dsp/beamformer/src/vhdl/beamformer.vhd
index d1424b3a5fc01db80281061a669780ddd43a2f20..2ed92578d202ce242531a27a9d051efa7a03c6b9 100644
--- a/libraries/dsp/beamformer/src/vhdl/beamformer.vhd
+++ b/libraries/dsp/beamformer/src/vhdl/beamformer.vhd
@@ -150,7 +150,7 @@ begin
generic map (
g_technology => g_technology,
g_ram => c_common_ram_crw_crw_ram,
- g_init_file => sel_a_b(g_weights_file ="UNUSED ", "UNUSED", g_weights_file & "_" & natural'image(i) & ".hex"),
+ g_init_file => sel_a_b(g_weights_file ="UNUSED ", "UNUSED", g_weights_file & "_" & natural'image(i) & ".hex"),
g_true_dual_port => g_weights_ram_dual_port
)
port map (
diff --git a/libraries/dsp/beamformer/tb/vhdl/tb_beamformer.vhd b/libraries/dsp/beamformer/tb/vhdl/tb_beamformer.vhd
index 59c8ec7d2941d5f3496af33f55f5c9ad094bc1f3..c1d69fc2d41a7254b5a7c66570fbabe3dacf2f56 100644
--- a/libraries/dsp/beamformer/tb/vhdl/tb_beamformer.vhd
+++ b/libraries/dsp/beamformer/tb/vhdl/tb_beamformer.vhd
@@ -169,7 +169,7 @@ architecture tb of tb_beamformer is
for I in 0 to g_nof_inputs - 1 loop
for J in 0 to g_nof_weights - 1 loop
-- write MM page
- mmf_mm_bus_wr(c_mm_file_ram_beamformer, I * g_nof_weights + J, (J + 1) *2**16 + J +1, mm_clk);
+ mmf_mm_bus_wr(c_mm_file_ram_beamformer, I * g_nof_weights + J, (J + 1) * 2**16 + J +1, mm_clk);
end loop;
end loop;
@@ -327,5 +327,4 @@ architecture tb of tb_beamformer is
src_out => beamformer_src_out
);
-end tb;
-
+end tb;
\ No newline at end of file
diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd
index be91592efd4fe12e048960a708c7368648ee0e5d..eb96e06bf9c81445926f1c8aef8541f49a483e5b 100644
--- a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd
@@ -137,7 +137,7 @@ architecture str of mmm_unb1_fn_bf is
constant c_tse_clk_period : time := 8 ns;
constant c_sim_node_type : string(1 to 2) := sel_a_b(g_sim_node_nr <4, "FN", "BN");
- constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type ="BN ", g_sim_node_nr -4, g_sim_node_nr);
+ constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type ="BN ", g_sim_node_nr -4, g_sim_node_nr);
signal i_mm_clk : std_logic := '1';
signal i_tse_clk : std_logic := '1';
@@ -445,6 +445,3 @@ end;
-
-
-
diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/unb1_fn_bf.vhd b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/unb1_fn_bf.vhd
index a5d3403cc7f2018be12328e2f0cbc84560794677..e2d58a79fbf3e7241f2d35a0ca11bd31e0ad30a6 100644
--- a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/unb1_fn_bf.vhd
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/unb1_fn_bf.vhd
@@ -65,8 +65,8 @@ entity unb1_fn_bf is
-- 1GbE Control Interface
ETH_clk : in std_logic;
- ETH_SGin : IN std_logic;
- ETH_SGout : OUT std_logic
+ ETH_SGin : in std_logic;
+ ETH_SGout : out std_logic
);
end unb1_fn_bf;
@@ -408,6 +408,3 @@ end;
-
-
-
diff --git a/libraries/dsp/bf/src/vhdl/bf.vhd b/libraries/dsp/bf/src/vhdl/bf.vhd
index b748fa785f6c5d7d214d0543224af1e952510381..75ad914c1367f810b21e2650e2010f1618ddad09 100644
--- a/libraries/dsp/bf/src/vhdl/bf.vhd
+++ b/libraries/dsp/bf/src/vhdl/bf.vhd
@@ -183,4 +183,4 @@ begin
in_siso_arr <= in_siso_2arr(0);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/dsp/bf/src/vhdl/bf_pkg.vhd b/libraries/dsp/bf/src/vhdl/bf_pkg.vhd
index b46eb8173445749992d349d4e2e692eee95313be..c3114fe22df5b0eb0126bd5b3efeca611c8b66e6 100644
--- a/libraries/dsp/bf/src/vhdl/bf_pkg.vhd
+++ b/libraries/dsp/bf/src/vhdl/bf_pkg.vhd
@@ -55,4 +55,4 @@ package bf_pkg is
end bf_pkg;
package body bf_pkg is
-end bf_pkg;
+end bf_pkg;
\ No newline at end of file
diff --git a/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd b/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
index 5c23374aea36538d40e3b034701456790d3b727d..d350d28cb04d489ba231dae8e4909fc1711b665a 100644
--- a/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
+++ b/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
@@ -95,7 +95,7 @@ architecture str of mmm_unb1_correlator is
constant c_mm_clk_period : time := 8 ns; -- 125 MHz
constant c_sim_node_type : string(1 to 2) := sel_a_b(g_sim_node_nr <4, "FN", "BN");
- constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type ="BN ", g_sim_node_nr -4, g_sim_node_nr);
+ constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type ="BN ", g_sim_node_nr -4, g_sim_node_nr);
signal i_mm_clk : std_logic := '1';
diff --git a/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/unb1_correlator.vhd b/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/unb1_correlator.vhd
index 84599589ae9bb7946b8562fd4a1167fc66c77377..f78292132557fa8fa61ac8676df75717327c3d81 100644
--- a/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/unb1_correlator.vhd
+++ b/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/unb1_correlator.vhd
@@ -58,8 +58,8 @@ entity unb1_correlator is
-- 1GbE Control Interface
ETH_clk : in std_logic;
- ETH_SGin : IN std_logic;
- ETH_SGout : OUT std_logic
+ ETH_SGin : in std_logic;
+ ETH_SGout : out std_logic
);
end unb1_correlator;
@@ -433,4 +433,4 @@ begin
eth1g_ram_miso => eth1g_ram_miso
);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/dsp/correlator/src/vhdl/corr_folder.vhd b/libraries/dsp/correlator/src/vhdl/corr_folder.vhd
index 5a73b748b4ececf8b8d3a72345d9350e611f2acf..37cbdaa9cd7b2337c6f4fdee3a03272986671bb7 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_folder.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_folder.vhd
@@ -151,4 +151,4 @@ begin
src_out_arr <= snk_in_arr;
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/dsp/correlator/src/vhdl/corr_folder_2arr_2.vhd b/libraries/dsp/correlator/src/vhdl/corr_folder_2arr_2.vhd
index 4893c385119584f13e570dd650c8a132d973c870..20e8a76939fbebe60b45bf67183eb57241a5a1e2 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_folder_2arr_2.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_folder_2arr_2.vhd
@@ -144,4 +144,4 @@ begin
end generate;
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/dsp/correlator/src/vhdl/corr_output_framer.vhd b/libraries/dsp/correlator/src/vhdl/corr_output_framer.vhd
index aaa63c18412ac0aa59ba8a938380ebbe8e6c8e07..5d7fc1371fe49fea0323c7d1ac00888c125a9909 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_output_framer.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_output_framer.vhd
@@ -169,4 +169,4 @@ begin
end loop;
end process;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/dsp/correlator/src/vhdl/corr_permutor_pkg.vhd b/libraries/dsp/correlator/src/vhdl/corr_permutor_pkg.vhd
index a2eca4702f098cada06e4136017d0db31fddc603..f1765a0eaa1fd341b7dea1b33cf24795026fcac7 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_permutor_pkg.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_permutor_pkg.vhd
@@ -151,6 +151,4 @@ package body corr_permutor_pkg is
return v_result;
end corr_permute;
-end corr_permutor_pkg;
-
-
+end corr_permutor_pkg;
\ No newline at end of file
diff --git a/libraries/dsp/correlator/src/vhdl/corr_unfolder.vhd b/libraries/dsp/correlator/src/vhdl/corr_unfolder.vhd
index 1d52e56a96e3f3f90eb93aa098ea1646b429e4eb..cfe13b4daa109a79d99ba47e8ff8586a38b08d50 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_unfolder.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_unfolder.vhd
@@ -155,4 +155,4 @@ begin
src_out_arr <= snk_in_arr;
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/dsp/fft/src/vhdl/fft_lfsr.vhd b/libraries/dsp/fft/src/vhdl/fft_lfsr.vhd
index 37e298ea68d36681f7e6e37c9cdd0e72dc24a4d7..499c9a413c559f9363b6b758a35aaa5b29f8e571 100644
--- a/libraries/dsp/fft/src/vhdl/fft_lfsr.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_lfsr.vhd
@@ -96,4 +96,4 @@ begin
end if;
end process;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/dsp/fft/src/vhdl/fft_pkg.vhd b/libraries/dsp/fft/src/vhdl/fft_pkg.vhd
index 51f64966e0232554ddaababf6b24757d227a42e4..0d45def4fcb92133cc1dd638e1b68223e83f24d6 100644
--- a/libraries/dsp/fft/src/vhdl/fft_pkg.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_pkg.vhd
@@ -168,4 +168,4 @@ package body fft_pkg is
return to_uint(fft_shift(to_uvec(bin, w)));
end;
-end fft_pkg;
+end fft_pkg;
\ No newline at end of file
diff --git a/libraries/dsp/fft/src/vhdl/fft_r2_pipe.vhd b/libraries/dsp/fft/src/vhdl/fft_r2_pipe.vhd
index 4165fe49918105f44484529503b4b8ae4000855b..488d803aaffafe5208b04dd793f22a2b35ed556e 100644
--- a/libraries/dsp/fft/src/vhdl/fft_r2_pipe.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_r2_pipe.vhd
@@ -380,4 +380,4 @@ begin
out_dat => out_raw_im
);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/dsp/fft/src/vhdl/fft_reorder_sepa_pipe.vhd b/libraries/dsp/fft/src/vhdl/fft_reorder_sepa_pipe.vhd
index b0608375b6aa767be642682c247f9ce328e0e330..e21fd2008b15801123b3eb7b34b95c2514a43c69 100644
--- a/libraries/dsp/fft/src/vhdl/fft_reorder_sepa_pipe.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_reorder_sepa_pipe.vhd
@@ -347,5 +347,4 @@ begin
out_val <= out_val_i;
end generate;
-end rtl;
-
+end rtl;
\ No newline at end of file
diff --git a/libraries/dsp/fft/src/vhdl/fft_sepa.vhd b/libraries/dsp/fft/src/vhdl/fft_sepa.vhd
index 1c51049e8fea03585976f9b17f84ec31f4434596..90d5146185a2b58842f39fd4b658e6475f9b7d36 100644
--- a/libraries/dsp/fft/src/vhdl/fft_sepa.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_sepa.vhd
@@ -188,5 +188,4 @@ begin
out_dat <= r.out_dat;
out_val <= r.out_val;
-end rtl;
-
+end rtl;
\ No newline at end of file
diff --git a/libraries/dsp/fft/src/vhdl/fft_sepa_wide.vhd b/libraries/dsp/fft/src/vhdl/fft_sepa_wide.vhd
index 21613491a5ed21374141866989b8103aa1be8a52..5a031ede6677123ff93b08d84c926ea6149641fd 100644
--- a/libraries/dsp/fft/src/vhdl/fft_sepa_wide.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_sepa_wide.vhd
@@ -184,9 +184,9 @@ begin
-- once every two clock cylces.
gen_compose_zip_matrix : for I in g_fft.wb_factor / 2 - 1 downto 0 generate
zip_in_matrix(2 * I)(0) (c_dat_w - 1 downto 0) <= rd_dat_arr(I);
- zip_in_matrix(2 * I)(1) (c_dat_w - 1 downto 0) <= rd_dat_arr((g_fft.wb_factor - I) rem g_fft.wb_factor) when r.count_up = 0 else rd_dat_arr(g_fft.wb_factor - 1 -I);
+ zip_in_matrix(2 * I)(1) (c_dat_w - 1 downto 0) <= rd_dat_arr((g_fft.wb_factor - I) rem g_fft.wb_factor) when r.count_up = 0 else rd_dat_arr(g_fft.wb_factor - 1 - I);
zip_in_matrix(2 * I + 1)(0)(c_dat_w - 1 downto 0) <= rd_dat_arr(I);
- zip_in_matrix(2 * I + 1)(1)(c_dat_w - 1 downto 0) <= rd_dat_arr(g_fft.wb_factor - 1 -I);
+ zip_in_matrix(2 * I + 1)(1)(c_dat_w - 1 downto 0) <= rd_dat_arr(g_fft.wb_factor - 1 - I);
zip_in_val(2 * I) <= r.val_even;
zip_in_val(2 * I + 1) <= r.val_odd;
end generate;
@@ -329,5 +329,4 @@ begin
out_im_arr(I) <= resize_fft_svec(out_dat_arr(I)(c_nof_complex * c_out_w - 1 downto c_out_w));
end generate;
-end rtl;
-
+end rtl;
\ No newline at end of file
diff --git a/libraries/dsp/fft/src/vhdl/fft_wide_unit.vhd b/libraries/dsp/fft/src/vhdl/fft_wide_unit.vhd
index ed165c0bf3d86672291a7f80e432cb69b24aefd9..c14177cc4f72b70a3cd1a6e7d2fa28f91462dddc 100644
--- a/libraries/dsp/fft/src/vhdl/fft_wide_unit.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_wide_unit.vhd
@@ -227,5 +227,4 @@ begin
out_sosi_arr(I) <= fft_out_sosi_arr(I);
end generate;
-end str;
-
+end str;
\ No newline at end of file
diff --git a/libraries/dsp/fft/src/vhdl/fft_wide_unit_control.vhd b/libraries/dsp/fft/src/vhdl/fft_wide_unit_control.vhd
index 5eacb922f4d6b3d1054ded82843ed4fefa7b015c..935c2a44cc813b141fb33c126f857195634b3fee 100644
--- a/libraries/dsp/fft/src/vhdl/fft_wide_unit_control.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_wide_unit_control.vhd
@@ -292,5 +292,4 @@ begin
out_sosi_arr(I) <= r.out_sosi_arr(I);
end generate;
-end rtl;
-
+end rtl;
\ No newline at end of file
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_functions.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_functions.vhd
index f20fdf51c9a50eeaee05320c8b1e02aa01929324..65dd8c7925e36efdf018b1a529e2166802938f42 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_functions.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_functions.vhd
@@ -95,4 +95,4 @@ begin
wait;
end process;
-end tb;
+end tb;
\ No newline at end of file
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_pkg.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_pkg.vhd
index b06f67ce3cc8d6d32964293fa255c21e3a6e3c12..6f8eeb5041888dff8879a0482fef0aca8df39ff9 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_pkg.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_pkg.vhd
@@ -615,4 +615,4 @@ package body tb_fft_pkg is
-- proc_common_close_file(v_file_status, v_in_file); -- Close the file
-- END proc_prepare_input_data;
-end tb_fft_pkg;
+end tb_fft_pkg;
\ No newline at end of file
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_sepa.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_sepa.vhd
index 8eb499f8720c49986dd69faad53699cc4bff1181..a688ad61c7afa30ac4e09c26cff5ca8dcbb248cc 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_sepa.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_sepa.vhd
@@ -212,6 +212,4 @@ begin
end if;
end process p_tester;
-end tb;
-
-
+end tb;
\ No newline at end of file
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd
index cd0b81a7c6768050cd42b7e858fca89f59ba461b..dca54e3ac8065c8aae75cfaef0414093e6a0832b 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd
@@ -122,7 +122,7 @@ architecture tb of tb_fft_switch is
signal out_eop : std_logic := '0';
signal out_sync : std_logic := '0';
- signal dly_val : std_logic_vector(0 TO c_dly) := (others => '0');
+ signal dly_val : std_logic_vector(0 to c_dly) := (others => '0');
signal dly_a : t_integer_arr(0 to c_dly) := (others => 0);
signal dly_b : t_integer_arr(0 to c_dly) := (others => 0);
signal exp_val : std_logic := '0';
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_wide_unit.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_wide_unit.vhd
index 342ef803f4f9a6b5fd0ebde954e2df1add01a6b0..6d7f37aac397176a35acf9f198b8acb7ebbded24 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_wide_unit.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_wide_unit.vhd
@@ -101,18 +101,18 @@ architecture tb of tb_fft_wide_unit is
constant c_normal : boolean := TRUE;
-- input from uniform noise file created automatically by MATLAB testFFT_input.m
- constant c_noiseInputFile : string := "data/test/in/uniNoise_p" & natural'image(g_fft.nof_points) & "_b" & natural'image(c_twiddle_w) &"_in.txt ";
- constant c_noiseGoldenFile : string := "data/test/out/uniNoise_p" & natural'image(g_fft.nof_points) & "_b" & natural'image(c_twiddle_w) &"_tb " & natural'image(wTyp'length) &"_out.txt ";
+ constant c_noiseInputFile : string := "data/test/in/uniNoise_p" & natural'image(g_fft.nof_points) & "_b" & natural'image(c_twiddle_w) &"_in.txt ";
+ constant c_noiseGoldenFile : string := "data/test/out/uniNoise_p" & natural'image(g_fft.nof_points) & "_b" & natural'image(c_twiddle_w) &"_tb " & natural'image(wTyp'length) &"_out.txt ";
constant c_noiseOutputFile : string := "data/test/out/uniNoise_out.txt";
-- input from sinus file. Data is from diag_wg_wideband.
- constant c_sinusInputFile : string := "data/test/in/sinus_p" & natural'image(g_fft.nof_points) & "_b" & natural'image(g_fft.in_dat_w) &"_in.txt ";
- constant c_sinusGoldenFile : string := "data/test/out/sinus_p" & natural'image(g_fft.nof_points) & "_b" & natural'image(g_fft.in_dat_w) &"_tb " & natural'image(wTyp'length) &"_out.txt ";
+ constant c_sinusInputFile : string := "data/test/in/sinus_p" & natural'image(g_fft.nof_points) & "_b" & natural'image(g_fft.in_dat_w) &"_in.txt ";
+ constant c_sinusGoldenFile : string := "data/test/out/sinus_p" & natural'image(g_fft.nof_points) & "_b" & natural'image(g_fft.in_dat_w) &"_tb " & natural'image(wTyp'length) &"_out.txt ";
constant c_sinusOutputFile : string := "data/test/out/sinus_out.txt";
-- input from combined sinus with noise file. Real part is sinus, imaginary part is noise
- constant c_sinNoiseInputFile : string := "data/test/in/sinNoise_p" & natural'image(g_fft.nof_points) & "_b" & natural'image(g_fft.in_dat_w) &"_in.txt ";
- constant c_sinNoiseGoldenFile : string := "data/test/out/sinNoise_p" & natural'image(g_fft.nof_points) & "_b" & natural'image(g_fft.in_dat_w) &"_tb " & natural'image(wTyp'length) &"_out.txt ";
+ constant c_sinNoiseInputFile : string := "data/test/in/sinNoise_p" & natural'image(g_fft.nof_points) & "_b" & natural'image(g_fft.in_dat_w) &"_in.txt ";
+ constant c_sinNoiseGoldenFile : string := "data/test/out/sinNoise_p" & natural'image(g_fft.nof_points) & "_b" & natural'image(g_fft.in_dat_w) &"_tb " & natural'image(wTyp'length) &"_out.txt ";
constant c_sinNoiseOutputFile : string := "data/test/out/sinNoise_out.txt";
-- input from impulse files
@@ -125,9 +125,9 @@ architecture tb of tb_fft_wide_unit is
constant c_2xrealImpulseGoldenFile : string := "data/2xreal_impulse_p" & natural'image(g_fft.nof_points) & "_b" & natural'image(c_twiddle_w) & "_out.txt";
constant c_2xrealImpulseOutputFile : string := "data/2xreal_impulse_out.txt";
- constant c_2xrealNoiseGoldenFile : string := "data/test/out/uniNoise_2xreal_p" & natural'image(g_fft.nof_points) & "_b" & natural'image(c_twiddle_w) &"_tb " & natural'image(wTyp'length) &"_out.txt ";
- constant c_2xrealSinusGoldenFile : string := "data/test/out/sinus_2xreal_p" & natural'image(g_fft.nof_points) & "_b" & natural'image(g_fft.in_dat_w) &"_tb " & natural'image(wTyp'length) &"_out.txt ";
- constant c_2xrealSinNoiseGoldenFile : string := "data/test/out/sinNoise_2xreal_p" & natural'image(g_fft.nof_points) & "_b" & natural'image(g_fft.in_dat_w) &"_tb " & natural'image(wTyp'length) &"_out.txt ";
+ constant c_2xrealNoiseGoldenFile : string := "data/test/out/uniNoise_2xreal_p" & natural'image(g_fft.nof_points) & "_b" & natural'image(c_twiddle_w) &"_tb " & natural'image(wTyp'length) &"_out.txt ";
+ constant c_2xrealSinusGoldenFile : string := "data/test/out/sinus_2xreal_p" & natural'image(g_fft.nof_points) & "_b" & natural'image(g_fft.in_dat_w) &"_tb " & natural'image(wTyp'length) &"_out.txt ";
+ constant c_2xrealSinNoiseGoldenFile : string := "data/test/out/sinNoise_2xreal_p" & natural'image(g_fft.nof_points) & "_b" & natural'image(g_fft.in_dat_w) &"_tb " & natural'image(wTyp'length) &"_out.txt ";
-- determine active stimuli and result files
constant c_preSelImpulseInputFile : string := sel_a_b(g_use_2xreal_inputs, c_2xrealImpulseInputFile, c_impulseInputFile);
diff --git a/libraries/dsp/filter/src/vhdl/fil_pkg.vhd b/libraries/dsp/filter/src/vhdl/fil_pkg.vhd
index c243c5fb3598534b458105e5c583b262e3df9eed..1f1fa5d716736e9b28d713be5014fa5731935591 100644
--- a/libraries/dsp/filter/src/vhdl/fil_pkg.vhd
+++ b/libraries/dsp/filter/src/vhdl/fil_pkg.vhd
@@ -69,4 +69,4 @@ package fil_pkg is
end package fil_pkg;
package body fil_pkg is
-end fil_pkg;
+end fil_pkg;
\ No newline at end of file
diff --git a/libraries/dsp/filter/src/vhdl/fil_ppf_filter.vhd b/libraries/dsp/filter/src/vhdl/fil_ppf_filter.vhd
index 49b9c8529b15144a6b0f9f91e9a1ec5fbdbaa0e0..3aa96401872238f6fcec2240aba68ed571932ee0 100644
--- a/libraries/dsp/filter/src/vhdl/fil_ppf_filter.vhd
+++ b/libraries/dsp/filter/src/vhdl/fil_ppf_filter.vhd
@@ -142,4 +142,4 @@ begin
result <= RESIZE_SVEC(requant_out, result'length);
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/dsp/filter/src/vhdl/fil_ppf_wide.vhd b/libraries/dsp/filter/src/vhdl/fil_ppf_wide.vhd
index 1c1b95d5c6fe87832d8b0cb03e2d9508f5e52636..44e03f5b95d3dd0ba4a6fb8ba26a96c776024df4 100644
--- a/libraries/dsp/filter/src/vhdl/fil_ppf_wide.vhd
+++ b/libraries/dsp/filter/src/vhdl/fil_ppf_wide.vhd
@@ -218,7 +218,7 @@ begin
begin
for P in 0 to g_fil_ppf.wb_factor - 1 loop
if g_big_endian_wb_in = true then
- vP := g_fil_ppf.wb_factor - 1 -P; -- convert input big endian time [0,1,2,3] to P [3,2,1,0] index mapping to internal little endian
+ vP := g_fil_ppf.wb_factor - 1 - P; -- convert input big endian time [0,1,2,3] to P [3,2,1,0] index mapping to internal little endian
else
vP := P; -- keep input little endian time [0,1,2,3] to P [0,1,2,3] index mapping
end if;
@@ -259,7 +259,7 @@ begin
begin
for P in 0 to g_fil_ppf.wb_factor - 1 loop
if g_big_endian_wb_out = true then
- vP := g_fil_ppf.wb_factor - 1 -P; -- convert internal little endian to output big endian time [0,1,2,3] to P [3,2,1,0] index mapping
+ vP := g_fil_ppf.wb_factor - 1 - P; -- convert internal little endian to output big endian time [0,1,2,3] to P [3,2,1,0] index mapping
else
vP := P; -- keep internal little endian for output little endian time [0,1,2,3] to P [0,1,2,3] index mapping
end if;
diff --git a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd
index be472ba8c1dff51404514807dadf98ed9177e66a..a893ba941da612971eebef710fd9b1ea9830193d 100644
--- a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd
+++ b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd
@@ -300,7 +300,7 @@ begin
-- Reverse the coeffs per tap
for J in 0 to g_fil_ppf.nof_taps - 1 loop
for I in 0 to g_fil_ppf.nof_bands - 1 loop
- v_coefs_flip_arr(J * g_fil_ppf.nof_bands + g_fil_ppf.nof_bands - 1 -I) := ref_coefs_arr(J*g_fil_ppf.nof_bands+I);
+ v_coefs_flip_arr(J * g_fil_ppf.nof_bands + g_fil_ppf.nof_bands - 1 - I) := ref_coefs_arr(J * g_fil_ppf.nof_bands + I);
end loop;
end loop;
-- Expand the channels (for one stream)
diff --git a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide.vhd b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide.vhd
index cfed7edcd20a2832113e94ce9c139f158b00f935..92df5cc4a856054a1fbdd95d244ca56ec184c9da 100644
--- a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide.vhd
+++ b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide.vhd
@@ -215,7 +215,7 @@ begin
-- Reverse the coeffs per tap
for J in 0 to g_fil_ppf.nof_taps - 1 loop
for I in 0 to g_fil_ppf.nof_bands - 1 loop
- v_coefs_flip_arr(J * g_fil_ppf.nof_bands + g_fil_ppf.nof_bands - 1 -I) := ref_coefs_arr(J*g_fil_ppf.nof_bands+I);
+ v_coefs_flip_arr(J * g_fil_ppf.nof_bands + g_fil_ppf.nof_bands - 1 - I) := ref_coefs_arr(J * g_fil_ppf.nof_bands + I);
end loop;
end loop;
-- Distribute over wb_factor and expand the channels (for one stream)
@@ -258,7 +258,7 @@ begin
for J in 0 to g_fil_ppf.nof_taps - 1 loop
v_mif_index := P * g_fil_ppf.nof_taps + J;
v_mif_base := v_mif_index * c_mif_coef_mem_span;
- v_coef_offset := g_fil_ppf.nof_bands * (J + 1) - 1 -P; -- coeff in MIF are in flipped order, unflip this in v_coef_index
+ v_coef_offset := g_fil_ppf.nof_bands * (J + 1) - 1 - P; -- coeff in MIF are in flipped order, unflip this in v_coef_index
for I in 0 to c_nof_bands_per_mif - 1 loop
proc_mem_mm_bus_rd(v_mif_base + I, clk, ram_coefs_miso, ram_coefs_mosi);
proc_mem_mm_bus_rd_latency(1, clk);
@@ -334,7 +334,7 @@ begin
if g_big_endian_wb_out = false then
vP := P;
else
- vP := g_fil_ppf.wb_factor - 1 -P;
+ vP := g_fil_ppf.wb_factor - 1 - P;
end if;
-- Output data width must be large enough to fit the coefficients width, this is verified by p_verify_out_dat_width
diff --git a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide_file_data.vhd b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide_file_data.vhd
index 75eecfd1c4efa252619c01f6e1b7ab9457bb4f2a..37267f0b00fb3b84980b29f8db2a5a7132fdb2af 100644
--- a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide_file_data.vhd
+++ b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide_file_data.vhd
@@ -244,7 +244,7 @@ begin
for K in 0 to c_nof_channels - 1 loop -- serial
for P in 0 to g_fil_ppf.wb_factor - 1 loop -- parallel
if g_big_endian_wb_in = TRUE then
- vP := g_fil_ppf.wb_factor - 1 -P; -- time to wideband big endian
+ vP := g_fil_ppf.wb_factor - 1 - P; -- time to wideband big endian
else
vP := P; -- time to wideband little endian
end if;
@@ -360,7 +360,7 @@ begin
if out_val = '1' then
for P in 0 to g_fil_ppf.wb_factor - 1 loop -- parallel
if g_big_endian_wb_out = true then
- vP := g_fil_ppf.wb_factor - 1 -P; -- time to wideband big endian
+ vP := g_fil_ppf.wb_factor - 1 - P; -- time to wideband big endian
else
vP := P; -- time to wideband little endian
end if;
@@ -412,7 +412,7 @@ begin
begin
for P in 0 to g_fil_ppf.wb_factor - 1 loop
if g_big_endian_wb_out = true then
- vP := g_fil_ppf.wb_factor - 1 -P;
+ vP := g_fil_ppf.wb_factor - 1 - P;
else
vP := P;
end if;
diff --git a/libraries/dsp/fringe_stop/src/vhdl/fringe_stop_unit.vhd b/libraries/dsp/fringe_stop/src/vhdl/fringe_stop_unit.vhd
index b05a38208cd1a8bfdac40c6eb7752d5321ecb1a8..3095677f685f27cf2e39db6ee9fa2aa7373d26cd 100644
--- a/libraries/dsp/fringe_stop/src/vhdl/fringe_stop_unit.vhd
+++ b/libraries/dsp/fringe_stop/src/vhdl/fringe_stop_unit.vhd
@@ -472,6 +472,3 @@ begin
end process;
end str;
-
-
-
diff --git a/libraries/dsp/fringe_stop/tb/vhdl/tb_fringe_stop_unit.vhd b/libraries/dsp/fringe_stop/tb/vhdl/tb_fringe_stop_unit.vhd
index 33e683bef87d6bb79008b757771c03cef7d5a255..200927cc837b5feb5a9b9b34ea2294abe8e43cdb 100644
--- a/libraries/dsp/fringe_stop/tb/vhdl/tb_fringe_stop_unit.vhd
+++ b/libraries/dsp/fringe_stop/tb/vhdl/tb_fringe_stop_unit.vhd
@@ -190,7 +190,7 @@ begin
if g_sim_type = 0 then
for J in 0 to g_nof_channels - 1 loop
fs_offset_matrix(I,J) <= I + 10 + J;
- fs_step_matrix(I,J) <= 2 ** (g_fs_step_w - 1) - 1 -g_nof_channels+J;
+ fs_step_matrix(I,J) <= 2 ** (g_fs_step_w - 1) - 1 - g_nof_channels + J;
end loop;
end if;
@@ -198,7 +198,7 @@ begin
if g_sim_type = 1 then
for J in 0 to g_nof_channels - 1 loop
fs_offset_matrix(I,J) <= 2 ** g_fs_offset_w - 1;
- fs_step_matrix(I,J) <= 2 ** (g_fs_step_w - 1) - 1 -g_nof_channels+J;
+ fs_step_matrix(I,J) <= 2 ** (g_fs_step_w - 1) - 1 - g_nof_channels + J;
end loop;
end if;
@@ -432,6 +432,4 @@ begin
tb_end <= '1' when r.loop_cnt = 4 else '0';
-end tb;
-
-
+end tb;
\ No newline at end of file
diff --git a/libraries/dsp/fringe_stop/tb/vhdl/tb_mmf_fringe_stop_unit.vhd b/libraries/dsp/fringe_stop/tb/vhdl/tb_mmf_fringe_stop_unit.vhd
index c204e442686e10895ebc426adf2376c748c9e803..5ce5f30518faba291ab9b24c184085da5398ac53 100644
--- a/libraries/dsp/fringe_stop/tb/vhdl/tb_mmf_fringe_stop_unit.vhd
+++ b/libraries/dsp/fringe_stop/tb/vhdl/tb_mmf_fringe_stop_unit.vhd
@@ -392,6 +392,4 @@ begin
wait;
end process;
-end tb;
-
-
+end tb;
\ No newline at end of file
diff --git a/libraries/dsp/fringe_stop/tb/vhdl/tb_tb_fringe_stop_unit.vhd b/libraries/dsp/fringe_stop/tb/vhdl/tb_tb_fringe_stop_unit.vhd
index f370ffc7a443363092bbbb75b77fc4dfe96983e2..bfe184787dbe0f63726eb2f8bcd57111bcb7ecde 100644
--- a/libraries/dsp/fringe_stop/tb/vhdl/tb_tb_fringe_stop_unit.vhd
+++ b/libraries/dsp/fringe_stop/tb/vhdl/tb_tb_fringe_stop_unit.vhd
@@ -59,6 +59,4 @@ begin
sim_minus_phi : entity work.tb_fringe_stop_unit generic map (I, 8, 10, 31, 17, 4, 9, TRUE);
end generate;
-end tb;
-
-
+end tb;
\ No newline at end of file
diff --git a/libraries/dsp/fringe_stop/tb/vhdl/tb_tb_mmf_fringe_stop_unit.vhd b/libraries/dsp/fringe_stop/tb/vhdl/tb_tb_mmf_fringe_stop_unit.vhd
index 1063fefdb9b6d4a78c833164b32c147c3e3c0384..7890128c444a6f6708b0043a24a9e60c2c075529 100644
--- a/libraries/dsp/fringe_stop/tb/vhdl/tb_tb_mmf_fringe_stop_unit.vhd
+++ b/libraries/dsp/fringe_stop/tb/vhdl/tb_tb_mmf_fringe_stop_unit.vhd
@@ -44,6 +44,4 @@ begin
u_mm_slower_no_gap : entity work.tb_mmf_fringe_stop_unit generic map (0, TRUE, FALSE, 0); -- use no gap to enable verification of phasor period
u_mm_faster_with_gap : entity work.tb_mmf_fringe_stop_unit generic map (1, TRUE, TRUE, 1); -- use gap to verify valid gaps
-end tb;
-
-
+end tb;
\ No newline at end of file
diff --git a/libraries/dsp/iquv/src/vhdl/iquv_iab.vhd b/libraries/dsp/iquv/src/vhdl/iquv_iab.vhd
index 427eacdfba3bc47b5ceeeb802f3ab3d2f39e2568..35ef5e0e37d07f5f8cb75eef2bffc016e5823dcd 100644
--- a/libraries/dsp/iquv/src/vhdl/iquv_iab.vhd
+++ b/libraries/dsp/iquv/src/vhdl/iquv_iab.vhd
@@ -643,4 +643,4 @@ begin
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/dsp/iquv/tb/vhdl/tb_iquv.vhd b/libraries/dsp/iquv/tb/vhdl/tb_iquv.vhd
index 70934c09d6577d6c01db7bcc08bc634f8385fe6e..4888101291d3ebc50fe70b665d0e097b56be429a 100644
--- a/libraries/dsp/iquv/tb/vhdl/tb_iquv.vhd
+++ b/libraries/dsp/iquv/tb/vhdl/tb_iquv.vhd
@@ -195,13 +195,13 @@ begin
for BLOCKCOUNT in 0 to 0 loop -- Repeat as needed
in_complex.im <= TO_DP_DSP_DATA(0); -- Keep the imaginary part 0
- for FBin IN 0 to c_npoints - 1 loop -- BLOCK cycle one
+ for FBin in 0 to c_npoints - 1 loop -- BLOCK cycle one
in_complex.re <= TO_DP_DSP_DATA(FBIN); -- The real part of the X pol counts up
wait until rising_edge(dp_clk) and valid_enable = '1';
in_complex.re <= TO_DP_DSP_DATA(0); -- The real part of the Y pol stays 0
wait until rising_edge(dp_clk) and valid_enable = '1';
end loop;
- for FBin IN 0 to c_npoints - 1 loop -- BLOCK cycle two
+ for FBin in 0 to c_npoints - 1 loop -- BLOCK cycle two
in_complex.re <= TO_DP_DSP_DATA(0); -- The real part of the X pol stays 0
wait until rising_edge(dp_clk) and valid_enable = '1';
in_complex.re <= TO_DP_DSP_DATA(FBIN); -- The real part of the Y pol counts up
@@ -209,13 +209,13 @@ begin
end loop;
in_complex.re <= TO_DP_DSP_DATA(0); -- Keep the real part 0
- for FBin IN 0 to c_npoints - 1 loop -- BLOCK cycle three
+ for FBin in 0 to c_npoints - 1 loop -- BLOCK cycle three
in_complex.im <= TO_DP_DSP_DATA(FBIN); -- The im part of the X pol counts up
wait until rising_edge(dp_clk) and valid_enable = '1';
in_complex.im <= TO_DP_DSP_DATA(0); -- The im part of the Y pol stays 0
wait until rising_edge(dp_clk) and valid_enable = '1';
end loop;
- for FBin IN 0 to c_npoints - 1 loop -- BLOCK cycle four
+ for FBin in 0 to c_npoints - 1 loop -- BLOCK cycle four
in_complex.im <= TO_DP_DSP_DATA(0); -- The im part of the X pol stays 0
wait until rising_edge(dp_clk) and valid_enable = '1';
in_complex.im <= TO_DP_DSP_DATA(FBIN); -- The im part of the Y pol counts up
@@ -223,21 +223,21 @@ begin
end loop;
in_complex.im <= TO_DP_DSP_DATA(0); -- Keep the imaginary part 0
- for FBin IN 0 to c_npoints - 1 loop -- BLOCK cycle five
+ for FBin in 0 to c_npoints - 1 loop -- BLOCK cycle five
in_complex.re <= TO_DP_DSP_DATA(FBIN); -- The real part of the X pol counts up
wait until rising_edge(dp_clk) and valid_enable = '1';
in_complex.re <= TO_DP_DSP_DATA(FBIN); -- The real part of the Y pol counts up
wait until rising_edge(dp_clk) and valid_enable = '1';
end loop;
in_complex.re <= TO_DP_DSP_DATA(0); -- Keep the real part 0
- for FBin IN 0 to c_npoints - 1 loop -- BLOCK cycle six
+ for FBin in 0 to c_npoints - 1 loop -- BLOCK cycle six
in_complex.im <= TO_DP_DSP_DATA(FBIN); -- The im part of the X pol counts up
wait until rising_edge(dp_clk) and valid_enable = '1';
in_complex.im <= TO_DP_DSP_DATA(FBIN); -- The im part of the Y pol counts up
wait until rising_edge(dp_clk) and valid_enable = '1';
end loop;
- for FBin IN 0 to c_npoints - 1 loop -- BLOCK cycle seven
+ for FBin in 0 to c_npoints - 1 loop -- BLOCK cycle seven
in_complex.re <= TO_DP_DSP_DATA(FBIN); -- The real part of the X pol counts up
in_complex.im <= TO_DP_DSP_DATA(FBIN); -- The im part of the X pol counts up
wait until rising_edge(dp_clk) and valid_enable = '1';
@@ -246,7 +246,7 @@ begin
wait until rising_edge(dp_clk) and valid_enable = '1';
end loop;
- for FBin IN 0 to c_npoints - 1 loop -- BLOCK cycle eight
+ for FBin in 0 to c_npoints - 1 loop -- BLOCK cycle eight
in_complex.re <= TO_DP_DSP_DATA(-8); -- The real part of the X pol is fixed
in_complex.im <= TO_DP_DSP_DATA(20); -- The im part of the X pol is fixed
wait until rising_edge(dp_clk) and valid_enable = '1';
@@ -255,7 +255,7 @@ begin
wait until rising_edge(dp_clk) and valid_enable = '1';
end loop;
- for FBin IN 0 to c_npoints - 1 loop -- BLOCK cycle nine
+ for FBin in 0 to c_npoints - 1 loop -- BLOCK cycle nine
in_complex.re <= TO_DP_DSP_DATA(2047); -- The real part of the X pol is fixed
in_complex.im <= TO_DP_DSP_DATA(2047); -- The im part of the X pol is fixed
wait until rising_edge(dp_clk) and valid_enable = '1';
diff --git a/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab.vhd b/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab.vhd
index 07d59cef3a1f683238b230fe3d7b4b6a61993508..1d9942e6fe9c1f6e921ade1a70e76f5cc97719c8 100644
--- a/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab.vhd
+++ b/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab.vhd
@@ -145,7 +145,7 @@ begin
for BLOCKCOUNT in 0 to 0 loop -- Repeat as needed
- for FBin IN 0 to c_npoints - 1 loop -- BLOCK cycle one
+ for FBin in 0 to c_npoints - 1 loop -- BLOCK cycle one
in_complex.re <= TO_DP_DSP_DATA(10 * FBIN); -- Set the real part of the X pol
in_complex.im <= TO_DP_DSP_DATA(50 - 10 * FBIN ); -- Set the imag part of the X pol
wait until rising_edge(dp_clk) and valid_enable = '1';
@@ -154,7 +154,7 @@ begin
wait until rising_edge(dp_clk) and valid_enable = '1';
end loop;
- for FBin IN 0 to c_npoints - 1 loop -- BLOCK cycle one
+ for FBin in 0 to c_npoints - 1 loop -- BLOCK cycle one
in_complex.re <= TO_DP_DSP_DATA(2047); -- Set the real part of the X pol
in_complex.im <= TO_DP_DSP_DATA(2047); -- Set the imag part of the X pol
wait until rising_edge(dp_clk) and valid_enable = '1';
diff --git a/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDFPkg.vhd b/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDFPkg.vhd
index fc4fb6443357a7951fb94fe7895046b78a67afb8..2c209ef277d910b0fb4cbb55d2540052ead01c89 100644
--- a/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDFPkg.vhd
+++ b/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDFPkg.vhd
@@ -44,4 +44,4 @@ package rTwoSDFPkg is
end package rTwoSDFPkg;
package body rTwoSDFPkg is
-end rTwoSDFPkg;
+end rTwoSDFPkg;
\ No newline at end of file
diff --git a/libraries/dsp/rTwoSDF/src/vhdl/rTwoWMul.vhd b/libraries/dsp/rTwoSDF/src/vhdl/rTwoWMul.vhd
index d584674743e685497520ca1893ebe8fe4bedeeda..210d9f13087449d9e85c7e7155ceef6e1dfd8b4e 100644
--- a/libraries/dsp/rTwoSDF/src/vhdl/rTwoWMul.vhd
+++ b/libraries/dsp/rTwoSDF/src/vhdl/rTwoWMul.vhd
@@ -30,7 +30,7 @@ entity rTwoWMul is
g_technology : natural := c_tech_select_default;
g_stage : natural := 1;
g_round_even : boolean := true;
- g_lat : natural := 3 +1 -- 3 for mult, 1 for round
+ g_lat : natural := 3 + 1 -- 3 for mult, 1 for round
);
port (
clk : in std_logic;
diff --git a/libraries/dsp/si/tb/vhdl/tb_si.vhd b/libraries/dsp/si/tb/vhdl/tb_si.vhd
index c449cab82d7fa5a1e33c619e0e86fa289e3313ac..4549a1d44eca41b943e66563e2315fe7b34841ff 100755
--- a/libraries/dsp/si/tb/vhdl/tb_si.vhd
+++ b/libraries/dsp/si/tb/vhdl/tb_si.vhd
@@ -248,4 +248,4 @@ begin
cnt_even <= cnt_even + 1 when rising_edge(clk) and clip_even = '1';
cnt_odd <= cnt_odd + 1 when rising_edge(clk) and clip_odd = '1';
-end tb;
+end tb;
\ No newline at end of file
diff --git a/libraries/dsp/st/src/vhdl/mmp_st_histogram.vhd b/libraries/dsp/st/src/vhdl/mmp_st_histogram.vhd
index 3aa8f8aca4803ebce3a9608fcc3ddfe481c513b6..c068434b8fced0f71364bdcb2aad2f9a888a4bf2 100644
--- a/libraries/dsp/st/src/vhdl/mmp_st_histogram.vhd
+++ b/libraries/dsp/st/src/vhdl/mmp_st_histogram.vhd
@@ -225,4 +225,4 @@ begin
miso_arr => ram_cipo_arr
);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/dsp/st/src/vhdl/st_ctrl.vhd b/libraries/dsp/st/src/vhdl/st_ctrl.vhd
index 3e696c077be6754a44ab2b003abd03b595a25228..8a36883841d3b62e1ee1e2398d6d35abfad3682f 100644
--- a/libraries/dsp/st/src/vhdl/st_ctrl.vhd
+++ b/libraries/dsp/st/src/vhdl/st_ctrl.vhd
@@ -77,9 +77,9 @@ architecture rtl of st_ctrl is
constant c_tin_out : natural := c_tot_rd;
constant c_tot_out : natural := c_tin_out + g_dly_out;
- signal dly_val : std_logic_vector(0 TO c_tin_wr);
- signal dly_sync : std_logic_vector(0 TO c_tin_wr);
- signal dly_load : std_logic_vector(c_tin_rd TO c_tin_wr);
+ signal dly_val : std_logic_vector(0 to c_tin_wr);
+ signal dly_sync : std_logic_vector(0 to c_tin_wr);
+ signal dly_load : std_logic_vector(c_tin_rd to c_tin_wr);
signal i_rd_adr : std_logic_vector(rd_adr'range);
signal nxt_rd_adr : std_logic_vector(rd_adr'range);
diff --git a/libraries/dsp/st/src/vhdl/st_histogram.vhd b/libraries/dsp/st/src/vhdl/st_histogram.vhd
index 82676c9eec09506dc677c28c3caed42f47cb8284..437bbb4086b15eda4276b9c6f05b4009985215ef 100644
--- a/libraries/dsp/st/src/vhdl/st_histogram.vhd
+++ b/libraries/dsp/st/src/vhdl/st_histogram.vhd
@@ -211,7 +211,7 @@ begin
-------------------------------------------------------------------------------
-- Select range from snk_in.data and interpret as (un)signed
-------------------------------------------------------------------------------
- gen_unsigned : if g_data_type /="signed " generate
+ gen_unsigned : if g_data_type /="signed " generate
snk_in_data <= snk_in.data(g_data_w - 1 downto c_adr_low);
end generate;
@@ -225,7 +225,7 @@ begin
-- signed two-complement value: -128 -1 0 +127
-- signed offset binary value: -127.5 -0.5 +0.5 +127.5
-- unsigned value: 0 127 128 255
- gen_signed : if g_data_type ="signed " generate
+ gen_signed : if g_data_type ="signed " generate
snk_in_data <= offset_binary(snk_in.data(g_data_w - 1 downto c_adr_low));
end generate;
diff --git a/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd b/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd
index 75a617c9745849e71a19052705311a497076dbee..972f9594239abc7644d773eb80a760bffc791607 100644
--- a/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd
@@ -166,7 +166,7 @@ begin
proc_common_wait_some_cycles(dp_clk, 5);
-- Generate a block of counter data every sync
- if g_stimuli_mode ="counter " then
+ if g_stimuli_mode ="counter " then
for I in 0 to g_nof_sync - 1 loop
v_sosi.sync := '1';
v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_data_w - 1 downto 0)); -- wrap when >= 2**g_data_w
@@ -175,7 +175,7 @@ begin
end if;
-- Generate a DC level that increments every sync
- if g_stimuli_mode ="dc " then
+ if g_stimuli_mode ="dc " then
nxt_stimuli_src_out.valid <= '1';
for I in 0 to g_nof_sync - 1 loop
nxt_stimuli_src_out.data <= INCR_UVEC(stimuli_src_out.data, 1); --all g_nof_data_per_sync cycles
@@ -189,7 +189,7 @@ begin
end if;
-- Generate a sine wave
- if g_stimuli_mode ="sine " then
+ if g_stimuli_mode ="sine " then
nxt_stimuli_src_out <= stimuli_src_out;
nxt_stimuli_src_out.valid <= '1';
stimuli_count <= 0.0;
@@ -206,7 +206,7 @@ begin
end if;
-- Generate pseudo random noise
- if g_stimuli_mode ="random " then
+ if g_stimuli_mode ="random " then
nxt_stimuli_src_out.valid <= '1';
for I in 0 to g_nof_sync - 1 loop
random_data <= (others => '0');
@@ -319,10 +319,10 @@ begin
if i = 0 then -- Sync period 0: we expect RAM to contain zeros
assert histogram_data = 0 report "RAM contains wrong bin count (expected 0, actual " & integer'image(histogram_data) & ")" severity ERROR;
else -- Sync period 1 onwards
- if g_stimuli_mode ="counter " then
+ if g_stimuli_mode ="counter " then
-- Counter data: bin values remain the same every sync
assert histogram_data = c_expected_ram_content_counter report "RAM contains wrong bin count (expected " & integer'image(c_expected_ram_content_counter) & ", actual " & integer'image(histogram_data) & ")" severity ERROR;
- elsif g_stimuli_mode ="dc " then
+ elsif g_stimuli_mode ="dc " then
-- DC data: DC level increments every sync
if j = (i / c_nof_levels_per_bin) then -- Check bin address and account for multiple levels per bin
-- this address (j) should contain the DC level total count of this sync period (i)
diff --git a/libraries/dsp/verify_pfb/tb_verify_pfb_response.vhd b/libraries/dsp/verify_pfb/tb_verify_pfb_response.vhd
index 79d6a82607c0511f8404ac756040da65fc0e8147..94d403e1fa917afbb1da6af8846947388f8eb7f2 100644
--- a/libraries/dsp/verify_pfb/tb_verify_pfb_response.vhd
+++ b/libraries/dsp/verify_pfb/tb_verify_pfb_response.vhd
@@ -310,7 +310,7 @@ begin
-- Read and verify FIR coefficients (similar as in tb_fil_ppf_single.vhd)
---------------------------------------------------------------
- gen_mm_wpfb : if g_sel_pfb ="WPFB " generate
+ gen_mm_wpfb : if g_sel_pfb ="WPFB " generate
p_get_coefs_ref : process
begin
-- Read all coeffs from coefs file
@@ -319,7 +319,7 @@ begin
-- Reverse the coeffs per tap
for J in 0 to c_N_taps - 1 loop
for I in 0 to c_N_fft - 1 loop
- flip_coefs_arr(J * c_N_fft + c_N_fft - 1 -I) <= ref_coefs_arr(J*c_N_fft + I);
+ flip_coefs_arr(J * c_N_fft + c_N_fft - 1 - I) <= ref_coefs_arr(J * c_N_fft + I);
end loop;
end loop;
wait;
@@ -358,7 +358,7 @@ begin
in_sosi_arr(0) <= in_sosi;
-- DUT = APERTIF WFPB
- dut_wpfb_unit_dev : if g_sel_pfb ="WPFB " generate
+ dut_wpfb_unit_dev : if g_sel_pfb ="WPFB " generate
u_wpfb_unit_dev : entity wpfb_lib.wpfb_unit_dev
generic map (
g_wpfb => c_wpfb,
@@ -379,7 +379,7 @@ begin
end generate;
-- DUT = LOFAR1 WFPB
- dut_pfb2_unit : if g_sel_pfb ="PFB2 " generate
+ dut_pfb2_unit : if g_sel_pfb ="PFB2 " generate
u_pfb2_unit : entity pfb2_lib.pfb2_unit
generic map (
g_nof_streams => 1, -- number of pfb2 instances, 1 pfb2 per stream
diff --git a/libraries/dsp/verify_pfb/tb_verify_pfb_wg.vhd b/libraries/dsp/verify_pfb/tb_verify_pfb_wg.vhd
index 948cb783886644c47d1a96dfefbec0c7d3499232..071a5dc316d6b05f4cbcd627ddcb0425db6d2f49 100644
--- a/libraries/dsp/verify_pfb/tb_verify_pfb_wg.vhd
+++ b/libraries/dsp/verify_pfb/tb_verify_pfb_wg.vhd
@@ -176,21 +176,21 @@ architecture tb of tb_verify_pfb_wg is
constant c_pfs_lofar1 : boolean := g_fil_coefs_file_prefix = "data/Coeffs16384Kaiser-quant_1wb";
-- Determine PFIR coefficient width for WPFB and PFB2
- constant c_pfir_coef_w : natural := sel_a_b(g_sel_pfb ="WPFB ", g_fil_coef_dat_w, 16);
+ constant c_pfir_coef_w : natural := sel_a_b(g_sel_pfb ="WPFB ", g_fil_coef_dat_w, 16);
constant c_pfir_coefs_file : string := c_pfs_coefs_file; -- PFB2 "data/pfs_coefsbuf_1024.hex" default from pfs_pkg.vhd
-- Determine internal data width between PFIR and PFT for WPFB and PFB2, use default if g_internal_dat_w=0
- constant c_internal_dat_w : natural := sel_a_b(g_sel_pfb ="WPFB ",
+ constant c_internal_dat_w : natural := sel_a_b(g_sel_pfb ="WPFB ",
sel_a_b(g_internal_dat_w >0, g_internal_dat_w, g_fft_stage_dat_w - g_fft_guard_w),
sel_a_b(g_internal_dat_w >0, g_internal_dat_w, g_fft_stage_dat_w));
-- Determine two real input decorrelation logic option, only supported in PFB2
- constant c_switch_en : std_logic := sel_a_b(g_sel_pfb ="WPFB ", '0', g_switch_en);
+ constant c_switch_en : std_logic := sel_a_b(g_sel_pfb ="WPFB ", '0', g_switch_en);
-- Determine FFT twiddle factors info
constant c_fft_twiddle : wTyp := (others => '0');
constant c_fft_twiddle_w : natural := c_fft_twiddle'length; -- from rTwoSDF twiddlesPkg.vhd
- constant c_twiddle_w : natural := sel_a_b(g_sel_pfb ="WPFB ", c_fft_twiddle_w, c_pft_twiddle_w);
+ constant c_twiddle_w : natural := sel_a_b(g_sel_pfb ="WPFB ", c_fft_twiddle_w, c_pft_twiddle_w);
-- WPFB
-- type t_wpfb is record
@@ -910,8 +910,8 @@ begin
-- Convert SST to unsigned REAL per signal path (SP) and normalize for integration interval of c_N_blk
for SUB in 0 to c_N_sub - 1 loop
- sp_subband_powers_a(SUB) <= to_ureal(sp_subband_powers_arr2(0)(SUB)) / REAL(c_N_blk);
- sp_subband_powers_b(SUB) <= to_ureal(sp_subband_powers_arr2(1)(SUB)) / REAL(c_N_blk);
+ sp_subband_powers_a(SUB) <= to_ureal(sp_subband_powers_arr2(0)(SUB)) / real(c_N_blk);
+ sp_subband_powers_b(SUB) <= to_ureal(sp_subband_powers_arr2(1)(SUB)) / real(c_N_blk);
end loop;
proc_common_wait_some_cycles(dp_clk, 1);
@@ -970,7 +970,7 @@ begin
-- Report
---------------------------------------------------------------------------
proc_common_wait_some_cycles(dp_clk, g_tb_index); -- use g_tb_index to identify and separate logging in case of multiple tb instances finishing in parallel
- if g_sel_pfb ="WPFB " then
+ if g_sel_pfb ="WPFB " then
print_str("-------------------------------------------------------------");
print_str("-- WPFB settings of tb-" & int_to_str(g_tb_index) & ":");
print_str("-------------------------------------------------------------");
@@ -987,7 +987,7 @@ begin
print_str(". g_fft_guard_w = " & int_to_str(g_fft_guard_w));
print_str(". c_switch_en = " & slv_to_str(slv(c_switch_en)));
end if;
- if g_sel_pfb ="PFB2 " then
+ if g_sel_pfb ="PFB2 " then
print_str("-------------------------------------------------------------");
print_str("-- PFB2 settings of tb-" & int_to_str(g_tb_index) & ":");
print_str("-------------------------------------------------------------");
@@ -1120,7 +1120,7 @@ begin
in_sosi_arr(0) <= in_sosi;
-- DUT = APERTIF WFPB
- dut_wpfb_unit_dev : if g_sel_pfb ="WPFB " generate
+ dut_wpfb_unit_dev : if g_sel_pfb ="WPFB " generate
u_wpfb_unit_dev : entity wpfb_lib.wpfb_unit_dev
generic map (
g_wpfb => c_wpfb,
@@ -1143,7 +1143,7 @@ begin
end generate;
-- DUT = LOFAR1 WFPB
- dut_pfb2_unit : if g_sel_pfb ="PFB2 " generate
+ dut_pfb2_unit : if g_sel_pfb ="PFB2 " generate
u_pfb2_unit : entity pfb2_lib.pfb2_unit
generic map (
g_nof_streams => 1, -- number of pfb2 instances, 1 pfb2 per stream
diff --git a/libraries/dsp/wpfb/src/vhdl/wpfb_pkg.vhd b/libraries/dsp/wpfb/src/vhdl/wpfb_pkg.vhd
index 49fb7bc2b3d57e778b4f11ac8d1208c1b6c2041f..67f7cd6aff46353407a732eb1f1152cacf27df00 100644
--- a/libraries/dsp/wpfb/src/vhdl/wpfb_pkg.vhd
+++ b/libraries/dsp/wpfb/src/vhdl/wpfb_pkg.vhd
@@ -355,4 +355,4 @@ package body wpfb_pkg is
return v_wpfb;
end func_wpfb_set_nof_block_per_sync;
-end wpfb_pkg;
+end wpfb_pkg;
\ No newline at end of file
diff --git a/libraries/dsp/wpfb/src/vhdl/wpfb_unit.vhd b/libraries/dsp/wpfb/src/vhdl/wpfb_unit.vhd
index 4c61c0040881c91c8ad404292199ba9167dd59c5..5cc1b916e88708cff9681e555a0fa732920d8444 100644
--- a/libraries/dsp/wpfb/src/vhdl/wpfb_unit.vhd
+++ b/libraries/dsp/wpfb/src/vhdl/wpfb_unit.vhd
@@ -396,6 +396,4 @@ begin
end generate;
end generate;
-end str;
-
-
+end str;
\ No newline at end of file
diff --git a/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd b/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd
index 4ba6cc75599ec552fe5ec139566cc673aa373489..0d1051bb29dbfd4b8429d807cb5b6d79233d95e4 100644
--- a/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd
+++ b/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd
@@ -725,6 +725,4 @@ begin
-- Connect to the outside world
out_quant_sosi_arr <= pfb_out_quant_sosi_arr;
-end str;
-
-
+end str;
\ No newline at end of file
diff --git a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd
index fe6e37a5bc2246cc3470a4a64669fb8817425044..a30300342cbbea617e464c6b55f66dd9bd9e8bb5 100644
--- a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd
+++ b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd
@@ -381,7 +381,7 @@ begin
for S in 0 to g_wpfb.nof_wb_streams - 1 loop -- parallel
for P in 0 to g_wpfb.wb_factor - 1 loop -- parallel
if c_big_endian_wb_in = TRUE then
- vP := g_wpfb.wb_factor - 1 -P; -- time to big endian
+ vP := g_wpfb.wb_factor - 1 - P; -- time to big endian
else
vP := P; -- time in little endian
end if;
diff --git a/libraries/io/aduh/src/vhdl/aduh_quad.vhd b/libraries/io/aduh/src/vhdl/aduh_quad.vhd
index c5ca9d380cdc1b02d76271dbbac16f81ff4a32ef..4dd3d2376933c80aab257e3ab4a73c415a16e23c 100644
--- a/libraries/io/aduh/src/vhdl/aduh_quad.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_quad.vhd
@@ -72,8 +72,8 @@ entity aduh_quad is
aduh_cd_control : in std_logic_vector(c_word_w - 1 downto 0);
aduh_verify_res : out t_slv_32_arr(0 to g_ai.nof_sp - 1); -- [8,7:0]
- aduh_verify_res_val : out std_logic_vector(0 TO g_ai.nof_sp - 1);
- aduh_verify_res_ack : in std_logic_vector(0 TO g_ai.nof_sp - 1)
+ aduh_verify_res_val : out std_logic_vector(0 to g_ai.nof_sp - 1);
+ aduh_verify_res_ack : in std_logic_vector(0 to g_ai.nof_sp - 1)
);
end aduh_quad;
diff --git a/libraries/io/aduh/src/vhdl/aduh_quad_reg.vhd b/libraries/io/aduh/src/vhdl/aduh_quad_reg.vhd
index 67f3ebd32154d24578f88dbbca89428b1d45973e..fb9cc40b48684f9f4c7e45954c9e9cc44ed39636 100644
--- a/libraries/io/aduh/src/vhdl/aduh_quad_reg.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_quad_reg.vhd
@@ -535,4 +535,4 @@ begin
);
end generate; -- gen_cross
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/io/aduh/src/vhdl/aduh_verify.vhd b/libraries/io/aduh/src/vhdl/aduh_verify.vhd
index 3641744826630555bce561a05a7f60705024df08..ed8d6e5f5c4f9056bdebe52bdae31b6cdbcd8ee2 100644
--- a/libraries/io/aduh/src/vhdl/aduh_verify.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_verify.vhd
@@ -121,17 +121,17 @@ architecture rtl of aduh_verify is
constant c_tp_symbol : t_slv_8_arr(0 to 1) := (x"02", x"01"); -- = (I, Q), use patter_sel to select
- type t_nibble_arr is array (integer range <> ) of std_logic_vector(0 TO g_nof_symbols_per_data - 1); -- here use index [0:3] for the big endian nibbles
+ type t_nibble_arr is array (integer range <> ) of std_logic_vector(0 to g_nof_symbols_per_data - 1); -- here use index [0:3] for the big endian nibbles
signal symbols : t_slv_8_arr(0 to g_nof_symbols_per_data - 1);
- signal symb : std_logic_vector(0 TO g_nof_symbols_per_data - 1); -- here use index [0:3] for the big endian nibbles
- signal symb_err : std_logic_vector(0 TO g_nof_symbols_per_data - 1);
+ signal symb : std_logic_vector(0 to g_nof_symbols_per_data - 1); -- here use index [0:3] for the big endian nibbles
+ signal symb_err : std_logic_vector(0 to g_nof_symbols_per_data - 1);
signal bits : t_nibble_arr(g_symbol_w - 1 downto 0);
signal in_val : std_logic;
signal nxt_in_val : std_logic;
- signal in_symb : std_logic_vector(0 TO g_nof_symbols_per_data - 1); -- here use index [0:3] for the big endian nibbles
- signal nxt_in_symb : std_logic_vector(0 TO g_nof_symbols_per_data - 1);
+ signal in_symb : std_logic_vector(0 to g_nof_symbols_per_data - 1); -- here use index [0:3] for the big endian nibbles
+ signal nxt_in_symb : std_logic_vector(0 to g_nof_symbols_per_data - 1);
signal in_symb_err : std_logic;
signal nxt_in_symb_err : std_logic;
signal in_bits : t_nibble_arr(g_symbol_w - 1 downto 0);
diff --git a/libraries/io/aduh/src/vhdl/aduh_verify_bit.vhd b/libraries/io/aduh/src/vhdl/aduh_verify_bit.vhd
index 221420f3ea2e17c39832659c1885fe9bcdae067e..b3e0e3cf689a971618539bb759bad565364d3b6e 100644
--- a/libraries/io/aduh/src/vhdl/aduh_verify_bit.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_verify_bit.vhd
@@ -40,7 +40,7 @@ entity aduh_verify_bit is
-- ST input
in_val : in std_logic;
- in_dat : in std_logic_vector(0 TO g_nof_symbols_per_data - 1);
+ in_dat : in std_logic_vector(0 to g_nof_symbols_per_data - 1);
in_dat_err : in std_logic := '0';
-- Static control input (connect via MM or leave open to use default)
@@ -74,10 +74,10 @@ architecture rtl of aduh_verify_bit is
return to_uvec(0, g_nof_symbols_per_data); -- else return invalid value
end;
- signal ref_dat : std_logic_vector(0 TO g_nof_symbols_per_data - 1);
- signal nxt_ref_dat : std_logic_vector(0 TO g_nof_symbols_per_data - 1);
- signal prev_ref_dat : std_logic_vector(0 TO g_nof_symbols_per_data - 1);
- signal nxt_prev_ref_dat : std_logic_vector(0 TO g_nof_symbols_per_data - 1);
+ signal ref_dat : std_logic_vector(0 to g_nof_symbols_per_data - 1);
+ signal nxt_ref_dat : std_logic_vector(0 to g_nof_symbols_per_data - 1);
+ signal prev_ref_dat : std_logic_vector(0 to g_nof_symbols_per_data - 1);
+ signal nxt_prev_ref_dat : std_logic_vector(0 to g_nof_symbols_per_data - 1);
signal state : t_state;
signal nxt_state : t_state;
diff --git a/libraries/io/aduh/src/vhdl/lvdsh_dd_phs4_align.vhd b/libraries/io/aduh/src/vhdl/lvdsh_dd_phs4_align.vhd
index dc0c3252259728d950221ee295865bb839435ad8..c3ccd643abc4b1067bd6b15d5900a606ead5269a 100644
--- a/libraries/io/aduh/src/vhdl/lvdsh_dd_phs4_align.vhd
+++ b/libraries/io/aduh/src/vhdl/lvdsh_dd_phs4_align.vhd
@@ -358,7 +358,7 @@ begin
-- Declare dd_phs_locked when dd_sync=0 to ensure the dd_sync will be detected when it is becoming 1 again.
nxt_r.dd_phs_locked <= '0' when dd_phs_detected_ok = '0' else
- '1' when dd_phs_detected_ok = '1' and r.dd_sync ="0000 " else r.dd_phs_locked;
+ '1' when dd_phs_detected_ok = '1' and r.dd_sync ="0000 " else r.dd_phs_locked;
------------------------------------------------------------------------------
diff --git a/libraries/io/aduh/src/vhdl/lvdsh_dd_wb4.vhd b/libraries/io/aduh/src/vhdl/lvdsh_dd_wb4.vhd
index 63e3b4671b66e95b23bd21495cc4c5bdcd64d8a5..1d4e2eb1493d1bf2a78611d35d0cec913971071b 100644
--- a/libraries/io/aduh/src/vhdl/lvdsh_dd_wb4.vhd
+++ b/libraries/io/aduh/src/vhdl/lvdsh_dd_wb4.vhd
@@ -380,12 +380,12 @@ begin
-- Set phase based on where the valid be_sync "1111" is detected in two cycles
-- Signal illegal be_sync combinations that can occur if the in_clk and dp_clk edges are too close
nxt_r.sync_phase <= r.sync_phase;
- if r.be_sync ="1111 " and be_sync ="0000 " then nxt_r.sync_phase <= 0; end if; -- F0
- if r.be_sync ="0111 " and be_sync ="1000 " then nxt_r.sync_phase <= 1; end if; -- 78
- if r.be_sync ="0011 " and be_sync ="1100 " then nxt_r.sync_phase <= 2; end if; -- 3C
- if r.be_sync ="0001 " and be_sync ="1110 " then nxt_r.sync_phase <= 3; end if; -- 1E
- if r.be_sync ="1011 " and be_sync ="0100 " then nxt_r.sync_phase <= 5; end if; -- B4 = swap hi lo of 78, so map to phase 4+1=5
- if r.be_sync ="0010 " and be_sync ="1101 " then nxt_r.sync_phase <= 7; end if; -- 2D = swap hi lo of 1E, so map to phase 4+3=7
+ if r.be_sync ="1111 " and be_sync ="0000 " then nxt_r.sync_phase <= 0; end if; -- F0
+ if r.be_sync ="0111 " and be_sync ="1000 " then nxt_r.sync_phase <= 1; end if; -- 78
+ if r.be_sync ="0011 " and be_sync ="1100 " then nxt_r.sync_phase <= 2; end if; -- 3C
+ if r.be_sync ="0001 " and be_sync ="1110 " then nxt_r.sync_phase <= 3; end if; -- 1E
+ if r.be_sync ="1011 " and be_sync ="0100 " then nxt_r.sync_phase <= 5; end if; -- B4 = swap hi lo of 78, so map to phase 4+1=5
+ if r.be_sync ="0010 " and be_sync ="1101 " then nxt_r.sync_phase <= 7; end if; -- 2D = swap hi lo of 1E, so map to phase 4+3=7
-- F0 = swap hi lo of F0, so phase 4 cannot be distinghuised from phase 0
-- 3C = swap hi lo of 3C, so phase 6 cannot be distinghuised from phase 2
-- Map sync_phase 0:3 and 5:7 on dat_phase 0:3
@@ -402,10 +402,10 @@ begin
nxt_r.status <= r.status;
nxt_r.status(7 downto 4) <= to_uvec(r.sync_phase, 4);
nxt_r.status(7 downto 4) <= "000" & dd_phase;
- if r.be_sync ="1111 " or (r.be_sync /="0000 " and be_sync /="0000 ") then
+ if r.be_sync ="1111 " or (r.be_sync /="0000 " and be_sync /="0000 ") then
nxt_r.status(15 downto 8) <= r.be_sync & be_sync;
end if;
- if be_sync /="0000 " then
+ if be_sync /="0000 " then
nxt_r.status(23 downto 16) <= r.be_sync & be_sync;
elsif unsigned(wb_cnt) > c_wb_sync_latency then
nxt_r.status(23 downto 16) <= (others => '0');
diff --git a/libraries/io/aduh/src/vhdl/mms_aduh_quad.vhd b/libraries/io/aduh/src/vhdl/mms_aduh_quad.vhd
index 63606ba2e5eba4c54af77e34d23b14d081ebb99b..0ccc55cacc9b8e4a45b167da888a09233781bbe2 100644
--- a/libraries/io/aduh/src/vhdl/mms_aduh_quad.vhd
+++ b/libraries/io/aduh/src/vhdl/mms_aduh_quad.vhd
@@ -86,8 +86,8 @@ architecture str of mms_aduh_quad is
signal aduh_cd_control : std_logic_vector(c_word_w - 1 downto 0);
signal aduh_verify_res : t_slv_32_arr(0 to g_ai.nof_sp - 1); -- [8,7:0]
- signal aduh_verify_res_val : std_logic_vector(0 TO g_ai.nof_sp - 1);
- signal aduh_verify_res_ack : std_logic_vector(0 TO g_ai.nof_sp - 1);
+ signal aduh_verify_res_val : std_logic_vector(0 to g_ai.nof_sp - 1);
+ signal aduh_verify_res_ack : std_logic_vector(0 to g_ai.nof_sp - 1);
begin
diff --git a/libraries/io/aduh/tb/vhdl/tb_aduh_dd.vhd b/libraries/io/aduh/tb/vhdl/tb_aduh_dd.vhd
index a0d4185fc261fe5bd8527f3bbc7fbccd7c461514..fe52134bd28049748eda4f317a7d7d728eb63d9a 100644
--- a/libraries/io/aduh/tb/vhdl/tb_aduh_dd.vhd
+++ b/libraries/io/aduh/tb/vhdl/tb_aduh_dd.vhd
@@ -126,10 +126,10 @@ architecture tb of tb_aduh_dd is
signal cd_stable_ack : std_logic := '0';
-- Verify
- signal verify_en : std_logic_vector(0 TO c_ai.nof_sp - 1) := (others => '0');
+ signal verify_en : std_logic_vector(0 to c_ai.nof_sp - 1) := (others => '0');
signal verify_en_all : std_logic := '0';
- signal verify_valid : std_logic_vector(0 TO c_ai.nof_sp - 1) := (others => '0');
- signal verify_done : std_logic_vector(0 TO c_ai.nof_sp - 1) := (others => '0');
+ signal verify_valid : std_logic_vector(0 to c_ai.nof_sp - 1) := (others => '0');
+ signal verify_done : std_logic_vector(0 to c_ai.nof_sp - 1) := (others => '0');
signal verify_data : t_dp_data_arr( 0 to c_ai.nof_sp - 1);
signal prev_verify_data : t_dp_data_arr( 0 to c_ai.nof_sp - 1);
signal sl0 : std_logic := '0';
diff --git a/libraries/io/aduh/tb/vhdl/tb_aduh_pll.vhd b/libraries/io/aduh/tb/vhdl/tb_aduh_pll.vhd
index c881f4076037541786b9fced0a388c67e1f8759c..848c29e9a04b6307b183005bd485dd3d4f2d78ca 100644
--- a/libraries/io/aduh/tb/vhdl/tb_aduh_pll.vhd
+++ b/libraries/io/aduh/tb/vhdl/tb_aduh_pll.vhd
@@ -154,9 +154,9 @@ architecture tb of tb_aduh_pll is
-- Verify
signal restart_any : std_logic := '0';
- signal verify_valid : std_logic_vector(0 TO c_ai.nof_sp - 1) := (others => '0');
- signal verify_restart : std_logic_vector(0 TO c_ai.nof_sp - 1) := (others => '0');
- signal verify_en : std_logic_vector(0 TO c_ai.nof_sp - 1) := (others => '0');
+ signal verify_valid : std_logic_vector(0 to c_ai.nof_sp - 1) := (others => '0');
+ signal verify_restart : std_logic_vector(0 to c_ai.nof_sp - 1) := (others => '0');
+ signal verify_en : std_logic_vector(0 to c_ai.nof_sp - 1) := (others => '0');
signal verify_en_all : std_logic := '0';
signal verify_data : t_dp_data_arr( 0 to c_ai.nof_sp - 1);
signal prev_verify_data : t_dp_data_arr( 0 to c_ai.nof_sp - 1);
diff --git a/libraries/io/ddr/src/vhdl/io_ddr.vhd b/libraries/io/ddr/src/vhdl/io_ddr.vhd
index db328735375285fcdf3556fd91d8e1e81849260a..2f496b018f2c7f60ebb193e4a25c6ee3233e65da 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr.vhd
@@ -230,8 +230,8 @@ end io_ddr;
architecture str of io_ddr is
- constant c_wr_use_sync : boolean := sel_a_b(g_wr_flush_mode ="SYN ", TRUE, FALSE);
- constant c_wr_use_ctrl : boolean := sel_a_b(g_wr_flush_mode ="SOP ", TRUE, FALSE);
+ constant c_wr_use_sync : boolean := sel_a_b(g_wr_flush_mode ="SYN ", TRUE, FALSE);
+ constant c_wr_use_ctrl : boolean := sel_a_b(g_wr_flush_mode ="SOP ", TRUE, FALSE);
constant c_wr_fifo_use_ctrl : boolean := c_wr_use_sync or c_wr_use_ctrl;
constant c_ddr_gigabytes : natural := func_tech_ddr_module_size(g_tech_ddr); -- units GiByte
@@ -243,7 +243,7 @@ architecture str of io_ddr is
constant c_wr_fifo_af_margin : natural := 8 + 1; -- use 8 (>= 4 default) to be safe and use +1 to compensate for latency introduced by registering wr_siso.ready due to RL=0
- constant c_nof_rd_bursts_max : natural := sel_a_b(g_tech_ddr.name ="DDR3 ", 1, 3); -- max number of rd bursts in queue, derived empirically from simulation, seems fixed 1 for DDR3 and seems to match (g_tech_ddr.command_queue_depth-1)/2 for DDR4
+ constant c_nof_rd_bursts_max : natural := sel_a_b(g_tech_ddr.name ="DDR3 ", 1, 3); -- max number of rd bursts in queue, derived empirically from simulation, seems fixed 1 for DDR3 and seems to match (g_tech_ddr.command_queue_depth-1)/2 for DDR4
constant c_rd_fifo_af_margin : natural := 8 + c_nof_rd_bursts_max * g_tech_ddr.maxburstsize; -- use 8 (>= 4 default) to be safe and use sufficient extra margin to fit one or more rd burst accesses of g_tech_ddr.maxburstsize each
constant c_mem_reg_adr_w : natural := 2;
@@ -555,4 +555,4 @@ begin
out_reg => open
);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/io/ddr/src/vhdl/io_ddr_driver.vhd b/libraries/io/ddr/src/vhdl/io_ddr_driver.vhd
index 94d7f2e12fe736bfa014f5b6e05088439b445f74..4b0840668a55fcb48934b3193f34d424856b72b9 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr_driver.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr_driver.vhd
@@ -276,4 +276,4 @@ begin
end case;
end process;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/io/ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd b/libraries/io/ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd
index c85ac22bc13e0ea55808e8481eac9c9435a681b0..3ff6b47ab65fbb23810e767f224dcf26df98c3e3 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd
@@ -85,17 +85,17 @@ begin
-- Flush disable control
no_channel : if g_use_channel = FALSE generate
- gen_valid : if g_mode ="VAL " generate flush_dis <= ctlr_wr_sosi.valid; end generate;
- gen_sop : if g_mode ="SOP " generate flush_dis <= ctlr_wr_sosi.sop ; end generate;
- gen_sync : if g_mode ="SYN " generate flush_dis <= ctlr_wr_sosi.sync ; end generate;
+ gen_valid : if g_mode ="VAL " generate flush_dis <= ctlr_wr_sosi.valid; end generate;
+ gen_sop : if g_mode ="SOP " generate flush_dis <= ctlr_wr_sosi.sop ; end generate;
+ gen_sync : if g_mode ="SYN " generate flush_dis <= ctlr_wr_sosi.sync ; end generate;
end generate;
use_channel : if g_use_channel = TRUE generate
channel <= to_uint(ctlr_wr_sosi.channel(c_channel_w - 1 downto 0));
- gen_valid : if g_mode ="VAL " generate flush_dis <= '1' when ctlr_wr_sosi.valid = '1' and channel = g_start_channel else '0'; end generate;
- gen_sop : if g_mode ="SOP " generate flush_dis <= '1' when ctlr_wr_sosi.sop = '1' and channel = g_start_channel else '0'; end generate;
- gen_sync : if g_mode ="SYN " generate flush_dis <= '1' when ctlr_wr_sosi.sync = '1' and channel = g_start_channel else '0'; end generate;
+ gen_valid : if g_mode ="VAL " generate flush_dis <= '1' when ctlr_wr_sosi.valid = '1' and channel = g_start_channel else '0'; end generate;
+ gen_sop : if g_mode ="SOP " generate flush_dis <= '1' when ctlr_wr_sosi.sop = '1' and channel = g_start_channel else '0'; end generate;
+ gen_sync : if g_mode ="SYN " generate flush_dis <= '1' when ctlr_wr_sosi.sync = '1' and channel = g_start_channel else '0'; end generate;
end generate;
p_reg : process(rst, clk)
@@ -136,4 +136,4 @@ begin
end case;
end process;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/io/ddr/src/vhdl/io_ddr_reg.vhd b/libraries/io/ddr/src/vhdl/io_ddr_reg.vhd
index c7e1a284f8900beef20a55254223c4e82bfa22e3..4f7baedefde5674b6dbcc39c0154cea7992e987b 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr_reg.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr_reg.vhd
@@ -141,4 +141,4 @@ begin
end if;
end process;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/io/ddr/src/vhdl/mms_io_ddr.vhd b/libraries/io/ddr/src/vhdl/mms_io_ddr.vhd
index 4037d66200ae88347af02fc3d7b16dcbc4a7b2d6..182da5fa0ba8960d8ecb2feb1b136b5092c06866 100644
--- a/libraries/io/ddr/src/vhdl/mms_io_ddr.vhd
+++ b/libraries/io/ddr/src/vhdl/mms_io_ddr.vhd
@@ -205,4 +205,4 @@ begin
dvr_mosi => mm_dvr_mosi
);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd b/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
index 18a27d9b48ef9b24e9d8ac2930bfaa2cd6f57697..ad21d96cd9032f861c576c5f741e67e0813d052e 100644
--- a/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
+++ b/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
@@ -77,7 +77,7 @@ architecture str of tb_io_ddr is
constant c_dp_clk_period : time := 5 ns; -- 200 MHz
constant c_mm_clk_period : time := 8 ns; -- 125 MHz
- constant c_ctlr_ref_clk_period : time := sel_a_b(g_sim_model, c_dp_clk_period, sel_a_b(c_tech_ddr.name ="DDR3 ", 5 ns, 40 ns)); -- 200 MHz for DDR3 on UniBoard and 25 MHz for DDR4 on UniBoard2, use dp clock for sim_model
+ constant c_ctlr_ref_clk_period : time := sel_a_b(g_sim_model, c_dp_clk_period, sel_a_b(c_tech_ddr.name ="DDR3 ", 5 ns, 40 ns)); -- 200 MHz for DDR3 on UniBoard and 25 MHz for DDR4 on UniBoard2, use dp clock for sim_model
constant c_ctlr_clk_freq : natural := c_tech_ddr.mts / c_tech_ddr.rsl; -- 200 MHz
constant c_ctlr_clk_period : time := (1000000 / c_ctlr_clk_freq) * 1 ps; -- 5000 ps
constant c_cross_domain_dvr_ctlr : boolean := g_cross_domain_dvr_ctlr or g_dvr_clk_period /= c_ctlr_clk_period;
@@ -142,7 +142,7 @@ architecture str of tb_io_ddr is
end;
function func_ctlr_wr_not_rd_arr return std_logic_vector is
- variable v_arr : std_logic_vector(0 TO c_nof_access - 1);
+ variable v_arr : std_logic_vector(0 to c_nof_access - 1);
begin
for R in 0 to g_nof_block - 1 loop
-- Write block in g_nof_wr_per_block accesses
@@ -159,11 +159,11 @@ architecture str of tb_io_ddr is
constant c_ctlr_address_lo_arr : t_nat_natural_arr(0 to c_nof_access - 1) := func_ctlr_address_lo_arr;
constant c_ctlr_nof_address_arr : t_nat_natural_arr(0 to c_nof_access - 1) := func_ctlr_nof_address_arr;
- constant c_ctlr_wr_not_rd_arr : std_logic_vector(0 TO c_nof_access - 1) := func_ctlr_wr_not_rd_arr;
+ constant c_ctlr_wr_not_rd_arr : std_logic_vector(0 to c_nof_access - 1) := func_ctlr_wr_not_rd_arr;
signal dbg_c_ctlr_address_lo_arr : t_nat_natural_arr(0 to c_nof_access - 1) := c_ctlr_address_lo_arr;
signal dbg_c_ctlr_nof_address_arr : t_nat_natural_arr(0 to c_nof_access - 1) := c_ctlr_nof_address_arr;
- signal dbg_c_ctlr_wr_not_rd_arr : std_logic_vector(0 TO c_nof_access - 1) := c_ctlr_wr_not_rd_arr;
+ signal dbg_c_ctlr_wr_not_rd_arr : std_logic_vector(0 to c_nof_access - 1) := c_ctlr_wr_not_rd_arr;
signal dbg_c_tech_ddr : t_c_tech_ddr := c_tech_ddr;
signal dbg_c_exp_gigabytes : natural := c_exp_gigabytes; -- = 0 for sim model, else nof GB
@@ -407,7 +407,7 @@ begin
-- Default, fits g_wr_flush_mode="VAL"
wr_src_out <= diag_wr_src_out;
- if g_wr_flush_mode ="SOP " then
+ if g_wr_flush_mode ="SOP " then
wr_src_out.sop <= '0';
wr_src_out.eop <= '0';
if wr_val_cnt mod c_wr_frame_size = 0 then
@@ -417,7 +417,7 @@ begin
end if;
end if;
- if g_wr_flush_mode ="SYN " then
+ if g_wr_flush_mode ="SYN " then
wr_src_out.sync <= '0';
if wr_val_cnt mod c_wr_sync_period = 0 then
wr_src_out.sync <= diag_wr_src_out.valid;
@@ -517,5 +517,4 @@ begin
mem4_io => phy4_io
);
-end architecture str;
-
+end architecture str;
\ No newline at end of file
diff --git a/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd b/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
index 9b3e45243c2ea603d8d7fdb97ff8d6176eb1194a..fd26490118777837ab79494408ccc4832d68567f 100644
--- a/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
+++ b/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
@@ -70,7 +70,7 @@ begin
u_sim_model : entity work.tb_io_ddr generic map ( TRUE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 4, 2500, 2, 1, 1, 1, "VAL") port map (tb_end_vec(0));
- gen_ddr3 : if c_tech_ddr.name ="DDR3 " generate
+ gen_ddr3 : if c_tech_ddr.name ="DDR3 " generate
u_default : entity work.tb_io_ddr generic map (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 4, 2500, 2, 1, 1, 1, "VAL") port map (tb_end_vec(1));
u_fill_wrfifo_on_next_valid : entity work.tb_io_ddr generic map (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 1, 1000, 2, 1, 4, 2, "VAL") port map (tb_end_vec(2));
@@ -91,7 +91,7 @@ begin
end generate;
-- Distinghuis between tests for DDR3 and DDR4, because the Quartus 14.1 ip_arria10 DDR4 model simulates about 40x slower than the Quartus 11.1 ip_stratixiv DDR3 uniphy model.
- gen_ddr4 : if c_tech_ddr.name ="DDR4 " generate
+ gen_ddr4 : if c_tech_ddr.name ="DDR4 " generate
u_default : entity work.tb_io_ddr generic map (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 4, 2500, 2, 1, 1, 1, "VAL") port map (tb_end_vec(1));
end generate;
diff --git a/libraries/io/ddr3/src/vhdl/ddr3.vhd b/libraries/io/ddr3/src/vhdl/ddr3.vhd
index 11143724e51f82849803ad2c5f27ca0170ac8d69..84bbd0364cde65436009c195f344a85db11d0c36 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3.vhd
@@ -373,4 +373,4 @@ begin
phy3_ou => phy_ou
);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/io/ddr3/src/vhdl/ddr3_driver.vhd b/libraries/io/ddr3/src/vhdl/ddr3_driver.vhd
index bfc23caa8131609a4a5e12fd7c856d4c54eb1325..1e2af73d4802ce453617f3da37c8058be7cacf3a 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3_driver.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3_driver.vhd
@@ -272,4 +272,4 @@ begin
cur_addr.row( g_ddr.a_w - 1 downto 0) <= cur_address( g_ddr.a_w + g_ddr.a_col_w - 1 downto g_ddr.a_col_w);
cur_addr.column(g_ddr.a_col_w - 1 downto 0) <= cur_address( g_ddr.a_col_w - 1 downto 0);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/io/ddr3/src/vhdl/ddr3_flush_ctrl.vhd b/libraries/io/ddr3/src/vhdl/ddr3_flush_ctrl.vhd
index bdeec8367c8a4574f915ad844559c193b906d880..644a9e428139d4f669f295c09eda7313a038dc43 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3_flush_ctrl.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3_flush_ctrl.vhd
@@ -151,4 +151,4 @@ begin
end case;
end process;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd b/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
index dff72c51a7d46fb253be7d551f498a19756844ef..6802cc8fce157e54a5a48a57221e42f3668062e5 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
@@ -276,4 +276,4 @@ end ddr3_pkg;
package body ddr3_pkg is
-end ddr3_pkg;
+end ddr3_pkg;
\ No newline at end of file
diff --git a/libraries/io/ddr3/src/vhdl/ddr3_reg.vhd b/libraries/io/ddr3/src/vhdl/ddr3_reg.vhd
index fb78cf988d4bba455e069bef2bd5a39846fd2ee5..8c085fd5d2202b4422e93ab39d9b36946109de7e 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3_reg.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3_reg.vhd
@@ -267,4 +267,4 @@ begin
out_new => open
);
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/io/ddr3/src/vhdl/ddr3_seq.vhd b/libraries/io/ddr3/src/vhdl/ddr3_seq.vhd
index dd7f9f3165baa2d3a6abd3e21ab5a3ae9e558f2c..833da44b506f0edb4e0a722db64c39c64ec52100 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3_seq.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3_seq.vhd
@@ -247,4 +247,4 @@ begin
end_addr.row(c_address_w - c_ddr3_phy.a_col_w - 1 downto 0) <= r.end_addr(c_address_w - 1 downto c_ddr3_phy.a_col_w);
end process;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/io/ddr3/src/vhdl/ddr3_transpose.vhd b/libraries/io/ddr3/src/vhdl/ddr3_transpose.vhd
index acb70c1a8083d28bf62b5179752a6f0020c40052..68905b91f2632a92ab644ad82cfea9d5f0989db6 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3_transpose.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3_transpose.vhd
@@ -436,5 +436,4 @@ begin
end process;
end generate;
-end str;
-
+end str;
\ No newline at end of file
diff --git a/libraries/io/ddr3/src/vhdl/mms_ddr3.vhd b/libraries/io/ddr3/src/vhdl/mms_ddr3.vhd
index e265b1bbdc60b0518ddf2f06254a3cee50d94b2e..c88cf43375dda29b85bb259833249b8ac687b6aa 100644
--- a/libraries/io/ddr3/src/vhdl/mms_ddr3.vhd
+++ b/libraries/io/ddr3/src/vhdl/mms_ddr3.vhd
@@ -199,4 +199,4 @@ begin
st_ctlr_rdy => ctlr_rdy
);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/io/ddr3/src/vhdl/mms_ddr3_capture.vhd b/libraries/io/ddr3/src/vhdl/mms_ddr3_capture.vhd
index 593589f38badd1486dc747ae7ac4edd3fd0b9763..a049205477bdffd9239d4b38a8cccdb889025057 100644
--- a/libraries/io/ddr3/src/vhdl/mms_ddr3_capture.vhd
+++ b/libraries/io/ddr3/src/vhdl/mms_ddr3_capture.vhd
@@ -164,4 +164,4 @@ begin
);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/io/ddr3/src/vhdl/seq_ddr3.vhd b/libraries/io/ddr3/src/vhdl/seq_ddr3.vhd
index 52b5db3a7ef13c08e440371b6d78e32cd4f920fb..74c2f69be5243a732b28d8d63f29b5806a367a59 100644
--- a/libraries/io/ddr3/src/vhdl/seq_ddr3.vhd
+++ b/libraries/io/ddr3/src/vhdl/seq_ddr3.vhd
@@ -185,4 +185,4 @@ begin
ctlr_rdy => ctlr_rdy
);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/io/ddr3/tb/vhdl/tb_ddr3.vhd b/libraries/io/ddr3/tb/vhdl/tb_ddr3.vhd
index e772111689d8be0faea7df40ed8f1ac573fdf68e..0485a79f1dcd221b9a1e3323e26316d083bf8288 100644
--- a/libraries/io/ddr3/tb/vhdl/tb_ddr3.vhd
+++ b/libraries/io/ddr3/tb/vhdl/tb_ddr3.vhd
@@ -284,5 +284,4 @@ begin
phy_in => phy_in
);
-end architecture str;
-
+end architecture str;
\ No newline at end of file
diff --git a/libraries/io/epcs/src/vhdl/epcs_reg.vhd b/libraries/io/epcs/src/vhdl/epcs_reg.vhd
index fcbfd13d74fcd4d07fe9f7036290015db5964e4b..4198ceae15c362d7cdc57841cc6541dc9f55feb6 100644
--- a/libraries/io/epcs/src/vhdl/epcs_reg.vhd
+++ b/libraries/io/epcs/src/vhdl/epcs_reg.vhd
@@ -190,4 +190,4 @@ begin
epcs_in_rden <= mm_epcs_in_rden;
unprotect_address_range <= mm_unprotect_address_range;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/io/epcs/src/vhdl/mms_epcs.vhd b/libraries/io/epcs/src/vhdl/mms_epcs.vhd
index 378c674e67a9b391222b252e58c1c3e13cc60a41..d84339ccdcbf5fcdec55a20a3d0d0eb0b0cde7b7 100644
--- a/libraries/io/epcs/src/vhdl/mms_epcs.vhd
+++ b/libraries/io/epcs/src/vhdl/mms_epcs.vhd
@@ -371,4 +371,4 @@ begin
out_rst => epcs_rst
);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/io/epcs/tb/vhdl/tb_mms_epcs.vhd b/libraries/io/epcs/tb/vhdl/tb_mms_epcs.vhd
index 26ddeb8c12658c58a30f1d7644e56cb6ff21148f..5f5d49c099a07a9c84db361b6623b66338309790 100644
--- a/libraries/io/epcs/tb/vhdl/tb_mms_epcs.vhd
+++ b/libraries/io/epcs/tb/vhdl/tb_mms_epcs.vhd
@@ -190,4 +190,4 @@ begin
);
-end architecture str;
+end architecture str;
\ No newline at end of file
diff --git a/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd b/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd
index 09418a0558ad30861fe68d9e0bb3967ae1f77678..60265140c22aaa3b54974b02513b7a7a6d7470ec 100644
--- a/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd
+++ b/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd
@@ -227,7 +227,7 @@ end entity mmm_unb1_eth_10g;
architecture str of mmm_unb1_eth_10g is
constant c_sim_node_type : string(1 to 2) := sel_a_b(g_sim_node_nr <4, "FN", "BN");
- constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type ="BN ", g_sim_node_nr -4, g_sim_node_nr);
+ constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type ="BN ", g_sim_node_nr -4, g_sim_node_nr);
constant c_sim_eth_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := x"00228608" & to_uvec(g_sim_unb_nr, c_byte_w) & to_uvec(g_sim_node_nr, c_byte_w);
constant c_sim_eth_control_rx_en : natural := 2 ** c_eth_mm_reg_control_bi.rx_en;
diff --git a/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/unb1_eth_10g.vhd b/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/unb1_eth_10g.vhd
index 38c9b9a5a5bf0ffaf3277a6f2e1fb5d8a645de08..7ae3eef66c854085074565a31de0b7c3bebac360 100644
--- a/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/unb1_eth_10g.vhd
+++ b/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/unb1_eth_10g.vhd
@@ -75,8 +75,8 @@ entity unb1_eth_10g is
-- 1GbE Control Interface
ETH_clk : in std_logic;
- ETH_SGin : IN std_logic;
- ETH_SGout : OUT std_logic;
+ ETH_SGin : in std_logic;
+ ETH_SGout : out std_logic;
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- SerDes Clock BN-BI / SI_FN
@@ -136,7 +136,7 @@ architecture str of unb1_eth_10g is
-- . UDP total length: 8 (UDP header) + 20 (usr header) + 2920 (payload bytes) = 2948 -- 1488
constant c_ip_length : natural := c_bg_block_size * 8 + 50; --2970;
constant c_udp_length : natural := c_bg_block_size * 8 + 30; --2950;
- constant c_nof_hdr_fields : natural := 3 +12 + 4 + 9 + 1; -- Total header bits = 512
+ constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 9 + 1; -- Total header bits = 512
constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
@@ -172,7 +172,7 @@ architecture str of unb1_eth_10g is
constant c_bypass_rx_filter : boolean := TRUE;
- constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "111" &"111111111111 " &"0011 " &"001111111 " &"0 ";
+ constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "111" &"111111111111 " &"0011 " &"001111111 " &"0 ";
constant c_nof_crc_words : natural := 0;
constant c_max_nof_words_per_block : natural := c_bg_block_size;
@@ -888,5 +888,4 @@ begin
reg_mdio_1_miso <= reg_mdio_miso_arr(1);
reg_mdio_2_miso <= reg_mdio_miso_arr(2);
-end str;
-
+end str;
\ No newline at end of file
diff --git a/libraries/io/eth/src/vhdl/eth_control.vhd b/libraries/io/eth/src/vhdl/eth_control.vhd
index ca2fa213edc7fce46d2df8b6096464fd2c1c2880..9f767b43e19156e747ed366d75abcadbefa42183 100644
--- a/libraries/io/eth/src/vhdl/eth_control.vhd
+++ b/libraries/io/eth/src/vhdl/eth_control.vhd
@@ -110,8 +110,8 @@ architecture rtl of eth_control is
signal i_mem_in : t_mem_mosi;
signal nxt_mem_in : t_mem_mosi;
- signal rd_val : std_logic_vector(0 TO c_mem_ram_rd_latency); -- use [0] to combinatorially store rd (= rd_en)
- signal nxt_rd_val : std_logic_vector(1 TO c_mem_ram_rd_latency);
+ signal rd_val : std_logic_vector(0 to c_mem_ram_rd_latency); -- use [0] to combinatorially store rd (= rd_en)
+ signal nxt_rd_val : std_logic_vector(1 to c_mem_ram_rd_latency);
signal rd_sop : std_logic_vector( rd_val'range);
signal nxt_rd_sop : std_logic_vector(nxt_rd_val'range);
signal rd_eop : std_logic_vector( rd_val'range);
diff --git a/libraries/io/eth/src/vhdl/eth_hdr.vhd b/libraries/io/eth/src/vhdl/eth_hdr.vhd
index 0d74b8b71301067a5a5574b1de7bc4550595df77..b69d1055d5c62501fc5d15fbec0df854bf9a0982 100644
--- a/libraries/io/eth/src/vhdl/eth_hdr.vhd
+++ b/libraries/io/eth/src/vhdl/eth_hdr.vhd
@@ -60,9 +60,9 @@ entity eth_hdr is
-- Header info
hdr_words_arr : out t_network_total_header_32b_arr;
- hdr_words_arr_val : out std_logic_vector(0 TO c_network_total_header_32b_nof_words - 1);
+ hdr_words_arr_val : out std_logic_vector(0 to c_network_total_header_32b_nof_words - 1);
hdr_fields : out t_network_total_header;
- hdr_fields_val : out std_logic_vector(0 TO c_network_total_header_32b_nof_words - 1);
+ hdr_fields_val : out std_logic_vector(0 to c_network_total_header_32b_nof_words - 1);
hdr_data : out std_logic_vector(c_word_w - 1 downto 0);
hdr_data_val : out std_logic;
hdr_status : out t_eth_hdr_status;
@@ -81,9 +81,9 @@ architecture str of eth_hdr is
-- Extract total header
signal i_hdr_words_arr : t_network_total_header_32b_arr;
- signal i_hdr_words_arr_val : std_logic_vector(0 TO c_network_total_header_32b_nof_words - 1);
+ signal i_hdr_words_arr_val : std_logic_vector(0 to c_network_total_header_32b_nof_words - 1);
signal i_hdr_fields : t_network_total_header;
- signal i_hdr_fields_val : std_logic_vector(0 TO c_network_total_header_32b_nof_words - 1);
+ signal i_hdr_fields_val : std_logic_vector(0 to c_network_total_header_32b_nof_words - 1);
signal i_hdr_data : std_logic_vector(c_word_w - 1 downto 0);
signal i_hdr_data_val : std_logic;
signal i_hdr_status : t_eth_hdr_status;
diff --git a/libraries/io/eth/src/vhdl/eth_hdr_status.vhd b/libraries/io/eth/src/vhdl/eth_hdr_status.vhd
index fe732786459777cbd41901626f65b53880559229..0fc6b4045448ddb089d9ef4e09e856a29358e061 100644
--- a/libraries/io/eth/src/vhdl/eth_hdr_status.vhd
+++ b/libraries/io/eth/src/vhdl/eth_hdr_status.vhd
@@ -52,9 +52,9 @@ entity eth_hdr_status is
-- Total header
hdr_words_arr : in t_network_total_header_32b_arr;
- hdr_words_arr_val : in std_logic_vector(0 TO c_network_total_header_32b_nof_words - 1);
+ hdr_words_arr_val : in std_logic_vector(0 to c_network_total_header_32b_nof_words - 1);
hdr_fields : in t_network_total_header;
- hdr_fields_val : in std_logic_vector(0 TO c_network_total_header_32b_nof_words - 1);
+ hdr_fields_val : in std_logic_vector(0 to c_network_total_header_32b_nof_words - 1);
hdr_data : in std_logic_vector(c_word_w - 1 downto 0);
hdr_data_val : in std_logic;
diff --git a/libraries/io/eth/src/vhdl/eth_hdr_store.vhd b/libraries/io/eth/src/vhdl/eth_hdr_store.vhd
index 701f81a05d49b8fe173ee0aee09ada605d127df2..d16c626bba5e4abc1b1865bd279c01531ca74ded 100644
--- a/libraries/io/eth/src/vhdl/eth_hdr_store.vhd
+++ b/libraries/io/eth/src/vhdl/eth_hdr_store.vhd
@@ -64,10 +64,10 @@ entity eth_hdr_store is
-- Total header
hdr_words_arr : out t_network_total_header_32b_arr;
- hdr_words_arr_val : out std_logic_vector(0 TO c_network_total_header_32b_nof_words - 1);
+ hdr_words_arr_val : out std_logic_vector(0 to c_network_total_header_32b_nof_words - 1);
-- Combinatorial map of the 11 header words on to the Ethernet header records
hdr_fields : out t_network_total_header;
- hdr_fields_val : out std_logic_vector(0 TO c_network_total_header_32b_nof_words - 1);
+ hdr_fields_val : out std_logic_vector(0 to c_network_total_header_32b_nof_words - 1);
-- Support also outputting only the currently valid header data
hdr_data : out std_logic_vector(c_word_w - 1 downto 0);
hdr_data_val : out std_logic
diff --git a/libraries/io/eth/src/vhdl/eth_pkg.vhd b/libraries/io/eth/src/vhdl/eth_pkg.vhd
index b0f87cddd725bb03ce5cb82ce3856df0a35c2c2a..35befeed97d70499914cc0e2f5871681368f91e0 100644
--- a/libraries/io/eth/src/vhdl/eth_pkg.vhd
+++ b/libraries/io/eth/src/vhdl/eth_pkg.vhd
@@ -109,7 +109,7 @@ package eth_pkg is
-- . write/read back registers
type t_eth_demux_ports_arr is array(1 to c_eth_nof_udp_ports) of std_logic_vector(c_network_udp_port_w - 1 downto 0);
type t_eth_mm_reg_demux is record
- udp_ports_en : std_logic_vector(1 TO c_eth_nof_udp_ports); -- [16]
+ udp_ports_en : std_logic_vector(1 to c_eth_nof_udp_ports); -- [16]
udp_ports : t_eth_demux_ports_arr; -- [15:0]
end record;
@@ -353,4 +353,4 @@ package body eth_pkg is
return v_reg;
end func_eth_mm_reg_status;
-end eth_pkg;
+end eth_pkg;
\ No newline at end of file
diff --git a/libraries/io/eth/src/vhdl/eth_tester_axi4_wrapper.vhd b/libraries/io/eth/src/vhdl/eth_tester_axi4_wrapper.vhd
index 1dc6ba295c786292a12cff7c58eccecd0d88cb55..51cb65218297ab58e215b4f5afb75e335ed09010 100644
--- a/libraries/io/eth/src/vhdl/eth_tester_axi4_wrapper.vhd
+++ b/libraries/io/eth/src/vhdl/eth_tester_axi4_wrapper.vhd
@@ -1,612 +1,612 @@
--------------------------------------------------------------------------------
---
--- Copyright 2023
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- Licensed under the Apache License, Version 2.0 (the "License");
--- you may not use this file except in compliance with the License.
--- You may obtain a copy of the License at
---
--- http://www.apache.org/licenses/LICENSE-2.0
---
--- Unless required by applicable law or agreed to in writing, software
--- distributed under the License is distributed on an "AS IS" BASIS,
--- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--- See the License for the specific language governing permissions and
--- limitations under the License.
---
--------------------------------------------------------------------------------
--- Author: R. van der Walle
--- Purpose: Provide AXI4-Stream and AXI4-Lite interface for eth_tester.vhd such
--- that it can be used to create a Vivado IP block.
--- Description:
--- . The eth_tester_axi4_wrapper uses axi4_stream_dp_bridge to convert the dp
--- sosi/siso interfaces of the eth_tester into AXI4-Stream interfaces.
--- Similarly, axi4_lite_mm_bridge is used to convert the mem copi/cipo
--- interfaces into AXI4_Lite interfaces.
--- . In order for this component to be suitable as a Vivado IP, the ports are
--- exclusively STD_LOGIC(_VECTOR) where the widths are hard-coded as demanded
--- by the Vivado IP creator (only supports VHDL-93).
-
-LIBRARY IEEE, common_lib, dp_lib, diag_lib, axi4_lib;
-USE IEEE.std_logic_1164.ALL;
-USE common_lib.common_pkg.ALL;
-USE common_lib.common_mem_pkg.ALL;
-USE common_lib.common_network_layers_pkg.ALL;
-USE dp_lib.dp_stream_pkg.ALL;
-USE dp_lib.dp_components_pkg.ALL;
-USE diag_lib.diag_pkg.ALL;
-USE axi4_lib.axi4_stream_pkg.ALL;
-USE axi4_lib.axi4_lite_pkg.ALL;
-USE work.eth_pkg.ALL;
-USE work.eth_tester_pkg.ALL;
-
-ENTITY eth_tester_axi4_wrapper IS
- PORT (
- -- Clocks and reset
- mm_clk : IN STD_LOGIC;
- st_clk : IN STD_LOGIC;
- st_pps : IN STD_LOGIC;
- aresetn : IN STD_LOGIC;
- -- UDP transmit interface
- eth_src_mac : IN STD_LOGIC_VECTOR(6*8-1 DOWNTO 0);
- ip_src_addr : IN STD_LOGIC_VECTOR(4*8-1 DOWNTO 0);
- udp_src_port : IN STD_LOGIC_VECTOR(2*8-1 DOWNTO 0);
-
- tx_fifo_rd_emp_arr : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
-
- -- tx_udp
- -- Source In and Sink Out
- tx_udp_tready : IN STD_LOGIC;
-
- -- Source Out and Sink In
- tx_udp_tvalid : OUT STD_LOGIC;
- tx_udp_tdata : OUT STD_LOGIC_VECTOR(512-1 DOWNTO 0);
- tx_udp_tstrb : OUT STD_LOGIC_VECTOR(512/8-1 DOWNTO 0);
- tx_udp_tkeep : OUT STD_LOGIC_VECTOR(512/8-1 DOWNTO 0);
- tx_udp_tlast : OUT STD_LOGIC;
- tx_udp_tid : OUT STD_LOGIC_VECTOR(4-1 DOWNTO 0);
- tx_udp_tdest : OUT STD_LOGIC_VECTOR(32-1 DOWNTO 0);
- tx_udp_tuser : OUT STD_LOGIC_VECTOR(70-1 DOWNTO 0);
-
- -- rx_udp
- -- Source In and Sink Out
- rx_udp_tready : OUT STD_LOGIC;
-
- -- Source Out and Sink In
- rx_udp_tvalid : IN STD_LOGIC;
- rx_udp_tdata : IN STD_LOGIC_VECTOR(512-1 DOWNTO 0);
- rx_udp_tstrb : IN STD_LOGIC_VECTOR(512/8-1 DOWNTO 0);
- rx_udp_tkeep : IN STD_LOGIC_VECTOR(512/8-1 DOWNTO 0);
- rx_udp_tlast : IN STD_LOGIC;
- rx_udp_tid : IN STD_LOGIC_VECTOR(4-1 DOWNTO 0);
- rx_udp_tdest : IN STD_LOGIC_VECTOR(32-1 DOWNTO 0);
- rx_udp_tuser : IN STD_LOGIC_VECTOR(70-1 DOWNTO 0);
-
- -- reg_bg_ctrl
- -- copi
- reg_bg_ctrl_awaddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
- reg_bg_ctrl_awprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
- reg_bg_ctrl_awvalid : IN STD_LOGIC;
- reg_bg_ctrl_wdata : IN STD_LOGIC_VECTOR(32-1 downto 0);
- reg_bg_ctrl_wstrb : IN STD_LOGIC_VECTOR((32/8)-1 downto 0);
- reg_bg_ctrl_wvalid : IN STD_LOGIC;
- reg_bg_ctrl_bready : IN STD_LOGIC;
- reg_bg_ctrl_araddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
- reg_bg_ctrl_arprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
- reg_bg_ctrl_arvalid : IN STD_LOGIC;
- reg_bg_ctrl_rready : IN STD_LOGIC;
- -- cipo
- reg_bg_ctrl_awready : OUT STD_LOGIC;
- reg_bg_ctrl_wready : OUT STD_LOGIC;
- reg_bg_ctrl_bresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
- reg_bg_ctrl_bvalid : OUT STD_LOGIC;
- reg_bg_ctrl_arready : OUT STD_LOGIC;
- reg_bg_ctrl_rdata : OUT STD_LOGIC_VECTOR(32-1 downto 0);
- reg_bg_ctrl_rresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
- reg_bg_ctrl_rvalid : OUT STD_LOGIC;
-
- -- reg_hdr_dat
- -- copi
- reg_hdr_dat_awaddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
- reg_hdr_dat_awprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
- reg_hdr_dat_awvalid : IN STD_LOGIC;
- reg_hdr_dat_wdata : IN STD_LOGIC_VECTOR(32-1 downto 0);
- reg_hdr_dat_wstrb : IN STD_LOGIC_VECTOR((32/8)-1 downto 0);
- reg_hdr_dat_wvalid : IN STD_LOGIC;
- reg_hdr_dat_bready : IN STD_LOGIC;
- reg_hdr_dat_araddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
- reg_hdr_dat_arprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
- reg_hdr_dat_arvalid : IN STD_LOGIC;
- reg_hdr_dat_rready : IN STD_LOGIC;
- -- cipo
- reg_hdr_dat_awready : OUT STD_LOGIC;
- reg_hdr_dat_wready : OUT STD_LOGIC;
- reg_hdr_dat_bresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
- reg_hdr_dat_bvalid : OUT STD_LOGIC;
- reg_hdr_dat_arready : OUT STD_LOGIC;
- reg_hdr_dat_rdata : OUT STD_LOGIC_VECTOR(32-1 downto 0);
- reg_hdr_dat_rresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
- reg_hdr_dat_rvalid : OUT STD_LOGIC;
-
- -- reg_bsn_monitor_v2_tx
- -- copi
- reg_bsn_monitor_v2_tx_awaddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
- reg_bsn_monitor_v2_tx_awprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
- reg_bsn_monitor_v2_tx_awvalid : IN STD_LOGIC;
- reg_bsn_monitor_v2_tx_wdata : IN STD_LOGIC_VECTOR(32-1 downto 0);
- reg_bsn_monitor_v2_tx_wstrb : IN STD_LOGIC_VECTOR((32/8)-1 downto 0);
- reg_bsn_monitor_v2_tx_wvalid : IN STD_LOGIC;
- reg_bsn_monitor_v2_tx_bready : IN STD_LOGIC;
- reg_bsn_monitor_v2_tx_araddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
- reg_bsn_monitor_v2_tx_arprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
- reg_bsn_monitor_v2_tx_arvalid : IN STD_LOGIC;
- reg_bsn_monitor_v2_tx_rready : IN STD_LOGIC;
- -- cipo
- reg_bsn_monitor_v2_tx_awready : OUT STD_LOGIC;
- reg_bsn_monitor_v2_tx_wready : OUT STD_LOGIC;
- reg_bsn_monitor_v2_tx_bresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
- reg_bsn_monitor_v2_tx_bvalid : OUT STD_LOGIC;
- reg_bsn_monitor_v2_tx_arready : OUT STD_LOGIC;
- reg_bsn_monitor_v2_tx_rdata : OUT STD_LOGIC_VECTOR(32-1 downto 0);
- reg_bsn_monitor_v2_tx_rresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
- reg_bsn_monitor_v2_tx_rvalid : OUT STD_LOGIC;
-
- -- reg_strobe_total_count_tx
- -- copi
- reg_strobe_total_count_tx_awaddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
- reg_strobe_total_count_tx_awprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
- reg_strobe_total_count_tx_awvalid : IN STD_LOGIC;
- reg_strobe_total_count_tx_wdata : IN STD_LOGIC_VECTOR(32-1 downto 0);
- reg_strobe_total_count_tx_wstrb : IN STD_LOGIC_VECTOR((32/8)-1 downto 0);
- reg_strobe_total_count_tx_wvalid : IN STD_LOGIC;
- reg_strobe_total_count_tx_bready : IN STD_LOGIC;
- reg_strobe_total_count_tx_araddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
- reg_strobe_total_count_tx_arprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
- reg_strobe_total_count_tx_arvalid : IN STD_LOGIC;
- reg_strobe_total_count_tx_rready : IN STD_LOGIC;
- -- cipo
- reg_strobe_total_count_tx_awready : OUT STD_LOGIC;
- reg_strobe_total_count_tx_wready : OUT STD_LOGIC;
- reg_strobe_total_count_tx_bresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
- reg_strobe_total_count_tx_bvalid : OUT STD_LOGIC;
- reg_strobe_total_count_tx_arready : OUT STD_LOGIC;
- reg_strobe_total_count_tx_rdata : OUT STD_LOGIC_VECTOR(32-1 downto 0);
- reg_strobe_total_count_tx_rresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
- reg_strobe_total_count_tx_rvalid : OUT STD_LOGIC;
-
- -- reg_bsn_monitor_v2_rx
- -- copi
- reg_bsn_monitor_v2_rx_awaddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
- reg_bsn_monitor_v2_rx_awprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
- reg_bsn_monitor_v2_rx_awvalid : IN STD_LOGIC;
- reg_bsn_monitor_v2_rx_wdata : IN STD_LOGIC_VECTOR(32-1 downto 0);
- reg_bsn_monitor_v2_rx_wstrb : IN STD_LOGIC_VECTOR((32/8)-1 downto 0);
- reg_bsn_monitor_v2_rx_wvalid : IN STD_LOGIC;
- reg_bsn_monitor_v2_rx_bready : IN STD_LOGIC;
- reg_bsn_monitor_v2_rx_araddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
- reg_bsn_monitor_v2_rx_arprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
- reg_bsn_monitor_v2_rx_arvalid : IN STD_LOGIC;
- reg_bsn_monitor_v2_rx_rready : IN STD_LOGIC;
- -- cipo
- reg_bsn_monitor_v2_rx_awready : OUT STD_LOGIC;
- reg_bsn_monitor_v2_rx_wready : OUT STD_LOGIC;
- reg_bsn_monitor_v2_rx_bresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
- reg_bsn_monitor_v2_rx_bvalid : OUT STD_LOGIC;
- reg_bsn_monitor_v2_rx_arready : OUT STD_LOGIC;
- reg_bsn_monitor_v2_rx_rdata : OUT STD_LOGIC_VECTOR(32-1 downto 0);
- reg_bsn_monitor_v2_rx_rresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
- reg_bsn_monitor_v2_rx_rvalid : OUT STD_LOGIC;
-
- -- reg_strobe_total_count_rx
- -- copi
- reg_strobe_total_count_rx_awaddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
- reg_strobe_total_count_rx_awprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
- reg_strobe_total_count_rx_awvalid : IN STD_LOGIC;
- reg_strobe_total_count_rx_wdata : IN STD_LOGIC_VECTOR(32-1 downto 0);
- reg_strobe_total_count_rx_wstrb : IN STD_LOGIC_VECTOR((32/8)-1 downto 0);
- reg_strobe_total_count_rx_wvalid : IN STD_LOGIC;
- reg_strobe_total_count_rx_bready : IN STD_LOGIC;
- reg_strobe_total_count_rx_araddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
- reg_strobe_total_count_rx_arprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
- reg_strobe_total_count_rx_arvalid : IN STD_LOGIC;
- reg_strobe_total_count_rx_rready : IN STD_LOGIC;
- -- cipo
- reg_strobe_total_count_rx_awready : OUT STD_LOGIC;
- reg_strobe_total_count_rx_wready : OUT STD_LOGIC;
- reg_strobe_total_count_rx_bresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
- reg_strobe_total_count_rx_bvalid : OUT STD_LOGIC;
- reg_strobe_total_count_rx_arready : OUT STD_LOGIC;
- reg_strobe_total_count_rx_rdata : OUT STD_LOGIC_VECTOR(32-1 downto 0);
- reg_strobe_total_count_rx_rresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
- reg_strobe_total_count_rx_rvalid : OUT STD_LOGIC
-
- );
-END eth_tester_axi4_wrapper;
-
-
-ARCHITECTURE str OF eth_tester_axi4_wrapper IS
- SIGNAL rx_udp_sosi_arr : t_dp_sosi_arr(0 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL rx_udp_siso_arr : t_dp_siso_arr(0 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
- SIGNAL tx_udp_sosi_arr : t_dp_sosi_arr(0 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL tx_udp_siso_arr : t_dp_siso_arr(0 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
-
- SIGNAL rx_udp_axi4_sosi : t_axi4_sosi := c_axi4_sosi_rst;
- SIGNAL rx_udp_axi4_siso : t_axi4_siso := c_axi4_siso_rst;
- SIGNAL tx_udp_axi4_sosi : t_axi4_sosi := c_axi4_sosi_rst;
- SIGNAL tx_udp_axi4_siso : t_axi4_siso := c_axi4_siso_rst;
-
- SIGNAL reg_bg_ctrl_copi : t_mem_copi := c_mem_copi_rst;
- SIGNAL reg_bg_ctrl_cipo : t_mem_cipo;
- SIGNAL reg_hdr_dat_copi : t_mem_copi := c_mem_copi_rst;
- SIGNAL reg_hdr_dat_cipo : t_mem_cipo;
- SIGNAL reg_bsn_monitor_v2_tx_copi : t_mem_copi := c_mem_copi_rst;
- SIGNAL reg_bsn_monitor_v2_tx_cipo : t_mem_cipo;
- SIGNAL reg_strobe_total_count_tx_copi : t_mem_copi := c_mem_copi_rst;
- SIGNAL reg_strobe_total_count_tx_cipo : t_mem_cipo;
-
- SIGNAL reg_bsn_monitor_v2_rx_copi : t_mem_copi := c_mem_copi_rst;
- SIGNAL reg_bsn_monitor_v2_rx_cipo : t_mem_cipo;
- SIGNAL reg_strobe_total_count_rx_copi : t_mem_copi := c_mem_copi_rst;
- SIGNAL reg_strobe_total_count_rx_cipo : t_mem_cipo;
-
-
- SIGNAL reg_bg_ctrl_axi4_copi : t_axi4_lite_copi := c_axi4_lite_copi_rst;
- SIGNAL reg_bg_ctrl_axi4_cipo : t_axi4_lite_cipo;
- SIGNAL reg_hdr_dat_axi4_copi : t_axi4_lite_copi := c_axi4_lite_copi_rst;
- SIGNAL reg_hdr_dat_axi4_cipo : t_axi4_lite_cipo;
- SIGNAL reg_bsn_monitor_v2_tx_axi4_copi : t_axi4_lite_copi := c_axi4_lite_copi_rst;
- SIGNAL reg_bsn_monitor_v2_tx_axi4_cipo : t_axi4_lite_cipo;
- SIGNAL reg_strobe_total_count_tx_axi4_copi : t_axi4_lite_copi := c_axi4_lite_copi_rst;
- SIGNAL reg_strobe_total_count_tx_axi4_cipo : t_axi4_lite_cipo;
-
- SIGNAL reg_bsn_monitor_v2_rx_axi4_copi : t_axi4_lite_copi := c_axi4_lite_copi_rst;
- SIGNAL reg_bsn_monitor_v2_rx_axi4_cipo : t_axi4_lite_cipo;
- SIGNAL reg_strobe_total_count_rx_axi4_copi : t_axi4_lite_copi := c_axi4_lite_copi_rst;
- SIGNAL reg_strobe_total_count_rx_axi4_cipo : t_axi4_lite_cipo;
-
- SIGNAL mm_rst : STD_LOGIC := '0';
- SIGNAL st_rst : STD_LOGIC := '0';
-
-BEGIN
-
- u_eth_tester : ENTITY work.eth_tester
- GENERIC MAP (
- g_remove_crc => FALSE
- )
- PORT MAP (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
- st_pps => st_pps,
-
- -- UDP transmit interface
- eth_src_mac => eth_src_mac,
- ip_src_addr => ip_src_addr,
- udp_src_port => udp_src_port,
-
- tx_fifo_rd_emp_arr => tx_fifo_rd_emp_arr,
-
- tx_udp_sosi_arr => tx_udp_sosi_arr,
- tx_udp_siso_arr => tx_udp_siso_arr,
-
- -- UDP receive interface
- rx_udp_sosi_arr => rx_udp_sosi_arr,
-
- -- Memory Mapped Slaves (one per stream)
- reg_bg_ctrl_copi => reg_bg_ctrl_copi,
- reg_bg_ctrl_cipo => reg_bg_ctrl_cipo,
- reg_hdr_dat_copi => reg_hdr_dat_copi,
- reg_hdr_dat_cipo => reg_hdr_dat_cipo,
- reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_copi,
- reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_cipo,
- reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_copi,
- reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_cipo,
-
- reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_copi,
- reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_cipo,
- reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_copi,
- reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_cipo
- );
-
- -- DP to AXI4
- u_axi4_tx_udp : ENTITY axi4_lib.axi4_stream_dp_bridge
- GENERIC MAP (
- g_axi4_rl => 0,
- g_dp_rl => 1,
- g_active_low_rst => TRUE
- )
- PORT MAP (
- in_clk => st_clk,
- in_rst => aresetn,
-
- dp_rst => st_rst,
-
- dp_in_sosi => tx_udp_sosi_arr(0),
- dp_in_siso => tx_udp_siso_arr(0),
-
- axi4_out_sosi => tx_udp_axi4_sosi,
- axi4_out_siso => tx_udp_axi4_siso
- );
-
- u_axi4_rx_udp : ENTITY axi4_lib.axi4_stream_dp_bridge
- GENERIC MAP (
- g_axi4_rl => 0,
- g_dp_rl => 1,
- g_active_low_rst => TRUE
- )
- PORT MAP (
- in_clk => st_clk,
- in_rst => aresetn,
-
- axi4_in_sosi => rx_udp_axi4_sosi,
- axi4_in_siso => rx_udp_axi4_siso,
-
- dp_out_sosi => rx_udp_sosi_arr(0),
- dp_out_siso => rx_udp_siso_arr(0)
- );
-
- -- AXI4 to MM
- u_axi4_reg_bg_ctrl : ENTITY axi4_lib.axi4_lite_mm_bridge
- GENERIC MAP (
- g_active_low_rst => TRUE
- )
- PORT MAP (
- in_clk => mm_clk,
- in_rst => aresetn,
-
- mm_rst => mm_rst,
-
- axi4_in_copi => reg_bg_ctrl_axi4_copi,
- axi4_in_cipo => reg_bg_ctrl_axi4_cipo,
-
- mm_out_copi => reg_bg_ctrl_copi,
- mm_out_cipo => reg_bg_ctrl_cipo
- );
-
- u_axi4_reg_hdr_dat : ENTITY axi4_lib.axi4_lite_mm_bridge
- GENERIC MAP (
- g_active_low_rst => TRUE
- )
- PORT MAP (
- in_clk => mm_clk,
- in_rst => aresetn,
-
- axi4_in_copi => reg_hdr_dat_axi4_copi,
- axi4_in_cipo => reg_hdr_dat_axi4_cipo,
-
- mm_out_copi => reg_hdr_dat_copi,
- mm_out_cipo => reg_hdr_dat_cipo
- );
-
-
- u_axi4_reg_bsn_monitor_v2_tx : ENTITY axi4_lib.axi4_lite_mm_bridge
- GENERIC MAP (
- g_active_low_rst => TRUE
- )
- PORT MAP (
- in_clk => mm_clk,
- in_rst => aresetn,
-
- axi4_in_copi => reg_bsn_monitor_v2_tx_axi4_copi,
- axi4_in_cipo => reg_bsn_monitor_v2_tx_axi4_cipo,
-
- mm_out_copi => reg_bsn_monitor_v2_tx_copi,
- mm_out_cipo => reg_bsn_monitor_v2_tx_cipo
- );
-
-
- u_axi4_reg_strobe_total_count_tx : ENTITY axi4_lib.axi4_lite_mm_bridge
- GENERIC MAP (
- g_active_low_rst => TRUE
- )
- PORT MAP (
- in_clk => mm_clk,
- in_rst => aresetn,
-
- axi4_in_copi => reg_strobe_total_count_tx_axi4_copi,
- axi4_in_cipo => reg_strobe_total_count_tx_axi4_cipo,
-
- mm_out_copi => reg_strobe_total_count_tx_copi,
- mm_out_cipo => reg_strobe_total_count_tx_cipo
- );
-
-
- u_axi4_reg_bsn_monitor_v2_rx : ENTITY axi4_lib.axi4_lite_mm_bridge
- GENERIC MAP (
- g_active_low_rst => TRUE
- )
- PORT MAP (
- in_clk => mm_clk,
- in_rst => aresetn,
-
- axi4_in_copi => reg_bsn_monitor_v2_rx_axi4_copi,
- axi4_in_cipo => reg_bsn_monitor_v2_rx_axi4_cipo,
-
- mm_out_copi => reg_bsn_monitor_v2_rx_copi,
- mm_out_cipo => reg_bsn_monitor_v2_rx_cipo
- );
-
- u_axi4_reg_strobe_total_count_rx : ENTITY axi4_lib.axi4_lite_mm_bridge
- GENERIC MAP (
- g_active_low_rst => TRUE
- )
- PORT MAP (
- in_clk => mm_clk,
- in_rst => aresetn,
-
- axi4_in_copi => reg_strobe_total_count_rx_axi4_copi,
- axi4_in_cipo => reg_strobe_total_count_rx_axi4_cipo,
-
- mm_out_copi => reg_strobe_total_count_rx_copi,
- mm_out_cipo => reg_strobe_total_count_rx_cipo
- );
-
- -- Wire Records to IN/OUT ports.
-
- -- tx_udp
- tx_udp_axi4_siso.tready <= tx_udp_tready;
-
- tx_udp_tvalid <= tx_udp_axi4_sosi.tvalid;
- tx_udp_tdata <= tx_udp_axi4_sosi.tdata;
- tx_udp_tstrb <= tx_udp_axi4_sosi.tstrb;
- tx_udp_tkeep <= tx_udp_axi4_sosi.tkeep;
- tx_udp_tlast <= tx_udp_axi4_sosi.tlast;
- tx_udp_tid <= tx_udp_axi4_sosi.tid;
- tx_udp_tdest <= tx_udp_axi4_sosi.tdest;
- tx_udp_tuser <= tx_udp_axi4_sosi.tuser;
-
- -- rx_udp
- rx_udp_tready <= rx_udp_axi4_siso.tready;
-
- rx_udp_axi4_sosi.tvalid <= rx_udp_tvalid;
- rx_udp_axi4_sosi.tdata <= rx_udp_tdata;
- rx_udp_axi4_sosi.tstrb <= rx_udp_tstrb;
- rx_udp_axi4_sosi.tkeep <= rx_udp_tkeep;
- rx_udp_axi4_sosi.tlast <= rx_udp_tlast;
- rx_udp_axi4_sosi.tid <= rx_udp_tid;
- rx_udp_axi4_sosi.tdest <= rx_udp_tdest;
- rx_udp_axi4_sosi.tuser <= rx_udp_tuser;
-
- -- reg_bg_ctrl
- -- copi
- reg_bg_ctrl_axi4_copi.awaddr <= reg_bg_ctrl_awaddr;
- reg_bg_ctrl_axi4_copi.awprot <= reg_bg_ctrl_awprot;
- reg_bg_ctrl_axi4_copi.awvalid <= reg_bg_ctrl_awvalid;
- reg_bg_ctrl_axi4_copi.wdata <= reg_bg_ctrl_wdata;
- reg_bg_ctrl_axi4_copi.wstrb <= reg_bg_ctrl_wstrb;
- reg_bg_ctrl_axi4_copi.wvalid <= reg_bg_ctrl_wvalid;
- reg_bg_ctrl_axi4_copi.bready <= reg_bg_ctrl_bready;
- reg_bg_ctrl_axi4_copi.araddr <= reg_bg_ctrl_araddr;
- reg_bg_ctrl_axi4_copi.arprot <= reg_bg_ctrl_arprot;
- reg_bg_ctrl_axi4_copi.arvalid <= reg_bg_ctrl_arvalid;
- reg_bg_ctrl_axi4_copi.rready <= reg_bg_ctrl_rready;
- -- cipo
- reg_bg_ctrl_awready <= reg_bg_ctrl_axi4_cipo.awready;
- reg_bg_ctrl_wready <= reg_bg_ctrl_axi4_cipo.wready;
- reg_bg_ctrl_bresp <= reg_bg_ctrl_axi4_cipo.bresp;
- reg_bg_ctrl_bvalid <= reg_bg_ctrl_axi4_cipo.bvalid;
- reg_bg_ctrl_arready <= reg_bg_ctrl_axi4_cipo.arready;
- reg_bg_ctrl_rdata <= reg_bg_ctrl_axi4_cipo.rdata;
- reg_bg_ctrl_rresp <= reg_bg_ctrl_axi4_cipo.rresp;
- reg_bg_ctrl_rvalid <= reg_bg_ctrl_axi4_cipo.rvalid;
-
- -- reg_hdr_dat
- -- copi
- reg_hdr_dat_axi4_copi.awaddr <= reg_hdr_dat_awaddr;
- reg_hdr_dat_axi4_copi.awprot <= reg_hdr_dat_awprot;
- reg_hdr_dat_axi4_copi.awvalid <= reg_hdr_dat_awvalid;
- reg_hdr_dat_axi4_copi.wdata <= reg_hdr_dat_wdata;
- reg_hdr_dat_axi4_copi.wstrb <= reg_hdr_dat_wstrb;
- reg_hdr_dat_axi4_copi.wvalid <= reg_hdr_dat_wvalid;
- reg_hdr_dat_axi4_copi.bready <= reg_hdr_dat_bready;
- reg_hdr_dat_axi4_copi.araddr <= reg_hdr_dat_araddr;
- reg_hdr_dat_axi4_copi.arprot <= reg_hdr_dat_arprot;
- reg_hdr_dat_axi4_copi.arvalid <= reg_hdr_dat_arvalid;
- reg_hdr_dat_axi4_copi.rready <= reg_hdr_dat_rready;
- -- cipo
- reg_hdr_dat_awready <= reg_hdr_dat_axi4_cipo.awready;
- reg_hdr_dat_wready <= reg_hdr_dat_axi4_cipo.wready;
- reg_hdr_dat_bresp <= reg_hdr_dat_axi4_cipo.bresp;
- reg_hdr_dat_bvalid <= reg_hdr_dat_axi4_cipo.bvalid;
- reg_hdr_dat_arready <= reg_hdr_dat_axi4_cipo.arready;
- reg_hdr_dat_rdata <= reg_hdr_dat_axi4_cipo.rdata;
- reg_hdr_dat_rresp <= reg_hdr_dat_axi4_cipo.rresp;
- reg_hdr_dat_rvalid <= reg_hdr_dat_axi4_cipo.rvalid;
-
- -- reg_bsn_monitor_v2_tx
- -- copi
- reg_bsn_monitor_v2_tx_axi4_copi.awaddr <= reg_bsn_monitor_v2_tx_awaddr;
- reg_bsn_monitor_v2_tx_axi4_copi.awprot <= reg_bsn_monitor_v2_tx_awprot;
- reg_bsn_monitor_v2_tx_axi4_copi.awvalid <= reg_bsn_monitor_v2_tx_awvalid;
- reg_bsn_monitor_v2_tx_axi4_copi.wdata <= reg_bsn_monitor_v2_tx_wdata;
- reg_bsn_monitor_v2_tx_axi4_copi.wstrb <= reg_bsn_monitor_v2_tx_wstrb;
- reg_bsn_monitor_v2_tx_axi4_copi.wvalid <= reg_bsn_monitor_v2_tx_wvalid;
- reg_bsn_monitor_v2_tx_axi4_copi.bready <= reg_bsn_monitor_v2_tx_bready;
- reg_bsn_monitor_v2_tx_axi4_copi.araddr <= reg_bsn_monitor_v2_tx_araddr;
- reg_bsn_monitor_v2_tx_axi4_copi.arprot <= reg_bsn_monitor_v2_tx_arprot;
- reg_bsn_monitor_v2_tx_axi4_copi.arvalid <= reg_bsn_monitor_v2_tx_arvalid;
- reg_bsn_monitor_v2_tx_axi4_copi.rready <= reg_bsn_monitor_v2_tx_rready;
- -- cipo
- reg_bsn_monitor_v2_tx_awready <= reg_bsn_monitor_v2_tx_axi4_cipo.awready;
- reg_bsn_monitor_v2_tx_wready <= reg_bsn_monitor_v2_tx_axi4_cipo.wready;
- reg_bsn_monitor_v2_tx_bresp <= reg_bsn_monitor_v2_tx_axi4_cipo.bresp;
- reg_bsn_monitor_v2_tx_bvalid <= reg_bsn_monitor_v2_tx_axi4_cipo.bvalid;
- reg_bsn_monitor_v2_tx_arready <= reg_bsn_monitor_v2_tx_axi4_cipo.arready;
- reg_bsn_monitor_v2_tx_rdata <= reg_bsn_monitor_v2_tx_axi4_cipo.rdata;
- reg_bsn_monitor_v2_tx_rresp <= reg_bsn_monitor_v2_tx_axi4_cipo.rresp;
- reg_bsn_monitor_v2_tx_rvalid <= reg_bsn_monitor_v2_tx_axi4_cipo.rvalid;
-
- -- reg_strobe_total_count_tx
- -- copi
- reg_strobe_total_count_tx_axi4_copi.awaddr <= reg_strobe_total_count_tx_awaddr;
- reg_strobe_total_count_tx_axi4_copi.awprot <= reg_strobe_total_count_tx_awprot;
- reg_strobe_total_count_tx_axi4_copi.awvalid <= reg_strobe_total_count_tx_awvalid;
- reg_strobe_total_count_tx_axi4_copi.wdata <= reg_strobe_total_count_tx_wdata;
- reg_strobe_total_count_tx_axi4_copi.wstrb <= reg_strobe_total_count_tx_wstrb;
- reg_strobe_total_count_tx_axi4_copi.wvalid <= reg_strobe_total_count_tx_wvalid;
- reg_strobe_total_count_tx_axi4_copi.bready <= reg_strobe_total_count_tx_bready;
- reg_strobe_total_count_tx_axi4_copi.araddr <= reg_strobe_total_count_tx_araddr;
- reg_strobe_total_count_tx_axi4_copi.arprot <= reg_strobe_total_count_tx_arprot;
- reg_strobe_total_count_tx_axi4_copi.arvalid <= reg_strobe_total_count_tx_arvalid;
- reg_strobe_total_count_tx_axi4_copi.rready <= reg_strobe_total_count_tx_rready;
- -- cipo
- reg_strobe_total_count_tx_awready <= reg_strobe_total_count_tx_axi4_cipo.awready;
- reg_strobe_total_count_tx_wready <= reg_strobe_total_count_tx_axi4_cipo.wready;
- reg_strobe_total_count_tx_bresp <= reg_strobe_total_count_tx_axi4_cipo.bresp;
- reg_strobe_total_count_tx_bvalid <= reg_strobe_total_count_tx_axi4_cipo.bvalid;
- reg_strobe_total_count_tx_arready <= reg_strobe_total_count_tx_axi4_cipo.arready;
- reg_strobe_total_count_tx_rdata <= reg_strobe_total_count_tx_axi4_cipo.rdata;
- reg_strobe_total_count_tx_rresp <= reg_strobe_total_count_tx_axi4_cipo.rresp;
- reg_strobe_total_count_tx_rvalid <= reg_strobe_total_count_tx_axi4_cipo.rvalid;
-
- -- reg_bsn_monitor_v2_rx
- -- copi
- reg_bsn_monitor_v2_rx_axi4_copi.awaddr <= reg_bsn_monitor_v2_rx_awaddr;
- reg_bsn_monitor_v2_rx_axi4_copi.awprot <= reg_bsn_monitor_v2_rx_awprot;
- reg_bsn_monitor_v2_rx_axi4_copi.awvalid <= reg_bsn_monitor_v2_rx_awvalid;
- reg_bsn_monitor_v2_rx_axi4_copi.wdata <= reg_bsn_monitor_v2_rx_wdata;
- reg_bsn_monitor_v2_rx_axi4_copi.wstrb <= reg_bsn_monitor_v2_rx_wstrb;
- reg_bsn_monitor_v2_rx_axi4_copi.wvalid <= reg_bsn_monitor_v2_rx_wvalid;
- reg_bsn_monitor_v2_rx_axi4_copi.bready <= reg_bsn_monitor_v2_rx_bready;
- reg_bsn_monitor_v2_rx_axi4_copi.araddr <= reg_bsn_monitor_v2_rx_araddr;
- reg_bsn_monitor_v2_rx_axi4_copi.arprot <= reg_bsn_monitor_v2_rx_arprot;
- reg_bsn_monitor_v2_rx_axi4_copi.arvalid <= reg_bsn_monitor_v2_rx_arvalid;
- reg_bsn_monitor_v2_rx_axi4_copi.rready <= reg_bsn_monitor_v2_rx_rready;
- -- cipo
- reg_bsn_monitor_v2_rx_awready <= reg_bsn_monitor_v2_rx_axi4_cipo.awready;
- reg_bsn_monitor_v2_rx_wready <= reg_bsn_monitor_v2_rx_axi4_cipo.wready;
- reg_bsn_monitor_v2_rx_bresp <= reg_bsn_monitor_v2_rx_axi4_cipo.bresp;
- reg_bsn_monitor_v2_rx_bvalid <= reg_bsn_monitor_v2_rx_axi4_cipo.bvalid;
- reg_bsn_monitor_v2_rx_arready <= reg_bsn_monitor_v2_rx_axi4_cipo.arready;
- reg_bsn_monitor_v2_rx_rdata <= reg_bsn_monitor_v2_rx_axi4_cipo.rdata;
- reg_bsn_monitor_v2_rx_rresp <= reg_bsn_monitor_v2_rx_axi4_cipo.rresp;
- reg_bsn_monitor_v2_rx_rvalid <= reg_bsn_monitor_v2_rx_axi4_cipo.rvalid;
-
- -- reg_strobe_total_count_rx
- -- copi
- reg_strobe_total_count_rx_axi4_copi.awaddr <= reg_strobe_total_count_rx_awaddr;
- reg_strobe_total_count_rx_axi4_copi.awprot <= reg_strobe_total_count_rx_awprot;
- reg_strobe_total_count_rx_axi4_copi.awvalid <= reg_strobe_total_count_rx_awvalid;
- reg_strobe_total_count_rx_axi4_copi.wdata <= reg_strobe_total_count_rx_wdata;
- reg_strobe_total_count_rx_axi4_copi.wstrb <= reg_strobe_total_count_rx_wstrb;
- reg_strobe_total_count_rx_axi4_copi.wvalid <= reg_strobe_total_count_rx_wvalid;
- reg_strobe_total_count_rx_axi4_copi.bready <= reg_strobe_total_count_rx_bready;
- reg_strobe_total_count_rx_axi4_copi.araddr <= reg_strobe_total_count_rx_araddr;
- reg_strobe_total_count_rx_axi4_copi.arprot <= reg_strobe_total_count_rx_arprot;
- reg_strobe_total_count_rx_axi4_copi.arvalid <= reg_strobe_total_count_rx_arvalid;
- reg_strobe_total_count_rx_axi4_copi.rready <= reg_strobe_total_count_rx_rready;
- -- cipo
- reg_strobe_total_count_rx_awready <= reg_strobe_total_count_rx_axi4_cipo.awready;
- reg_strobe_total_count_rx_wready <= reg_strobe_total_count_rx_axi4_cipo.wready;
- reg_strobe_total_count_rx_bresp <= reg_strobe_total_count_rx_axi4_cipo.bresp;
- reg_strobe_total_count_rx_bvalid <= reg_strobe_total_count_rx_axi4_cipo.bvalid;
- reg_strobe_total_count_rx_arready <= reg_strobe_total_count_rx_axi4_cipo.arready;
- reg_strobe_total_count_rx_rdata <= reg_strobe_total_count_rx_axi4_cipo.rdata;
- reg_strobe_total_count_rx_rresp <= reg_strobe_total_count_rx_axi4_cipo.rresp;
- reg_strobe_total_count_rx_rvalid <= reg_strobe_total_count_rx_axi4_cipo.rvalid;
-
-END str;
+-------------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Author: R. van der Walle
+-- Purpose: Provide AXI4-Stream and AXI4-Lite interface for eth_tester.vhd such
+-- that it can be used to create a Vivado IP block.
+-- Description:
+-- . The eth_tester_axi4_wrapper uses axi4_stream_dp_bridge to convert the dp
+-- sosi/siso interfaces of the eth_tester into AXI4-Stream interfaces.
+-- Similarly, axi4_lite_mm_bridge is used to convert the mem copi/cipo
+-- interfaces into AXI4_Lite interfaces.
+-- . In order for this component to be suitable as a Vivado IP, the ports are
+-- exclusively STD_LOGIC(_VECTOR) where the widths are hard-coded as demanded
+-- by the Vivado IP creator (only supports VHDL-93).
+
+library IEEE, common_lib, dp_lib, diag_lib, axi4_lib;
+use IEEE.std_logic_1164.all;
+use common_lib.common_pkg.all;
+use common_lib.common_mem_pkg.all;
+use common_lib.common_network_layers_pkg.all;
+use dp_lib.dp_stream_pkg.all;
+use dp_lib.dp_components_pkg.all;
+use diag_lib.diag_pkg.all;
+use axi4_lib.axi4_stream_pkg.all;
+use axi4_lib.axi4_lite_pkg.all;
+use work.eth_pkg.all;
+use work.eth_tester_pkg.all;
+
+entity eth_tester_axi4_wrapper is
+ port (
+ -- Clocks and reset
+ mm_clk : in std_logic;
+ st_clk : in std_logic;
+ st_pps : in std_logic;
+ aresetn : in std_logic;
+ -- UDP transmit interface
+ eth_src_mac : in std_logic_vector(6 * 8 - 1 downto 0);
+ ip_src_addr : in std_logic_vector(4 * 8 - 1 downto 0);
+ udp_src_port : in std_logic_vector(2 * 8 - 1 downto 0);
+
+ tx_fifo_rd_emp_arr : out std_logic_vector(0 downto 0);
+
+ -- tx_udp
+ -- Source In and Sink Out
+ tx_udp_tready : in std_logic;
+
+ -- Source Out and Sink In
+ tx_udp_tvalid : out std_logic;
+ tx_udp_tdata : out std_logic_vector(512 - 1 downto 0);
+ tx_udp_tstrb : out std_logic_vector(512 / 8 - 1 downto 0);
+ tx_udp_tkeep : out std_logic_vector(512 / 8 - 1 downto 0);
+ tx_udp_tlast : out std_logic;
+ tx_udp_tid : out std_logic_vector(4 - 1 downto 0);
+ tx_udp_tdest : out std_logic_vector(32 - 1 downto 0);
+ tx_udp_tuser : out std_logic_vector(70 - 1 downto 0);
+
+ -- rx_udp
+ -- Source In and Sink Out
+ rx_udp_tready : out std_logic;
+
+ -- Source Out and Sink In
+ rx_udp_tvalid : in std_logic;
+ rx_udp_tdata : in std_logic_vector(512 - 1 downto 0);
+ rx_udp_tstrb : in std_logic_vector(512 / 8 - 1 downto 0);
+ rx_udp_tkeep : in std_logic_vector(512 / 8 - 1 downto 0);
+ rx_udp_tlast : in std_logic;
+ rx_udp_tid : in std_logic_vector(4 - 1 downto 0);
+ rx_udp_tdest : in std_logic_vector(32 - 1 downto 0);
+ rx_udp_tuser : in std_logic_vector(70 - 1 downto 0);
+
+ -- reg_bg_ctrl
+ -- copi
+ reg_bg_ctrl_awaddr : in std_logic_vector(32 - 1 downto 0);
+ reg_bg_ctrl_awprot : in std_logic_vector(3 - 1 downto 0);
+ reg_bg_ctrl_awvalid : in std_logic;
+ reg_bg_ctrl_wdata : in std_logic_vector(32 - 1 downto 0);
+ reg_bg_ctrl_wstrb : in std_logic_vector((32 / 8) - 1 downto 0);
+ reg_bg_ctrl_wvalid : in std_logic;
+ reg_bg_ctrl_bready : in std_logic;
+ reg_bg_ctrl_araddr : in std_logic_vector(32 - 1 downto 0);
+ reg_bg_ctrl_arprot : in std_logic_vector(3 - 1 downto 0);
+ reg_bg_ctrl_arvalid : in std_logic;
+ reg_bg_ctrl_rready : in std_logic;
+ -- cipo
+ reg_bg_ctrl_awready : out std_logic;
+ reg_bg_ctrl_wready : out std_logic;
+ reg_bg_ctrl_bresp : out std_logic_vector(2 - 1 downto 0);
+ reg_bg_ctrl_bvalid : out std_logic;
+ reg_bg_ctrl_arready : out std_logic;
+ reg_bg_ctrl_rdata : out std_logic_vector(32 - 1 downto 0);
+ reg_bg_ctrl_rresp : out std_logic_vector(2 - 1 downto 0);
+ reg_bg_ctrl_rvalid : out std_logic;
+
+ -- reg_hdr_dat
+ -- copi
+ reg_hdr_dat_awaddr : in std_logic_vector(32 - 1 downto 0);
+ reg_hdr_dat_awprot : in std_logic_vector(3 - 1 downto 0);
+ reg_hdr_dat_awvalid : in std_logic;
+ reg_hdr_dat_wdata : in std_logic_vector(32 - 1 downto 0);
+ reg_hdr_dat_wstrb : in std_logic_vector((32 / 8) - 1 downto 0);
+ reg_hdr_dat_wvalid : in std_logic;
+ reg_hdr_dat_bready : in std_logic;
+ reg_hdr_dat_araddr : in std_logic_vector(32 - 1 downto 0);
+ reg_hdr_dat_arprot : in std_logic_vector(3 - 1 downto 0);
+ reg_hdr_dat_arvalid : in std_logic;
+ reg_hdr_dat_rready : in std_logic;
+ -- cipo
+ reg_hdr_dat_awready : out std_logic;
+ reg_hdr_dat_wready : out std_logic;
+ reg_hdr_dat_bresp : out std_logic_vector(2 - 1 downto 0);
+ reg_hdr_dat_bvalid : out std_logic;
+ reg_hdr_dat_arready : out std_logic;
+ reg_hdr_dat_rdata : out std_logic_vector(32 - 1 downto 0);
+ reg_hdr_dat_rresp : out std_logic_vector(2 - 1 downto 0);
+ reg_hdr_dat_rvalid : out std_logic;
+
+ -- reg_bsn_monitor_v2_tx
+ -- copi
+ reg_bsn_monitor_v2_tx_awaddr : in std_logic_vector(32 - 1 downto 0);
+ reg_bsn_monitor_v2_tx_awprot : in std_logic_vector(3 - 1 downto 0);
+ reg_bsn_monitor_v2_tx_awvalid : in std_logic;
+ reg_bsn_monitor_v2_tx_wdata : in std_logic_vector(32 - 1 downto 0);
+ reg_bsn_monitor_v2_tx_wstrb : in std_logic_vector((32 / 8) - 1 downto 0);
+ reg_bsn_monitor_v2_tx_wvalid : in std_logic;
+ reg_bsn_monitor_v2_tx_bready : in std_logic;
+ reg_bsn_monitor_v2_tx_araddr : in std_logic_vector(32 - 1 downto 0);
+ reg_bsn_monitor_v2_tx_arprot : in std_logic_vector(3 - 1 downto 0);
+ reg_bsn_monitor_v2_tx_arvalid : in std_logic;
+ reg_bsn_monitor_v2_tx_rready : in std_logic;
+ -- cipo
+ reg_bsn_monitor_v2_tx_awready : out std_logic;
+ reg_bsn_monitor_v2_tx_wready : out std_logic;
+ reg_bsn_monitor_v2_tx_bresp : out std_logic_vector(2 - 1 downto 0);
+ reg_bsn_monitor_v2_tx_bvalid : out std_logic;
+ reg_bsn_monitor_v2_tx_arready : out std_logic;
+ reg_bsn_monitor_v2_tx_rdata : out std_logic_vector(32 - 1 downto 0);
+ reg_bsn_monitor_v2_tx_rresp : out std_logic_vector(2 - 1 downto 0);
+ reg_bsn_monitor_v2_tx_rvalid : out std_logic;
+
+ -- reg_strobe_total_count_tx
+ -- copi
+ reg_strobe_total_count_tx_awaddr : in std_logic_vector(32 - 1 downto 0);
+ reg_strobe_total_count_tx_awprot : in std_logic_vector(3 - 1 downto 0);
+ reg_strobe_total_count_tx_awvalid : in std_logic;
+ reg_strobe_total_count_tx_wdata : in std_logic_vector(32 - 1 downto 0);
+ reg_strobe_total_count_tx_wstrb : in std_logic_vector((32 / 8) - 1 downto 0);
+ reg_strobe_total_count_tx_wvalid : in std_logic;
+ reg_strobe_total_count_tx_bready : in std_logic;
+ reg_strobe_total_count_tx_araddr : in std_logic_vector(32 - 1 downto 0);
+ reg_strobe_total_count_tx_arprot : in std_logic_vector(3 - 1 downto 0);
+ reg_strobe_total_count_tx_arvalid : in std_logic;
+ reg_strobe_total_count_tx_rready : in std_logic;
+ -- cipo
+ reg_strobe_total_count_tx_awready : out std_logic;
+ reg_strobe_total_count_tx_wready : out std_logic;
+ reg_strobe_total_count_tx_bresp : out std_logic_vector(2 - 1 downto 0);
+ reg_strobe_total_count_tx_bvalid : out std_logic;
+ reg_strobe_total_count_tx_arready : out std_logic;
+ reg_strobe_total_count_tx_rdata : out std_logic_vector(32 - 1 downto 0);
+ reg_strobe_total_count_tx_rresp : out std_logic_vector(2 - 1 downto 0);
+ reg_strobe_total_count_tx_rvalid : out std_logic;
+
+ -- reg_bsn_monitor_v2_rx
+ -- copi
+ reg_bsn_monitor_v2_rx_awaddr : in std_logic_vector(32 - 1 downto 0);
+ reg_bsn_monitor_v2_rx_awprot : in std_logic_vector(3 - 1 downto 0);
+ reg_bsn_monitor_v2_rx_awvalid : in std_logic;
+ reg_bsn_monitor_v2_rx_wdata : in std_logic_vector(32 - 1 downto 0);
+ reg_bsn_monitor_v2_rx_wstrb : in std_logic_vector((32 / 8) - 1 downto 0);
+ reg_bsn_monitor_v2_rx_wvalid : in std_logic;
+ reg_bsn_monitor_v2_rx_bready : in std_logic;
+ reg_bsn_monitor_v2_rx_araddr : in std_logic_vector(32 - 1 downto 0);
+ reg_bsn_monitor_v2_rx_arprot : in std_logic_vector(3 - 1 downto 0);
+ reg_bsn_monitor_v2_rx_arvalid : in std_logic;
+ reg_bsn_monitor_v2_rx_rready : in std_logic;
+ -- cipo
+ reg_bsn_monitor_v2_rx_awready : out std_logic;
+ reg_bsn_monitor_v2_rx_wready : out std_logic;
+ reg_bsn_monitor_v2_rx_bresp : out std_logic_vector(2 - 1 downto 0);
+ reg_bsn_monitor_v2_rx_bvalid : out std_logic;
+ reg_bsn_monitor_v2_rx_arready : out std_logic;
+ reg_bsn_monitor_v2_rx_rdata : out std_logic_vector(32 - 1 downto 0);
+ reg_bsn_monitor_v2_rx_rresp : out std_logic_vector(2 - 1 downto 0);
+ reg_bsn_monitor_v2_rx_rvalid : out std_logic;
+
+ -- reg_strobe_total_count_rx
+ -- copi
+ reg_strobe_total_count_rx_awaddr : in std_logic_vector(32 - 1 downto 0);
+ reg_strobe_total_count_rx_awprot : in std_logic_vector(3 - 1 downto 0);
+ reg_strobe_total_count_rx_awvalid : in std_logic;
+ reg_strobe_total_count_rx_wdata : in std_logic_vector(32 - 1 downto 0);
+ reg_strobe_total_count_rx_wstrb : in std_logic_vector((32 / 8) - 1 downto 0);
+ reg_strobe_total_count_rx_wvalid : in std_logic;
+ reg_strobe_total_count_rx_bready : in std_logic;
+ reg_strobe_total_count_rx_araddr : in std_logic_vector(32 - 1 downto 0);
+ reg_strobe_total_count_rx_arprot : in std_logic_vector(3 - 1 downto 0);
+ reg_strobe_total_count_rx_arvalid : in std_logic;
+ reg_strobe_total_count_rx_rready : in std_logic;
+ -- cipo
+ reg_strobe_total_count_rx_awready : out std_logic;
+ reg_strobe_total_count_rx_wready : out std_logic;
+ reg_strobe_total_count_rx_bresp : out std_logic_vector(2 - 1 downto 0);
+ reg_strobe_total_count_rx_bvalid : out std_logic;
+ reg_strobe_total_count_rx_arready : out std_logic;
+ reg_strobe_total_count_rx_rdata : out std_logic_vector(32 - 1 downto 0);
+ reg_strobe_total_count_rx_rresp : out std_logic_vector(2 - 1 downto 0);
+ reg_strobe_total_count_rx_rvalid : out std_logic
+
+ );
+end eth_tester_axi4_wrapper;
+
+
+architecture str of eth_tester_axi4_wrapper is
+ signal rx_udp_sosi_arr : t_dp_sosi_arr(0 downto 0) := (others => c_dp_sosi_rst);
+ signal rx_udp_siso_arr : t_dp_siso_arr(0 downto 0) := (others => c_dp_siso_rdy);
+ signal tx_udp_sosi_arr : t_dp_sosi_arr(0 downto 0) := (others => c_dp_sosi_rst);
+ signal tx_udp_siso_arr : t_dp_siso_arr(0 downto 0) := (others => c_dp_siso_rdy);
+
+ signal rx_udp_axi4_sosi : t_axi4_sosi := c_axi4_sosi_rst;
+ signal rx_udp_axi4_siso : t_axi4_siso := c_axi4_siso_rst;
+ signal tx_udp_axi4_sosi : t_axi4_sosi := c_axi4_sosi_rst;
+ signal tx_udp_axi4_siso : t_axi4_siso := c_axi4_siso_rst;
+
+ signal reg_bg_ctrl_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_bg_ctrl_cipo : t_mem_cipo;
+ signal reg_hdr_dat_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_hdr_dat_cipo : t_mem_cipo;
+ signal reg_bsn_monitor_v2_tx_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_bsn_monitor_v2_tx_cipo : t_mem_cipo;
+ signal reg_strobe_total_count_tx_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_strobe_total_count_tx_cipo : t_mem_cipo;
+
+ signal reg_bsn_monitor_v2_rx_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_bsn_monitor_v2_rx_cipo : t_mem_cipo;
+ signal reg_strobe_total_count_rx_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_strobe_total_count_rx_cipo : t_mem_cipo;
+
+
+ signal reg_bg_ctrl_axi4_copi : t_axi4_lite_copi := c_axi4_lite_copi_rst;
+ signal reg_bg_ctrl_axi4_cipo : t_axi4_lite_cipo;
+ signal reg_hdr_dat_axi4_copi : t_axi4_lite_copi := c_axi4_lite_copi_rst;
+ signal reg_hdr_dat_axi4_cipo : t_axi4_lite_cipo;
+ signal reg_bsn_monitor_v2_tx_axi4_copi : t_axi4_lite_copi := c_axi4_lite_copi_rst;
+ signal reg_bsn_monitor_v2_tx_axi4_cipo : t_axi4_lite_cipo;
+ signal reg_strobe_total_count_tx_axi4_copi : t_axi4_lite_copi := c_axi4_lite_copi_rst;
+ signal reg_strobe_total_count_tx_axi4_cipo : t_axi4_lite_cipo;
+
+ signal reg_bsn_monitor_v2_rx_axi4_copi : t_axi4_lite_copi := c_axi4_lite_copi_rst;
+ signal reg_bsn_monitor_v2_rx_axi4_cipo : t_axi4_lite_cipo;
+ signal reg_strobe_total_count_rx_axi4_copi : t_axi4_lite_copi := c_axi4_lite_copi_rst;
+ signal reg_strobe_total_count_rx_axi4_cipo : t_axi4_lite_cipo;
+
+ signal mm_rst : std_logic := '0';
+ signal st_rst : std_logic := '0';
+
+begin
+
+ u_eth_tester : entity work.eth_tester
+ generic map (
+ g_remove_crc => FALSE
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
+ st_pps => st_pps,
+
+ -- UDP transmit interface
+ eth_src_mac => eth_src_mac,
+ ip_src_addr => ip_src_addr,
+ udp_src_port => udp_src_port,
+
+ tx_fifo_rd_emp_arr => tx_fifo_rd_emp_arr,
+
+ tx_udp_sosi_arr => tx_udp_sosi_arr,
+ tx_udp_siso_arr => tx_udp_siso_arr,
+
+ -- UDP receive interface
+ rx_udp_sosi_arr => rx_udp_sosi_arr,
+
+ -- Memory Mapped Slaves (one per stream)
+ reg_bg_ctrl_copi => reg_bg_ctrl_copi,
+ reg_bg_ctrl_cipo => reg_bg_ctrl_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_copi,
+ reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_cipo,
+ reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_copi,
+ reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_cipo,
+
+ reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_copi,
+ reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_cipo,
+ reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_copi,
+ reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_cipo
+ );
+
+ -- DP to AXI4
+ u_axi4_tx_udp : entity axi4_lib.axi4_stream_dp_bridge
+ generic map (
+ g_axi4_rl => 0,
+ g_dp_rl => 1,
+ g_active_low_rst => TRUE
+ )
+ port map (
+ in_clk => st_clk,
+ in_rst => aresetn,
+
+ dp_rst => st_rst,
+
+ dp_in_sosi => tx_udp_sosi_arr(0),
+ dp_in_siso => tx_udp_siso_arr(0),
+
+ axi4_out_sosi => tx_udp_axi4_sosi,
+ axi4_out_siso => tx_udp_axi4_siso
+ );
+
+ u_axi4_rx_udp : entity axi4_lib.axi4_stream_dp_bridge
+ generic map (
+ g_axi4_rl => 0,
+ g_dp_rl => 1,
+ g_active_low_rst => TRUE
+ )
+ port map (
+ in_clk => st_clk,
+ in_rst => aresetn,
+
+ axi4_in_sosi => rx_udp_axi4_sosi,
+ axi4_in_siso => rx_udp_axi4_siso,
+
+ dp_out_sosi => rx_udp_sosi_arr(0),
+ dp_out_siso => rx_udp_siso_arr(0)
+ );
+
+ -- AXI4 to MM
+ u_axi4_reg_bg_ctrl : entity axi4_lib.axi4_lite_mm_bridge
+ generic map (
+ g_active_low_rst => TRUE
+ )
+ port map (
+ in_clk => mm_clk,
+ in_rst => aresetn,
+
+ mm_rst => mm_rst,
+
+ axi4_in_copi => reg_bg_ctrl_axi4_copi,
+ axi4_in_cipo => reg_bg_ctrl_axi4_cipo,
+
+ mm_out_copi => reg_bg_ctrl_copi,
+ mm_out_cipo => reg_bg_ctrl_cipo
+ );
+
+ u_axi4_reg_hdr_dat : entity axi4_lib.axi4_lite_mm_bridge
+ generic map (
+ g_active_low_rst => TRUE
+ )
+ port map (
+ in_clk => mm_clk,
+ in_rst => aresetn,
+
+ axi4_in_copi => reg_hdr_dat_axi4_copi,
+ axi4_in_cipo => reg_hdr_dat_axi4_cipo,
+
+ mm_out_copi => reg_hdr_dat_copi,
+ mm_out_cipo => reg_hdr_dat_cipo
+ );
+
+
+ u_axi4_reg_bsn_monitor_v2_tx : entity axi4_lib.axi4_lite_mm_bridge
+ generic map (
+ g_active_low_rst => TRUE
+ )
+ port map (
+ in_clk => mm_clk,
+ in_rst => aresetn,
+
+ axi4_in_copi => reg_bsn_monitor_v2_tx_axi4_copi,
+ axi4_in_cipo => reg_bsn_monitor_v2_tx_axi4_cipo,
+
+ mm_out_copi => reg_bsn_monitor_v2_tx_copi,
+ mm_out_cipo => reg_bsn_monitor_v2_tx_cipo
+ );
+
+
+ u_axi4_reg_strobe_total_count_tx : entity axi4_lib.axi4_lite_mm_bridge
+ generic map (
+ g_active_low_rst => TRUE
+ )
+ port map (
+ in_clk => mm_clk,
+ in_rst => aresetn,
+
+ axi4_in_copi => reg_strobe_total_count_tx_axi4_copi,
+ axi4_in_cipo => reg_strobe_total_count_tx_axi4_cipo,
+
+ mm_out_copi => reg_strobe_total_count_tx_copi,
+ mm_out_cipo => reg_strobe_total_count_tx_cipo
+ );
+
+
+ u_axi4_reg_bsn_monitor_v2_rx : entity axi4_lib.axi4_lite_mm_bridge
+ generic map (
+ g_active_low_rst => TRUE
+ )
+ port map (
+ in_clk => mm_clk,
+ in_rst => aresetn,
+
+ axi4_in_copi => reg_bsn_monitor_v2_rx_axi4_copi,
+ axi4_in_cipo => reg_bsn_monitor_v2_rx_axi4_cipo,
+
+ mm_out_copi => reg_bsn_monitor_v2_rx_copi,
+ mm_out_cipo => reg_bsn_monitor_v2_rx_cipo
+ );
+
+ u_axi4_reg_strobe_total_count_rx : entity axi4_lib.axi4_lite_mm_bridge
+ generic map (
+ g_active_low_rst => TRUE
+ )
+ port map (
+ in_clk => mm_clk,
+ in_rst => aresetn,
+
+ axi4_in_copi => reg_strobe_total_count_rx_axi4_copi,
+ axi4_in_cipo => reg_strobe_total_count_rx_axi4_cipo,
+
+ mm_out_copi => reg_strobe_total_count_rx_copi,
+ mm_out_cipo => reg_strobe_total_count_rx_cipo
+ );
+
+ -- Wire Records to IN/OUT ports.
+
+ -- tx_udp
+ tx_udp_axi4_siso.tready <= tx_udp_tready;
+
+ tx_udp_tvalid <= tx_udp_axi4_sosi.tvalid;
+ tx_udp_tdata <= tx_udp_axi4_sosi.tdata;
+ tx_udp_tstrb <= tx_udp_axi4_sosi.tstrb;
+ tx_udp_tkeep <= tx_udp_axi4_sosi.tkeep;
+ tx_udp_tlast <= tx_udp_axi4_sosi.tlast;
+ tx_udp_tid <= tx_udp_axi4_sosi.tid;
+ tx_udp_tdest <= tx_udp_axi4_sosi.tdest;
+ tx_udp_tuser <= tx_udp_axi4_sosi.tuser;
+
+ -- rx_udp
+ rx_udp_tready <= rx_udp_axi4_siso.tready;
+
+ rx_udp_axi4_sosi.tvalid <= rx_udp_tvalid;
+ rx_udp_axi4_sosi.tdata <= rx_udp_tdata;
+ rx_udp_axi4_sosi.tstrb <= rx_udp_tstrb;
+ rx_udp_axi4_sosi.tkeep <= rx_udp_tkeep;
+ rx_udp_axi4_sosi.tlast <= rx_udp_tlast;
+ rx_udp_axi4_sosi.tid <= rx_udp_tid;
+ rx_udp_axi4_sosi.tdest <= rx_udp_tdest;
+ rx_udp_axi4_sosi.tuser <= rx_udp_tuser;
+
+ -- reg_bg_ctrl
+ -- copi
+ reg_bg_ctrl_axi4_copi.awaddr <= reg_bg_ctrl_awaddr;
+ reg_bg_ctrl_axi4_copi.awprot <= reg_bg_ctrl_awprot;
+ reg_bg_ctrl_axi4_copi.awvalid <= reg_bg_ctrl_awvalid;
+ reg_bg_ctrl_axi4_copi.wdata <= reg_bg_ctrl_wdata;
+ reg_bg_ctrl_axi4_copi.wstrb <= reg_bg_ctrl_wstrb;
+ reg_bg_ctrl_axi4_copi.wvalid <= reg_bg_ctrl_wvalid;
+ reg_bg_ctrl_axi4_copi.bready <= reg_bg_ctrl_bready;
+ reg_bg_ctrl_axi4_copi.araddr <= reg_bg_ctrl_araddr;
+ reg_bg_ctrl_axi4_copi.arprot <= reg_bg_ctrl_arprot;
+ reg_bg_ctrl_axi4_copi.arvalid <= reg_bg_ctrl_arvalid;
+ reg_bg_ctrl_axi4_copi.rready <= reg_bg_ctrl_rready;
+ -- cipo
+ reg_bg_ctrl_awready <= reg_bg_ctrl_axi4_cipo.awready;
+ reg_bg_ctrl_wready <= reg_bg_ctrl_axi4_cipo.wready;
+ reg_bg_ctrl_bresp <= reg_bg_ctrl_axi4_cipo.bresp;
+ reg_bg_ctrl_bvalid <= reg_bg_ctrl_axi4_cipo.bvalid;
+ reg_bg_ctrl_arready <= reg_bg_ctrl_axi4_cipo.arready;
+ reg_bg_ctrl_rdata <= reg_bg_ctrl_axi4_cipo.rdata;
+ reg_bg_ctrl_rresp <= reg_bg_ctrl_axi4_cipo.rresp;
+ reg_bg_ctrl_rvalid <= reg_bg_ctrl_axi4_cipo.rvalid;
+
+ -- reg_hdr_dat
+ -- copi
+ reg_hdr_dat_axi4_copi.awaddr <= reg_hdr_dat_awaddr;
+ reg_hdr_dat_axi4_copi.awprot <= reg_hdr_dat_awprot;
+ reg_hdr_dat_axi4_copi.awvalid <= reg_hdr_dat_awvalid;
+ reg_hdr_dat_axi4_copi.wdata <= reg_hdr_dat_wdata;
+ reg_hdr_dat_axi4_copi.wstrb <= reg_hdr_dat_wstrb;
+ reg_hdr_dat_axi4_copi.wvalid <= reg_hdr_dat_wvalid;
+ reg_hdr_dat_axi4_copi.bready <= reg_hdr_dat_bready;
+ reg_hdr_dat_axi4_copi.araddr <= reg_hdr_dat_araddr;
+ reg_hdr_dat_axi4_copi.arprot <= reg_hdr_dat_arprot;
+ reg_hdr_dat_axi4_copi.arvalid <= reg_hdr_dat_arvalid;
+ reg_hdr_dat_axi4_copi.rready <= reg_hdr_dat_rready;
+ -- cipo
+ reg_hdr_dat_awready <= reg_hdr_dat_axi4_cipo.awready;
+ reg_hdr_dat_wready <= reg_hdr_dat_axi4_cipo.wready;
+ reg_hdr_dat_bresp <= reg_hdr_dat_axi4_cipo.bresp;
+ reg_hdr_dat_bvalid <= reg_hdr_dat_axi4_cipo.bvalid;
+ reg_hdr_dat_arready <= reg_hdr_dat_axi4_cipo.arready;
+ reg_hdr_dat_rdata <= reg_hdr_dat_axi4_cipo.rdata;
+ reg_hdr_dat_rresp <= reg_hdr_dat_axi4_cipo.rresp;
+ reg_hdr_dat_rvalid <= reg_hdr_dat_axi4_cipo.rvalid;
+
+ -- reg_bsn_monitor_v2_tx
+ -- copi
+ reg_bsn_monitor_v2_tx_axi4_copi.awaddr <= reg_bsn_monitor_v2_tx_awaddr;
+ reg_bsn_monitor_v2_tx_axi4_copi.awprot <= reg_bsn_monitor_v2_tx_awprot;
+ reg_bsn_monitor_v2_tx_axi4_copi.awvalid <= reg_bsn_monitor_v2_tx_awvalid;
+ reg_bsn_monitor_v2_tx_axi4_copi.wdata <= reg_bsn_monitor_v2_tx_wdata;
+ reg_bsn_monitor_v2_tx_axi4_copi.wstrb <= reg_bsn_monitor_v2_tx_wstrb;
+ reg_bsn_monitor_v2_tx_axi4_copi.wvalid <= reg_bsn_monitor_v2_tx_wvalid;
+ reg_bsn_monitor_v2_tx_axi4_copi.bready <= reg_bsn_monitor_v2_tx_bready;
+ reg_bsn_monitor_v2_tx_axi4_copi.araddr <= reg_bsn_monitor_v2_tx_araddr;
+ reg_bsn_monitor_v2_tx_axi4_copi.arprot <= reg_bsn_monitor_v2_tx_arprot;
+ reg_bsn_monitor_v2_tx_axi4_copi.arvalid <= reg_bsn_monitor_v2_tx_arvalid;
+ reg_bsn_monitor_v2_tx_axi4_copi.rready <= reg_bsn_monitor_v2_tx_rready;
+ -- cipo
+ reg_bsn_monitor_v2_tx_awready <= reg_bsn_monitor_v2_tx_axi4_cipo.awready;
+ reg_bsn_monitor_v2_tx_wready <= reg_bsn_monitor_v2_tx_axi4_cipo.wready;
+ reg_bsn_monitor_v2_tx_bresp <= reg_bsn_monitor_v2_tx_axi4_cipo.bresp;
+ reg_bsn_monitor_v2_tx_bvalid <= reg_bsn_monitor_v2_tx_axi4_cipo.bvalid;
+ reg_bsn_monitor_v2_tx_arready <= reg_bsn_monitor_v2_tx_axi4_cipo.arready;
+ reg_bsn_monitor_v2_tx_rdata <= reg_bsn_monitor_v2_tx_axi4_cipo.rdata;
+ reg_bsn_monitor_v2_tx_rresp <= reg_bsn_monitor_v2_tx_axi4_cipo.rresp;
+ reg_bsn_monitor_v2_tx_rvalid <= reg_bsn_monitor_v2_tx_axi4_cipo.rvalid;
+
+ -- reg_strobe_total_count_tx
+ -- copi
+ reg_strobe_total_count_tx_axi4_copi.awaddr <= reg_strobe_total_count_tx_awaddr;
+ reg_strobe_total_count_tx_axi4_copi.awprot <= reg_strobe_total_count_tx_awprot;
+ reg_strobe_total_count_tx_axi4_copi.awvalid <= reg_strobe_total_count_tx_awvalid;
+ reg_strobe_total_count_tx_axi4_copi.wdata <= reg_strobe_total_count_tx_wdata;
+ reg_strobe_total_count_tx_axi4_copi.wstrb <= reg_strobe_total_count_tx_wstrb;
+ reg_strobe_total_count_tx_axi4_copi.wvalid <= reg_strobe_total_count_tx_wvalid;
+ reg_strobe_total_count_tx_axi4_copi.bready <= reg_strobe_total_count_tx_bready;
+ reg_strobe_total_count_tx_axi4_copi.araddr <= reg_strobe_total_count_tx_araddr;
+ reg_strobe_total_count_tx_axi4_copi.arprot <= reg_strobe_total_count_tx_arprot;
+ reg_strobe_total_count_tx_axi4_copi.arvalid <= reg_strobe_total_count_tx_arvalid;
+ reg_strobe_total_count_tx_axi4_copi.rready <= reg_strobe_total_count_tx_rready;
+ -- cipo
+ reg_strobe_total_count_tx_awready <= reg_strobe_total_count_tx_axi4_cipo.awready;
+ reg_strobe_total_count_tx_wready <= reg_strobe_total_count_tx_axi4_cipo.wready;
+ reg_strobe_total_count_tx_bresp <= reg_strobe_total_count_tx_axi4_cipo.bresp;
+ reg_strobe_total_count_tx_bvalid <= reg_strobe_total_count_tx_axi4_cipo.bvalid;
+ reg_strobe_total_count_tx_arready <= reg_strobe_total_count_tx_axi4_cipo.arready;
+ reg_strobe_total_count_tx_rdata <= reg_strobe_total_count_tx_axi4_cipo.rdata;
+ reg_strobe_total_count_tx_rresp <= reg_strobe_total_count_tx_axi4_cipo.rresp;
+ reg_strobe_total_count_tx_rvalid <= reg_strobe_total_count_tx_axi4_cipo.rvalid;
+
+ -- reg_bsn_monitor_v2_rx
+ -- copi
+ reg_bsn_monitor_v2_rx_axi4_copi.awaddr <= reg_bsn_monitor_v2_rx_awaddr;
+ reg_bsn_monitor_v2_rx_axi4_copi.awprot <= reg_bsn_monitor_v2_rx_awprot;
+ reg_bsn_monitor_v2_rx_axi4_copi.awvalid <= reg_bsn_monitor_v2_rx_awvalid;
+ reg_bsn_monitor_v2_rx_axi4_copi.wdata <= reg_bsn_monitor_v2_rx_wdata;
+ reg_bsn_monitor_v2_rx_axi4_copi.wstrb <= reg_bsn_monitor_v2_rx_wstrb;
+ reg_bsn_monitor_v2_rx_axi4_copi.wvalid <= reg_bsn_monitor_v2_rx_wvalid;
+ reg_bsn_monitor_v2_rx_axi4_copi.bready <= reg_bsn_monitor_v2_rx_bready;
+ reg_bsn_monitor_v2_rx_axi4_copi.araddr <= reg_bsn_monitor_v2_rx_araddr;
+ reg_bsn_monitor_v2_rx_axi4_copi.arprot <= reg_bsn_monitor_v2_rx_arprot;
+ reg_bsn_monitor_v2_rx_axi4_copi.arvalid <= reg_bsn_monitor_v2_rx_arvalid;
+ reg_bsn_monitor_v2_rx_axi4_copi.rready <= reg_bsn_monitor_v2_rx_rready;
+ -- cipo
+ reg_bsn_monitor_v2_rx_awready <= reg_bsn_monitor_v2_rx_axi4_cipo.awready;
+ reg_bsn_monitor_v2_rx_wready <= reg_bsn_monitor_v2_rx_axi4_cipo.wready;
+ reg_bsn_monitor_v2_rx_bresp <= reg_bsn_monitor_v2_rx_axi4_cipo.bresp;
+ reg_bsn_monitor_v2_rx_bvalid <= reg_bsn_monitor_v2_rx_axi4_cipo.bvalid;
+ reg_bsn_monitor_v2_rx_arready <= reg_bsn_monitor_v2_rx_axi4_cipo.arready;
+ reg_bsn_monitor_v2_rx_rdata <= reg_bsn_monitor_v2_rx_axi4_cipo.rdata;
+ reg_bsn_monitor_v2_rx_rresp <= reg_bsn_monitor_v2_rx_axi4_cipo.rresp;
+ reg_bsn_monitor_v2_rx_rvalid <= reg_bsn_monitor_v2_rx_axi4_cipo.rvalid;
+
+ -- reg_strobe_total_count_rx
+ -- copi
+ reg_strobe_total_count_rx_axi4_copi.awaddr <= reg_strobe_total_count_rx_awaddr;
+ reg_strobe_total_count_rx_axi4_copi.awprot <= reg_strobe_total_count_rx_awprot;
+ reg_strobe_total_count_rx_axi4_copi.awvalid <= reg_strobe_total_count_rx_awvalid;
+ reg_strobe_total_count_rx_axi4_copi.wdata <= reg_strobe_total_count_rx_wdata;
+ reg_strobe_total_count_rx_axi4_copi.wstrb <= reg_strobe_total_count_rx_wstrb;
+ reg_strobe_total_count_rx_axi4_copi.wvalid <= reg_strobe_total_count_rx_wvalid;
+ reg_strobe_total_count_rx_axi4_copi.bready <= reg_strobe_total_count_rx_bready;
+ reg_strobe_total_count_rx_axi4_copi.araddr <= reg_strobe_total_count_rx_araddr;
+ reg_strobe_total_count_rx_axi4_copi.arprot <= reg_strobe_total_count_rx_arprot;
+ reg_strobe_total_count_rx_axi4_copi.arvalid <= reg_strobe_total_count_rx_arvalid;
+ reg_strobe_total_count_rx_axi4_copi.rready <= reg_strobe_total_count_rx_rready;
+ -- cipo
+ reg_strobe_total_count_rx_awready <= reg_strobe_total_count_rx_axi4_cipo.awready;
+ reg_strobe_total_count_rx_wready <= reg_strobe_total_count_rx_axi4_cipo.wready;
+ reg_strobe_total_count_rx_bresp <= reg_strobe_total_count_rx_axi4_cipo.bresp;
+ reg_strobe_total_count_rx_bvalid <= reg_strobe_total_count_rx_axi4_cipo.bvalid;
+ reg_strobe_total_count_rx_arready <= reg_strobe_total_count_rx_axi4_cipo.arready;
+ reg_strobe_total_count_rx_rdata <= reg_strobe_total_count_rx_axi4_cipo.rdata;
+ reg_strobe_total_count_rx_rresp <= reg_strobe_total_count_rx_axi4_cipo.rresp;
+ reg_strobe_total_count_rx_rvalid <= reg_strobe_total_count_rx_axi4_cipo.rvalid;
+
+end str;
\ No newline at end of file
diff --git a/libraries/io/eth/src/vhdl/eth_tester_pkg.vhd b/libraries/io/eth/src/vhdl/eth_tester_pkg.vhd
index 1ea6120bec1ad13aaafdf69ba424b1a7935ebf74..1a05df86b1e722871a34a4a62ed809c37606a243 100644
--- a/libraries/io/eth/src/vhdl/eth_tester_pkg.vhd
+++ b/libraries/io/eth/src/vhdl/eth_tester_pkg.vhd
@@ -58,8 +58,8 @@ package eth_tester_pkg is
-- to 0 by declaring hdr_fields_in_arr with all 0. Hence e.g. udp_checksum
-- = 0 can be achieve via data path and default hdr_fields_in_arr = 0 or
-- via MM controlled and field_default(0).
- constant c_eth_tester_nof_hdr_fields : natural := 1 +3 + 12 + 4 + 4;
- constant c_eth_tester_hdr_field_sel : std_logic_vector(c_eth_tester_nof_hdr_fields - 1 downto 0) := "1" &"101 " &"111011111001 " &"0100 " &"0100 ";
+ constant c_eth_tester_nof_hdr_fields : natural := 1 + 3 + 12 + 4 + 4;
+ constant c_eth_tester_hdr_field_sel : std_logic_vector(c_eth_tester_nof_hdr_fields - 1 downto 0) := "1" &"101 " &"111011111001 " &"0100 " &"0100 ";
-- Default use destination MAC/IP/UDP = 0, so these have to be MM programmed
-- before eth_tester packets can be send.
@@ -230,4 +230,4 @@ package body eth_tester_pkg is
return v;
end func_eth_tester_map_header;
-end eth_tester_pkg;
+end eth_tester_pkg;
\ No newline at end of file
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_crc_ctrl.vhd b/libraries/io/eth/tb/vhdl/tb_eth_crc_ctrl.vhd
index 87e82db15367d44f7964690a31932574243ad330..845bc35058ecf0a375d89f73c7392944272041c5 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_crc_ctrl.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_crc_ctrl.vhd
@@ -68,7 +68,7 @@ architecture tb of tb_eth_crc_ctrl is
signal cnt_en : std_logic;
signal tx_data : t_dp_data_arr(0 to c_tx_latency + c_tx_void) := (others => (others => '0'));
- signal tx_val : std_logic_vector(0 TO c_tx_latency + c_tx_void) := (others => '0');
+ signal tx_val : std_logic_vector(0 to c_tx_latency + c_tx_void) := (others => '0');
signal in_ready : std_logic;
signal in_data : std_logic_vector(c_eth_data_w - 1 downto 0) := (others => '0');
@@ -77,7 +77,7 @@ architecture tb of tb_eth_crc_ctrl is
signal in_eop : std_logic;
signal out_ready : std_logic;
- signal prev_out_ready : std_logic_vector(0 TO c_rx_latency);
+ signal prev_out_ready : std_logic_vector(0 to c_rx_latency);
signal out_data : std_logic_vector(c_eth_data_w - 1 downto 0);
signal out_data_1 : std_logic_vector(out_data'range);
signal out_data_2 : std_logic_vector(out_data'range);
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_hdr.vhd b/libraries/io/eth/tb/vhdl/tb_eth_hdr.vhd
index ca6103160356f5622a269344c26a481b4b6d86be..4dd72eb2961b2f0e71e31caeab2428ed618004f8 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_hdr.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_hdr.vhd
@@ -67,7 +67,7 @@ architecture tb of tb_eth_hdr is
signal cnt_en : std_logic;
signal tx_data : t_dp_data_arr(0 to c_tx_latency + c_tx_void) := (others => (others => '0'));
- signal tx_val : std_logic_vector(0 TO c_tx_latency + c_tx_void) := (others => '0');
+ signal tx_val : std_logic_vector(0 to c_tx_latency + c_tx_void) := (others => '0');
signal in_ready : std_logic;
signal in_data : std_logic_vector(c_dp_data_w - 1 downto 0) := (others => '0');
@@ -76,7 +76,7 @@ architecture tb of tb_eth_hdr is
signal in_eop : std_logic;
signal out_ready : std_logic;
- signal prev_out_ready : std_logic_vector(0 TO c_rx_latency);
+ signal prev_out_ready : std_logic_vector(0 to c_rx_latency);
signal out_data : std_logic_vector(c_dp_data_w - 1 downto 0);
signal out_val : std_logic;
signal out_sop : std_logic;
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_tester_pkg.vhd b/libraries/io/eth/tb/vhdl/tb_eth_tester_pkg.vhd
index 310a4b73a6c033068f833275a3148b1f3f7304d2..33bcb833a9fa7fe2584b22870aaf0a86e282951c 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_tester_pkg.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_tester_pkg.vhd
@@ -64,4 +64,4 @@ package body tb_eth_tester_pkg is
return c_network_eth_preamble_len + func_eth_tester_eth_packet_length(block_len) + c_word_sz;
end func_eth_tester_eth_packet_on_link_length;
-end tb_eth_tester_pkg;
+end tb_eth_tester_pkg;
\ No newline at end of file
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_udp_offload.vhd b/libraries/io/eth/tb/vhdl/tb_eth_udp_offload.vhd
index a6fe3c69e58a3e9d1837b84691aff7ebab754bdf..be8488ae2da26ac4cf15fd967eac7dbf17d410a8 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_udp_offload.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_udp_offload.vhd
@@ -177,7 +177,7 @@ architecture tb of tb_eth_udp_offload is
signal verify_en : std_logic := '0';
signal verify_done : std_logic := '0';
- signal prev_udp_rx_ready : std_logic_vector(0 TO c_rl);
+ signal prev_udp_rx_ready : std_logic_vector(0 to c_rl);
signal prev_udp_rx_data : std_logic_vector(g_data_w - 1 downto 0);
signal out_gap : std_logic := '1';
diff --git a/libraries/io/eth1g/src/vhdl/eth1g_master.vhd b/libraries/io/eth1g/src/vhdl/eth1g_master.vhd
index 11659e151f8d85d2dc721238f60f4a4731ebb413..7991faffdd2a0079f27562e0195fe5185298e74d 100644
--- a/libraries/io/eth1g/src/vhdl/eth1g_master.vhd
+++ b/libraries/io/eth1g/src/vhdl/eth1g_master.vhd
@@ -141,11 +141,11 @@ architecture rtl of eth1g_master is
constant lat_vec_size : natural := 8;
signal lat_reg_rd : std_logic;
- signal lat_reg_vec : std_logic_vector(0 TO lat_vec_size - 1);
+ signal lat_reg_vec : std_logic_vector(0 to lat_vec_size - 1);
signal reg_rd_valid : std_logic;
signal lat_ram_rd : std_logic;
- signal lat_ram_vec : std_logic_vector(0 TO lat_vec_size - 1);
+ signal lat_ram_vec : std_logic_vector(0 to lat_vec_size - 1);
signal ram_rd_valid : std_logic;
diff --git a/libraries/io/i2c/src/vhdl/avs_i2c_master.vhd b/libraries/io/i2c/src/vhdl/avs_i2c_master.vhd
index 243e217e972cd2388d1be447179decada77e48dd..ba295249c72ede2e9d9f3cdc3a0cff4e4db8d430 100644
--- a/libraries/io/i2c/src/vhdl/avs_i2c_master.vhd
+++ b/libraries/io/i2c/src/vhdl/avs_i2c_master.vhd
@@ -168,4 +168,4 @@ begin
sda => coe_i2c_sda_export
);
-end wrap;
+end wrap;
\ No newline at end of file
diff --git a/libraries/io/i2c/src/vhdl/i2c_bit.vhd b/libraries/io/i2c/src/vhdl/i2c_bit.vhd
index a7179f7ac8780b0af4180105416a1f598935ba78..390b297a8846adb250f8157e10db074f2886d583 100644
--- a/libraries/io/i2c/src/vhdl/i2c_bit.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_bit.vhd
@@ -512,4 +512,4 @@ begin
scl_oen <= iscl_oen;
sda_o <= '0';
sda_oen <= isda_oen;
-end architecture rtl;
+end architecture rtl;
\ No newline at end of file
diff --git a/libraries/io/i2c/src/vhdl/i2c_bit_scl_sense.vhd b/libraries/io/i2c/src/vhdl/i2c_bit_scl_sense.vhd
index ab507f65ddbed9d350a8425b39220ba4b1f50df1..a508f604eaa39be700384e2b554ccaca4abcfd6f 100644
--- a/libraries/io/i2c/src/vhdl/i2c_bit_scl_sense.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_bit_scl_sense.vhd
@@ -512,4 +512,4 @@ begin
scl_oen <= iscl_oen;
sda_o <= '0';
sda_oen <= isda_oen;
-end architecture rtl;
+end architecture rtl;
\ No newline at end of file
diff --git a/libraries/io/i2c/src/vhdl/i2c_byte.vhd b/libraries/io/i2c/src/vhdl/i2c_byte.vhd
index 5067fe35b1a0209141f9e8f47d3695f2fd1916ca..703d0f096dffabff78095e78b7ae4507a29c7967 100644
--- a/libraries/io/i2c/src/vhdl/i2c_byte.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_byte.vhd
@@ -433,4 +433,4 @@ begin
end block statemachine;
-end architecture structural;
+end architecture structural;
\ No newline at end of file
diff --git a/libraries/io/i2c/src/vhdl/i2c_smbus.vhd b/libraries/io/i2c/src/vhdl/i2c_smbus.vhd
index 5441ab0c7ea54302824700e7755eb35908281a1d..821c26040c97935aac9177c0d87e269d876e4864 100644
--- a/libraries/io/i2c/src/vhdl/i2c_smbus.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_smbus.vhd
@@ -74,7 +74,7 @@ architecture rtl of i2c_smbus is
signal rdy : std_logic;
signal nrst : std_logic;
- signal srst : std_logic_vector(0 TO 2);
+ signal srst : std_logic_vector(0 to 2);
signal nxt_srst : std_logic_vector(srst'range);
signal scl_i : std_logic;
diff --git a/libraries/io/i2c/src/vhdl/i2c_smbus_pkg.vhd b/libraries/io/i2c/src/vhdl/i2c_smbus_pkg.vhd
index a6c0ede4aea989b4cedd79403ffb5d12d73c8f5d..92e9dff0f68595fe4edfd6ef06bae4babe799ed9 100644
--- a/libraries/io/i2c/src/vhdl/i2c_smbus_pkg.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_smbus_pkg.vhd
@@ -49,7 +49,7 @@ package i2c_smbus_pkg is
-- SMBUS protocol definitions
-- a protocol is implemented as fixed length array of opcodes
- type SMBUS_PROtoCOL is array (0 TO 15) of OPCODE;
+ type SMBUS_PROtoCOL is array (0 to 15) of OPCODE;
-- The following protocols are as defined in the System Management Bus Specification v2.0
@@ -143,7 +143,7 @@ package i2c_smbus_pkg is
constant PROTOCOL_C_SAMPLE_SDA : SMBUS_PROTOCOL :=
( OP_LD_TIMEOUT, OP_LD_TIMEOUT, OP_LD_TIMEOUT, OP_LD_TIMEOUT, OP_WAIT, OP_RD_SDA, others => OP_IDLE );
- type PROTOCOL_array is ARRAY (natural range <> ) of SMBUS_PROTOCOL;
+ type PROTOCOL_array is array (natural range <> ) of SMBUS_PROTOCOL;
-- Protocol list
-- This maps a protocol identifier to the corresponding protocol
diff --git a/libraries/io/i2c/src/vhdl/i2cslave.vhd b/libraries/io/i2c/src/vhdl/i2cslave.vhd
index 2e5fd118e5fdf14c1ab3f827cef860b1b3bae788..1b5ff9472a65f24fa16e418fc91acf036e3a6c16 100644
--- a/libraries/io/i2c/src/vhdl/i2cslave.vhd
+++ b/libraries/io/i2c/src/vhdl/i2cslave.vhd
@@ -75,8 +75,8 @@ architecture rtl of i2cslave is
signal clk_cnt : unsigned(c_clk_cnt_w - 1 downto 0) := (others => '0');
signal nxt_clk_cnt : unsigned(clk_cnt'range);
- signal scl_meta : std_logic_vector(0 TO c_meta_len - 1);
- signal scl_line : std_logic_vector(0 TO c_line_len - 1);
+ signal scl_meta : std_logic_vector(0 to c_meta_len - 1);
+ signal scl_line : std_logic_vector(0 to c_line_len - 1);
signal scl_or : std_logic;
signal nxt_scl_or : std_logic;
signal scl_and : std_logic;
@@ -86,8 +86,8 @@ architecture rtl of i2cslave is
signal scl_rx : std_logic;
signal nxt_scl_rx : std_logic;
- signal sda_meta : std_logic_vector(0 TO c_meta_len - 1);
- signal sda_line : std_logic_vector(0 TO c_line_len - 1);
+ signal sda_meta : std_logic_vector(0 to c_meta_len - 1);
+ signal sda_line : std_logic_vector(0 to c_line_len - 1);
signal sda_or : std_logic;
signal nxt_sda_or : std_logic;
signal sda_and : std_logic;
@@ -364,7 +364,7 @@ begin
when write_data =>
if wbitcnt < 8 then
tri_en <= '1'; --enable tri-state buffer to write SDA
- if i_ctrl_reg(8 * g_nof_ctrl_bytes - 1 -(8*wbytecnt+wbitcnt))='0' then
+ if i_ctrl_reg(8 * g_nof_ctrl_bytes - 1 - (8 * wbytecnt + wbitcnt)) = '0' then
sda_int <= '0'; --copy one bit to SDA (MSB first), else default to 'H'
end if;
wbitcnt <= wbitcnt + 1;
diff --git a/libraries/io/i2c/tb/vhdl/i2c_slv_device.vhd b/libraries/io/i2c/tb/vhdl/i2c_slv_device.vhd
index 9a49eb05908967c1e1ef4417a6d5045c23bca037..709d7db9caec2eea5771b8ad6b6e7fa38871379f 100644
--- a/libraries/io/i2c/tb/vhdl/i2c_slv_device.vhd
+++ b/libraries/io/i2c/tb/vhdl/i2c_slv_device.vhd
@@ -149,7 +149,7 @@ begin
--output control signals
en <= '1' when dev_state = ST_CMD_OR_DATA else '0';
wr_val <= latch_ctrl_dly when dev_state = ST_CMD_OR_DATA else '0';
- rd_req <= rd_first or rd_next when dev_state = ST_CMD_or_DATA OR dev_state = ST_READ_DATA else '0';
+ rd_req <= rd_first or rd_next when dev_state = ST_CMD_or_DATA or dev_state = ST_READ_DATA else '0';
p <= stop; --output p is can be used to distinghuis beteen direct write data or cmd write data.
-- if at p n bytes were written, then it was a direct write,
-- else if at p 1+n bytes were written then it the first byte was the cmd.
@@ -340,7 +340,7 @@ begin
when write_data =>
if wbitcnt < 8 then
tri_en <= '1'; --enable tri-state buffer to write SDA
- if i_ctrl_reg(8 * g_nof_ctrl_bytes - 1 -(8*wbytecnt+wbitcnt))='0' then
+ if i_ctrl_reg(8 * g_nof_ctrl_bytes - 1 - (8 * wbytecnt + wbitcnt)) = '0' then
sda_int <= '0'; --copy one bit to SDA (MSB first), else default to 'H'
end if;
wbitcnt <= wbitcnt + 1;
diff --git a/libraries/io/i2c/tb/vhdl/tb_avs_i2c_master.vhd b/libraries/io/i2c/tb/vhdl/tb_avs_i2c_master.vhd
index 15932644b0098d28ada18ac30468ca34e64b005d..df5a2f60e7bd65b7f278b366fae85ee1e672e095 100644
--- a/libraries/io/i2c/tb/vhdl/tb_avs_i2c_master.vhd
+++ b/libraries/io/i2c/tb/vhdl/tb_avs_i2c_master.vhd
@@ -134,4 +134,4 @@ begin
ins_interrupt_irq => open
);
-end;
+end;
\ No newline at end of file
diff --git a/libraries/io/i2c/tb/vhdl/tb_i2c_commander.vhd b/libraries/io/i2c/tb/vhdl/tb_i2c_commander.vhd
index f8e86e8520fa5a6cc4cddf21ee14dd7a8df1fcb1..ee8c34ecc56602f136863325f580ae3819c69391 100644
--- a/libraries/io/i2c/tb/vhdl/tb_i2c_commander.vhd
+++ b/libraries/io/i2c/tb/vhdl/tb_i2c_commander.vhd
@@ -79,7 +79,7 @@ use work.i2c_commander_unbh_pkg.all;
architecture tb of tb_i2c_commander is
- constant c_protocol_ram_init_file : string := sel_a_b(g_board ="adu ", "data/adu_protocol_ram_init.hex", "data/unb_protocol_ram_init.hex");
+ constant c_protocol_ram_init_file : string := sel_a_b(g_board ="adu ", "data/adu_protocol_ram_init.hex", "data/unb_protocol_ram_init.hex");
--CONSTANT c_protocol_ram_init_file : STRING := "UNUSED";
constant c_use_result_ram : boolean := TRUE;
@@ -93,9 +93,9 @@ architecture tb of tb_i2c_commander is
constant c_phy_i2c : t_c_i2c_phy := func_i2c_sel_a_b(c_sim, c_i2c_phy_sim, func_i2c_calculate_phy(c_clk_freq_in_MHz));
-- Model I2C sensor slaves on the bus
- constant ADR_MAX6652 : natural := sel_a_b(g_board ="adu ", 0, I2C_UNB_MAX6652_ADR);
- constant ADR_MAX1617 : natural := sel_a_b(g_board ="adu ", I2C_ADU_MAX1617_ADR, I2C_UNB_MAX1617_ADR);
- constant ADR_PCA9555 : natural := sel_a_b(g_board ="adu ", I2C_ADU_PCA9555_ADR, 0);
+ constant ADR_MAX6652 : natural := sel_a_b(g_board ="adu ", 0, I2C_UNB_MAX6652_ADR);
+ constant ADR_MAX1617 : natural := sel_a_b(g_board ="adu ", I2C_ADU_MAX1617_ADR, I2C_UNB_MAX1617_ADR);
+ constant ADR_PCA9555 : natural := sel_a_b(g_board ="adu ", I2C_ADU_PCA9555_ADR, 0);
constant c_sens_volt_address : std_logic_vector := to_uvec(ADR_MAX6652, 7); -- MAX6652 address GND
constant c_max6652_volt_1v2 : natural := 92; -- 92 * 2.5/192 = 1.2
@@ -116,22 +116,22 @@ architecture tb of tb_i2c_commander is
constant c_max6652_expected_data_read_config_arr : t_i2c_cmdr_natural_arr := (c_max6652_volt_1v2, c_max6652_volt_2v5, c_max6652_volt_3v3, c_max6652_temp,
c_i2c_cmdr_expected_x, c_i2c_cmdr_expected_x, c_i2c_cmdr_expected_x, c_i2c_cmdr_expected_x);
- constant c_expected_data_0_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board ="adu ", c_max1618_expected_data_read_temp_arr, c_max1618_expected_data_read_temp_arr);
- constant c_expected_data_1_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board ="adu ", c_i2c_cmdr_expected_data_none_arr, c_max6652_expected_data_read_config_arr);
- constant c_expected_data_2_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board ="adu ", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
- constant c_expected_data_3_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board ="adu ", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
- constant c_expected_data_4_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board ="adu ", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
- constant c_expected_data_5_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board ="adu ", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
- constant c_expected_data_6_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board ="adu ", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
- constant c_expected_data_7_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board ="adu ", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
- constant c_expected_data_8_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board ="adu ", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
- constant c_expected_data_9_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board ="adu ", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
- constant c_expected_data_10_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board ="adu ", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
- constant c_expected_data_11_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board ="adu ", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
- constant c_expected_data_12_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board ="adu ", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
- constant c_expected_data_13_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board ="adu ", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
- constant c_expected_data_14_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board ="adu ", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
- constant c_expected_data_15_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board ="adu ", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
+ constant c_expected_data_0_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board ="adu ", c_max1618_expected_data_read_temp_arr, c_max1618_expected_data_read_temp_arr);
+ constant c_expected_data_1_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board ="adu ", c_i2c_cmdr_expected_data_none_arr, c_max6652_expected_data_read_config_arr);
+ constant c_expected_data_2_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board ="adu ", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
+ constant c_expected_data_3_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board ="adu ", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
+ constant c_expected_data_4_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board ="adu ", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
+ constant c_expected_data_5_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board ="adu ", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
+ constant c_expected_data_6_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board ="adu ", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
+ constant c_expected_data_7_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board ="adu ", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
+ constant c_expected_data_8_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board ="adu ", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
+ constant c_expected_data_9_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board ="adu ", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
+ constant c_expected_data_10_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board ="adu ", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
+ constant c_expected_data_11_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board ="adu ", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
+ constant c_expected_data_12_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board ="adu ", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
+ constant c_expected_data_13_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board ="adu ", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
+ constant c_expected_data_14_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board ="adu ", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
+ constant c_expected_data_15_arr : t_i2c_cmdr_natural_arr := func_i2c_cmdr_sel_a_b(g_board ="adu ", c_i2c_cmdr_expected_data_none_arr, c_i2c_cmdr_expected_data_none_arr);
constant c_expected_data_mat : t_i2c_cmdr_natural_mat(0 to c_i2c_cmdr_max_nof_protocols - 1) := (c_expected_data_0_arr,
c_expected_data_1_arr,
@@ -151,13 +151,13 @@ architecture tb of tb_i2c_commander is
c_expected_data_15_arr);
-- RAM sizes
- constant c_mem_i2c : t_c_i2c_mm := func_i2c_sel_a_b(g_board ="adu ", c_i2c_cmdr_aduh_i2c_mm, c_i2c_cmdr_unbh_i2c_mm);
+ constant c_mem_i2c : t_c_i2c_mm := func_i2c_sel_a_b(g_board ="adu ", c_i2c_cmdr_aduh_i2c_mm, c_i2c_cmdr_unbh_i2c_mm);
-- Commander parameters
- constant c_protocol_ram_init : t_nat_natural_arr := sel_a_b(g_board ="adu ", c_i2c_cmdr_aduh_protocol_ram_init, c_i2c_cmdr_unbh_protocol_ram_init);
- constant c_nof_result_data_arr : t_nat_natural_arr := sel_a_b(g_board ="adu ", c_i2c_cmdr_aduh_nof_result_data_arr, c_i2c_cmdr_unbh_nof_result_data_arr);
+ constant c_protocol_ram_init : t_nat_natural_arr := sel_a_b(g_board ="adu ", c_i2c_cmdr_aduh_protocol_ram_init, c_i2c_cmdr_unbh_protocol_ram_init);
+ constant c_nof_result_data_arr : t_nat_natural_arr := sel_a_b(g_board ="adu ", c_i2c_cmdr_aduh_nof_result_data_arr, c_i2c_cmdr_unbh_nof_result_data_arr);
- constant c_protocol_commander : t_c_i2c_cmdr_commander := func_i2c_cmdr_sel_a_b(g_board ="adu ", c_i2c_cmdr_aduh_protocol_commander, c_i2c_cmdr_unbh_protocol_commander);
+ constant c_protocol_commander : t_c_i2c_cmdr_commander := func_i2c_cmdr_sel_a_b(g_board ="adu ", c_i2c_cmdr_aduh_protocol_commander, c_i2c_cmdr_unbh_protocol_commander);
-- Commander MM register word indexes
constant c_protocol_status_wi : natural := 3 * c_protocol_commander.nof_protocols;
@@ -261,7 +261,7 @@ begin
-- Initialize the u_protocol_ram or verify its default contents
----------------------------------------------------------------------------
- if c_protocol_ram_init_file ="UNUSED " then
+ if c_protocol_ram_init_file ="UNUSED " then
-- Write
for I in 0 to c_protocol_ram_init'length - 1 loop
proc_mem_mm_bus_wr(I, c_protocol_ram_init(I), clk, protocol_miso, protocol_mosi); -- fill u_protocol_ram
@@ -455,4 +455,4 @@ begin
adu_atten_ctrl <= iobank1(5 downto 0);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/libraries/io/i2c/tb/vhdl/tb_i2c_commander_unb2_pmbus.vhd b/libraries/io/i2c/tb/vhdl/tb_i2c_commander_unb2_pmbus.vhd
index b4de3c93ba1551686f71b91bc358b1013d9c5a10..0173842166c13a1907eea12774f895b285045f50 100644
--- a/libraries/io/i2c/tb/vhdl/tb_i2c_commander_unb2_pmbus.vhd
+++ b/libraries/io/i2c/tb/vhdl/tb_i2c_commander_unb2_pmbus.vhd
@@ -206,7 +206,7 @@ begin
-- Initialize the u_protocol_ram or verify its default contents
----------------------------------------------------------------------------
- if c_protocol_ram_init_file ="UNUSED " then
+ if c_protocol_ram_init_file ="UNUSED " then
-- Write
for I in 0 to c_protocol_ram_init'length - 1 loop
proc_mem_mm_bus_wr(I, c_protocol_ram_init(I), clk, protocol_miso, protocol_mosi); -- fill u_protocol_ram
@@ -433,4 +433,4 @@ begin
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/libraries/io/i2c/tb/vhdl/tb_i2c_commander_unb2_sens.vhd b/libraries/io/i2c/tb/vhdl/tb_i2c_commander_unb2_sens.vhd
index fb609f332e9906a66ddf078b9e4cfeb50ad38e2d..47b1a5aad4f2bcb35e1f78d4378004bc43acbac4 100644
--- a/libraries/io/i2c/tb/vhdl/tb_i2c_commander_unb2_sens.vhd
+++ b/libraries/io/i2c/tb/vhdl/tb_i2c_commander_unb2_sens.vhd
@@ -211,7 +211,7 @@ begin
-- Initialize the u_protocol_ram or verify its default contents
----------------------------------------------------------------------------
- if c_protocol_ram_init_file ="UNUSED " then
+ if c_protocol_ram_init_file ="UNUSED " then
-- Write
for I in 0 to c_protocol_ram_init'length - 1 loop
proc_mem_mm_bus_wr(I, c_protocol_ram_init(I), clk, protocol_miso, protocol_mosi); -- fill u_protocol_ram
@@ -463,4 +463,4 @@ begin
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/libraries/io/i2c/tb/vhdl/tb_i2c_master.vhd b/libraries/io/i2c/tb/vhdl/tb_i2c_master.vhd
index 6e78871499521b91e143774d3a6d8fb9da4eddaa..51872f830c40b4bf607fc8146f3fbdbb04a9eae7 100644
--- a/libraries/io/i2c/tb/vhdl/tb_i2c_master.vhd
+++ b/libraries/io/i2c/tb/vhdl/tb_i2c_master.vhd
@@ -376,4 +376,4 @@ begin
temp => c_temp_pcb
);
-end tb;
+end tb;
\ No newline at end of file
diff --git a/libraries/io/i2c/tb/vhdl/tb_i2cslave.vhd b/libraries/io/i2c/tb/vhdl/tb_i2cslave.vhd
index 075387325e3adf6990379a3afde18df278a7eb46..4b659870d274174448419886f7d677582a898908 100644
--- a/libraries/io/i2c/tb/vhdl/tb_i2cslave.vhd
+++ b/libraries/io/i2c/tb/vhdl/tb_i2cslave.vhd
@@ -104,16 +104,16 @@ tbsda : process
wait for 452 ns; --next lines are evaluated 450 ns later
SDA <= 'z'; -- time for slave to acknowledge
wait for 50 ns; --WAIT 1 clk cycle
- SDA <= 'Z','h' after 10 ns, '0' after 60 ns, 'h' after 110 ns, '0' after 160 ns,'h' after 210 ns, 'H' after 260 ns, 'H' after 310 ns, '0' after 360 ns; -- sent first data byte
+ SDA <= 'Z','h' after 10 ns, '0' after 60 ns, 'h' after 110 ns, '0' after 160 ns,'h' after 210 ns, 'h' after 260 ns, 'h' after 310 ns, '0' after 360 ns; -- sent first data byte
wait for 400 ns;
SDA <= 'z'; -- time for slave to acknowledge
wait for 50 ns; --WAIT 1 clk cycle
- SDA <= 'z','0' after 10 ns, 'h' after 60 ns, 'h' after 110 ns, '0' after 160 ns,'h' after 210 ns, '0' after 260 ns, 'h' after 310 ns, 'H' after 360 ns; -- sent second data byte
+ SDA <= 'z','0' after 10 ns, 'h' after 60 ns, 'h' after 110 ns, '0' after 160 ns,'h' after 210 ns, '0' after 260 ns, 'h' after 310 ns, 'h' after 360 ns; -- sent second data byte
wait for 400 ns;
SDA <= 'z'; -- time for slave to acknowledge
wait for 50 ns; --WAIT 1 clk cycle
- SDA <= 'z','0' after 10 ns, 'h' after 60 ns, 'h' after 110 ns, '0' after 160 ns,'h' after 210 ns, '0' after 260 ns, 'h' after 310 ns, 'H' after 360 ns; -- sent third data byte
+ SDA <= 'z','0' after 10 ns, 'h' after 60 ns, 'h' after 110 ns, '0' after 160 ns,'h' after 210 ns, '0' after 260 ns, 'h' after 310 ns, 'h' after 360 ns; -- sent third data byte
wait for 400 ns;
SDA <= 'z'; -- time for slave to nacknowledge
@@ -162,11 +162,11 @@ tbsda : process
wait for 450 ns; --next lines are evaluated 450 ns later
SDA <= 'z'; -- time for slave to acknowledge
wait for 50 ns; --WAIT 1 clk cycle
- SDA <= 'z','0' after 10 ns, '0' after 60 ns, 'h' after 110 ns, '0' after 160 ns,'h' after 210 ns, 'h' after 260 ns, 'H' after 310 ns, '0' after 360 ns; -- sent first data byte
+ SDA <= 'z','0' after 10 ns, '0' after 60 ns, 'h' after 110 ns, '0' after 160 ns,'h' after 210 ns, 'h' after 260 ns, 'h' after 310 ns, '0' after 360 ns; -- sent first data byte
wait for 400 ns;
SDA <= 'z'; -- time for slave to acknowledge
wait for 50 ns; --WAIT 1 clk cycle
- SDA <= 'z','0' after 10 ns, 'h' after 60 ns, 'h' after 110 ns, '0' after 160 ns,'h' after 210 ns, '0' after 260 ns, 'h' after 310 ns, 'H' after 360 ns; -- sent second data byte
+ SDA <= 'z','0' after 10 ns, 'h' after 60 ns, 'h' after 110 ns, '0' after 160 ns,'h' after 210 ns, '0' after 260 ns, 'h' after 310 ns, 'h' after 360 ns; -- sent second data byte
wait for 400 ns;
SDA <= 'z'; -- time for slave to nacknowledge
wait for 80 ns; --WAIT 1.5 clk cycle
@@ -174,4 +174,4 @@ tbsda : process
wait for 20 ns; --to get in line with falling clk edge
end process;
-end;
+end;
\ No newline at end of file
diff --git a/libraries/io/mac_10g/io_mac_10g.vhd b/libraries/io/mac_10g/io_mac_10g.vhd
index 2c9b2e76ed18d5e6f125c922a81e595d6a0cf7a9..4846b8babcbc7e12eb0bbf054054c7aa6f819b1b 100644
--- a/libraries/io/mac_10g/io_mac_10g.vhd
+++ b/libraries/io/mac_10g/io_mac_10g.vhd
@@ -113,4 +113,4 @@ begin
xgmii_rx_data => xgmii_rx_data
);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/io/mdio/src/vhdl/avs_mdio.vhd b/libraries/io/mdio/src/vhdl/avs_mdio.vhd
index 2ae1548015434a0b34318fab677bad41e1281abc..cf9e6c324b12fbb7c45b70fc367dd8775361a61b 100644
--- a/libraries/io/mdio/src/vhdl/avs_mdio.vhd
+++ b/libraries/io/mdio/src/vhdl/avs_mdio.vhd
@@ -143,4 +143,4 @@ begin
mdat_oen => coe_mdio_phy_mdat_oen_export
);
-end wrap;
+end wrap;
\ No newline at end of file
diff --git a/libraries/io/mdio/src/vhdl/mdio_ctlr.vhd b/libraries/io/mdio/src/vhdl/mdio_ctlr.vhd
index cbc5fe6748003f736efa26453549be7fcea9b313..689867f7ff14fb1ac2e086030ea620d014dc1eae 100644
--- a/libraries/io/mdio/src/vhdl/mdio_ctlr.vhd
+++ b/libraries/io/mdio/src/vhdl/mdio_ctlr.vhd
@@ -166,4 +166,4 @@ begin
tx_dat <= r.tx_dat;
exec_complete <= r.exec_complete;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/io/mdio/src/vhdl/mdio_phy.vhd b/libraries/io/mdio/src/vhdl/mdio_phy.vhd
index 6897baa438fac578b017504620c9cc25436abf91..b0e9d8b84195b34d504c1f30eb3701606a36db2b 100644
--- a/libraries/io/mdio/src/vhdl/mdio_phy.vhd
+++ b/libraries/io/mdio/src/vhdl/mdio_phy.vhd
@@ -314,7 +314,7 @@ begin
if rx_en = '1' and state = s_receive then
for i in 3 to c_receive_msg_length - 1 loop
if bit_cnt = i then
- nxt_rx_dat(c_receive_msg_length - 1 -i) <= mdat_in;
+ nxt_rx_dat(c_receive_msg_length - 1 - i) <= mdat_in;
end if;
end loop;
end if;
diff --git a/libraries/io/mdio/src/vhdl/mdio_phy_reg.vhd b/libraries/io/mdio/src/vhdl/mdio_phy_reg.vhd
index 8ed559eb12d552112768cbe9c53012b158ee242b..4a500825bfe2cdbb4e4080f0284015b6a8b67395 100644
--- a/libraries/io/mdio/src/vhdl/mdio_phy_reg.vhd
+++ b/libraries/io/mdio/src/vhdl/mdio_phy_reg.vhd
@@ -178,4 +178,4 @@ begin
dout => mm_done
);
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/io/mdio/tb/vhdl/mmd_slave.vhd b/libraries/io/mdio/tb/vhdl/mmd_slave.vhd
index 173447ac3115c4fc3c8d74ef6e07feeeba27db95..d8b83aaf7d842fa772e2f96f5a4bc3b3192a8c9f 100644
--- a/libraries/io/mdio/tb/vhdl/mmd_slave.vhd
+++ b/libraries/io/mdio/tb/vhdl/mmd_slave.vhd
@@ -48,10 +48,10 @@ architecture beh of mmd_slave is
constant c_preamble_len : natural := 32;
constant c_preamble_timeout : natural := 1; -- >= 0
constant c_header_st_len : natural := 2;
- constant c_header_op_len : natural := 2 +2;
- constant c_header_prtad_len : natural := 2 +2 + 5;
- constant c_header_devad_len : natural := 2 +2 + 5 + 5;
- constant c_header_ta_len : natural := 2 +2 + 5 + 5 + 2;
+ constant c_header_op_len : natural := 2 + 2;
+ constant c_header_prtad_len : natural := 2 + 2 + 5;
+ constant c_header_devad_len : natural := 2 + 2 + 5 + 5;
+ constant c_header_ta_len : natural := 2 + 2 + 5 + 5 + 2;
constant c_data_len : natural := 16;
constant c_hdr_op_addr : std_logic_vector(1 downto 0) := "00"; -- operation code address (typically not used when g_quick = TRUE)
diff --git a/libraries/io/nw_10GbE/tb/vhdl/tb_nw_10GbE.vhd b/libraries/io/nw_10GbE/tb/vhdl/tb_nw_10GbE.vhd
index 597592135c239c822e1d2f703e561a90878c8679..fae0c32bf5872b7f44a4764dbe0acbab7fe8e07b 100644
--- a/libraries/io/nw_10GbE/tb/vhdl/tb_nw_10GbE.vhd
+++ b/libraries/io/nw_10GbE/tb/vhdl/tb_nw_10GbE.vhd
@@ -86,7 +86,7 @@ architecture tb of tb_nw_10GbE is
constant cal_clk_period : time := 25 ns; -- 40 MHz
constant phy_delay : time := sel_a_b(g_sim_level =0, 0 ns, 0 ns);
- constant c_tx_rx_loopback : boolean := g_direction /="TX_ONLY ";
+ constant c_tx_rx_loopback : boolean := g_direction /="TX_ONLY ";
constant c_tx_fifo_fill : natural := 100;
diff --git a/libraries/io/ppsh/src/vhdl/mm_ppsh.vhd b/libraries/io/ppsh/src/vhdl/mm_ppsh.vhd
index bd70aaae5db3f3401363d9c90622959240ec21be..20384838b9c0d27db3d478ffbe3cf0127d2ebc67 100644
--- a/libraries/io/ppsh/src/vhdl/mm_ppsh.vhd
+++ b/libraries/io/ppsh/src/vhdl/mm_ppsh.vhd
@@ -116,4 +116,4 @@ begin
nxt_mm_pps_toggle <= i_pps_toggle when i_mm_pps_pulse = '1' else i_mm_pps_toggle;
nxt_mm_pps_capture_cnt <= pps_capture_cnt when i_mm_pps_pulse = '1' else i_mm_pps_capture_cnt;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/io/ppsh/src/vhdl/mms_ppsh.vhd b/libraries/io/ppsh/src/vhdl/mms_ppsh.vhd
index e4987281a2837e8b199b3f59a88718807b78b924..a81b8ff5948b52a20b354bc64d1793a4855d049b 100644
--- a/libraries/io/ppsh/src/vhdl/mms_ppsh.vhd
+++ b/libraries/io/ppsh/src/vhdl/mms_ppsh.vhd
@@ -165,4 +165,4 @@ begin
pin_pps <= mm_pps_toggle & '0' & RESIZE_UVEC(mm_capture_cnt, 30); -- pin_pps did not support pps_stable yet
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/io/ppsh/src/vhdl/ppsh.vhd b/libraries/io/ppsh/src/vhdl/ppsh.vhd
index f0f49ce31b27ee5afdcf8ee84b15973b4df7615f..254d3ffa838bc4eccb2c81e8afc10c66d00ac987 100644
--- a/libraries/io/ppsh/src/vhdl/ppsh.vhd
+++ b/libraries/io/ppsh/src/vhdl/ppsh.vhd
@@ -208,4 +208,4 @@ begin
r_stable_ack => pps_stable_ack
);
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/io/ppsh/src/vhdl/ppsh_reg.vhd b/libraries/io/ppsh/src/vhdl/ppsh_reg.vhd
index 9d24cd187d2b554483a8c11b875c38b8a923af31..05c38626fae0220f5cb3226ba24c743075fdb968 100644
--- a/libraries/io/ppsh/src/vhdl/ppsh_reg.vhd
+++ b/libraries/io/ppsh/src/vhdl/ppsh_reg.vhd
@@ -281,4 +281,4 @@ begin
end generate; -- gen_cross
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/io/remu/src/vhdl/mms_remu.vhd b/libraries/io/remu/src/vhdl/mms_remu.vhd
index 5c8e89d7a8ca385aea277eadbfc2c0cbe8a7d21d..3b33c67e22ed41e8f3502afc9c9d88a6e9de14bb 100644
--- a/libraries/io/remu/src/vhdl/mms_remu.vhd
+++ b/libraries/io/remu/src/vhdl/mms_remu.vhd
@@ -145,4 +145,4 @@ begin
out_rst => epcs_rst
);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/io/remu/src/vhdl/remu_reg.vhd b/libraries/io/remu/src/vhdl/remu_reg.vhd
index 3633bd8606005bf95bc2f5c58a1a3760a7c66437..2a99d36b817bcca8a785394264299c1c59f12a16 100644
--- a/libraries/io/remu/src/vhdl/remu_reg.vhd
+++ b/libraries/io/remu/src/vhdl/remu_reg.vhd
@@ -227,4 +227,4 @@ begin
out_new => open
);
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/io/tr_10GbE/tb/vhdl/tb_tr_10GbE.vhd b/libraries/io/tr_10GbE/tb/vhdl/tb_tr_10GbE.vhd
index 6ca6aeab3f33f071415c4d2d8fc5a9bf5345ba1a..c4ffd0e8900df3abe1c3642d3738e0c029dd5309 100644
--- a/libraries/io/tr_10GbE/tb/vhdl/tb_tr_10GbE.vhd
+++ b/libraries/io/tr_10GbE/tb/vhdl/tb_tr_10GbE.vhd
@@ -84,7 +84,7 @@ architecture tb of tb_tr_10GbE is
constant cal_clk_period : time := 25 ns; -- 40 MHz
constant phy_delay : time := sel_a_b(g_sim_level =0, 0 ns, 0 ns);
- constant c_tx_rx_loopback : boolean := g_direction /="TX_ONLY ";
+ constant c_tx_rx_loopback : boolean := g_direction /="TX_ONLY ";
constant c_tx_fifo_fill : natural := 100;
diff --git a/libraries/io/tr_nonbonded/src/vhdl/tr_nonbonded.vhd b/libraries/io/tr_nonbonded/src/vhdl/tr_nonbonded.vhd
index e662db9362991c8aea799f377eeeb5e4dae0f60e..12c647af3afd591f47a121958122966d48112ea8 100644
--- a/libraries/io/tr_nonbonded/src/vhdl/tr_nonbonded.vhd
+++ b/libraries/io/tr_nonbonded/src/vhdl/tr_nonbonded.vhd
@@ -283,4 +283,4 @@ begin
end generate; -- gen_i
end generate; -- gen_rx
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/io/tr_nonbonded/src/vhdl/tr_nonbonded_reg.vhd b/libraries/io/tr_nonbonded/src/vhdl/tr_nonbonded_reg.vhd
index 546eabb3392a5283fcdb1fadf3cd43b449dddab1..b09cd39b4334647efbe6d0597de5cadd346c087f 100644
--- a/libraries/io/tr_nonbonded/src/vhdl/tr_nonbonded_reg.vhd
+++ b/libraries/io/tr_nonbonded/src/vhdl/tr_nonbonded_reg.vhd
@@ -178,4 +178,4 @@ begin
end generate;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/io/tr_nonbonded/tb/vhdl/tb_tr_nonbonded.vhd b/libraries/io/tr_nonbonded/tb/vhdl/tb_tr_nonbonded.vhd
index a602b0e54dbf8bc86d54931fa7aa4cd87401333f..e2e3e2cc590ecdb0eb4890185482b6a78e17bed2 100644
--- a/libraries/io/tr_nonbonded/tb/vhdl/tb_tr_nonbonded.vhd
+++ b/libraries/io/tr_nonbonded/tb/vhdl/tb_tr_nonbonded.vhd
@@ -307,5 +307,4 @@ begin
wait;
end process;
-end architecture str;
-
+end architecture str;
\ No newline at end of file
diff --git a/libraries/io/tr_xaui/src/vhdl/mms_tr_xaui.vhd b/libraries/io/tr_xaui/src/vhdl/mms_tr_xaui.vhd
index 73284be20baae92dd0fc3561e270e8300921730e..62388cd9db6b51e50e4d461c65d19c1f37278b16 100644
--- a/libraries/io/tr_xaui/src/vhdl/mms_tr_xaui.vhd
+++ b/libraries/io/tr_xaui/src/vhdl/mms_tr_xaui.vhd
@@ -295,4 +295,4 @@ begin
end generate;
-end wrap;
+end wrap;
\ No newline at end of file
diff --git a/libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd b/libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd
index f3be4b721c69d94242f775e289e66f5a6f86fe39..3d60e1cf5935a9c967cfddd9f1e87ec9bf51acf3 100644
--- a/libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd
+++ b/libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd
@@ -242,4 +242,4 @@ begin
);
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/io/tr_xaui/src/vhdl/tr_xaui_deframer.vhd b/libraries/io/tr_xaui/src/vhdl/tr_xaui_deframer.vhd
index af5532231fdb7935181717d007084ed892f1fe21..8cf60dcfc21ecb40b591c52e367605720b42feb9 100644
--- a/libraries/io/tr_xaui/src/vhdl/tr_xaui_deframer.vhd
+++ b/libraries/io/tr_xaui/src/vhdl/tr_xaui_deframer.vhd
@@ -207,5 +207,4 @@ begin
end case;
end process;
-end rtl;
-
+end rtl;
\ No newline at end of file
diff --git a/libraries/io/tr_xaui/src/vhdl/tr_xaui_framer.vhd b/libraries/io/tr_xaui/src/vhdl/tr_xaui_framer.vhd
index de18d5bbe4741877822267dd1e380e265e108521..e168fcfe15c6d828d3418cd9e6901e800870ddf8 100644
--- a/libraries/io/tr_xaui/src/vhdl/tr_xaui_framer.vhd
+++ b/libraries/io/tr_xaui/src/vhdl/tr_xaui_framer.vhd
@@ -156,5 +156,4 @@ begin
end case;
end process;
-end rtl;
-
+end rtl;
\ No newline at end of file
diff --git a/libraries/io/tr_xaui/src/vhdl/tr_xaui_mdio.vhd b/libraries/io/tr_xaui/src/vhdl/tr_xaui_mdio.vhd
index 39264fb3fd8e1ff03e8cf817adf1099962a109da..e98b24f3c49ac5a64e52c268292b3e792c017c70 100644
--- a/libraries/io/tr_xaui/src/vhdl/tr_xaui_mdio.vhd
+++ b/libraries/io/tr_xaui/src/vhdl/tr_xaui_mdio.vhd
@@ -207,4 +207,4 @@ begin
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/io/tr_xaui/tb/vhdl/tb_tr_xaui.vhd b/libraries/io/tr_xaui/tb/vhdl/tb_tr_xaui.vhd
index 97fa188e3775678338b49480387f564be79a5872..4f8d06feeda1ca097e829ea6a903567e897d447c 100644
--- a/libraries/io/tr_xaui/tb/vhdl/tb_tr_xaui.vhd
+++ b/libraries/io/tr_xaui/tb/vhdl/tb_tr_xaui.vhd
@@ -228,5 +228,4 @@ begin
src_val_cnt => src_val_cnt
);
-end architecture str;
-
+end architecture str;
\ No newline at end of file
diff --git a/libraries/technology/10gbase_r/sim_10gbase_r.vhd b/libraries/technology/10gbase_r/sim_10gbase_r.vhd
index 545b71598fbd7e460c45f7fb04a7f3ce29de0fca..377b71e9f871e71ebce1c88fd39d64ca31562b7e 100644
--- a/libraries/technology/10gbase_r/sim_10gbase_r.vhd
+++ b/libraries/technology/10gbase_r/sim_10gbase_r.vhd
@@ -141,4 +141,4 @@ begin
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r.vhd b/libraries/technology/10gbase_r/tech_10gbase_r.vhd
index f3ba946701a9b21fc8963fd4175d0f59e74ad659..c955aeba0a057ba16355c9dbeaa622b13472bc14 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r.vhd
@@ -126,4 +126,4 @@ begin
tx_serial_arr, rx_serial_arr);
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/technology/clkbuf/tech_clkbuf.vhd b/libraries/technology/clkbuf/tech_clkbuf.vhd
index 5ed687f5f98d873cd11e5b1a2fb649e4596ec7e5..5f935adc85322083b5dfc9bd739f83f52c10a0b7 100644
--- a/libraries/technology/clkbuf/tech_clkbuf.vhd
+++ b/libraries/technology/clkbuf/tech_clkbuf.vhd
@@ -50,7 +50,7 @@ begin
-- ip_arria10
-----------------------------------------------------------------------------
- gen_ip_arria10 : if g_technology = c_tech_arria10_proto and g_clock_net ="GLOBAL " generate
+ gen_ip_arria10 : if g_technology = c_tech_arria10_proto and g_clock_net ="GLOBAL " generate
u0 : ip_arria10_clkbuf_global
port map (
inclk => inclk, -- inclk
@@ -62,7 +62,7 @@ begin
-- ip_arria10_e3sge3
-----------------------------------------------------------------------------
- gen_ip_arria10_e3sge3 : if g_technology = c_tech_arria10_e3sge3 and g_clock_net ="GLOBAL " generate
+ gen_ip_arria10_e3sge3 : if g_technology = c_tech_arria10_e3sge3 and g_clock_net ="GLOBAL " generate
u0 : ip_arria10_e3sge3_clkbuf_global
port map (
inclk => inclk, -- inclk
@@ -74,7 +74,7 @@ begin
-- ip_arria10_e1sg
-----------------------------------------------------------------------------
- gen_ip_arria10_e1sg : if g_technology = c_tech_arria10_e1sg and g_clock_net ="GLOBAL " generate
+ gen_ip_arria10_e1sg : if g_technology = c_tech_arria10_e1sg and g_clock_net ="GLOBAL " generate
u0 : ip_arria10_e1sg_clkbuf_global
port map (
inclk => inclk, -- inclk
@@ -86,7 +86,7 @@ begin
-- ip_arria10_e2sg
-----------------------------------------------------------------------------
- gen_ip_arria10_e2sg : if g_technology = c_tech_arria10_e2sg and g_clock_net ="GLOBAL " generate
+ gen_ip_arria10_e2sg : if g_technology = c_tech_arria10_e2sg and g_clock_net ="GLOBAL " generate
u0 : ip_arria10_e2sg_clkbuf_global
port map (
inclk => inclk, -- inclk
diff --git a/libraries/technology/clkbuf/tech_clkbuf_component_pkg.vhd b/libraries/technology/clkbuf/tech_clkbuf_component_pkg.vhd
index bb3419abd340e7001d5b8cd4aac28a599becb2ac..6c7fa2870c60cf88dffdce2af8ec03410bd4c4bb 100644
--- a/libraries/technology/clkbuf/tech_clkbuf_component_pkg.vhd
+++ b/libraries/technology/clkbuf/tech_clkbuf_component_pkg.vhd
@@ -71,4 +71,4 @@ package tech_clkbuf_component_pkg is
);
end component;
-end tech_clkbuf_component_pkg;
+end tech_clkbuf_component_pkg;
\ No newline at end of file
diff --git a/libraries/technology/ddr/sim_ddr.vhd b/libraries/technology/ddr/sim_ddr.vhd
index 816c006b186eaf129965ab2db1c09a26bec1eee6..43b6395ac3986f691aeca84e0b383f24f1e45cc5 100644
--- a/libraries/technology/ddr/sim_ddr.vhd
+++ b/libraries/technology/ddr/sim_ddr.vhd
@@ -228,4 +228,4 @@ begin
end process;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/technology/ddr/tech_ddr.vhd b/libraries/technology/ddr/tech_ddr.vhd
index d9d4e07860ef1c404248e5123ed66d71951b735c..66b180745e1f08989d878bb1dcbe1654c1860652 100644
--- a/libraries/technology/ddr/tech_ddr.vhd
+++ b/libraries/technology/ddr/tech_ddr.vhd
@@ -148,4 +148,4 @@ begin
);
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/technology/ddr/tech_ddr_arria10.vhd b/libraries/technology/ddr/tech_ddr_arria10.vhd
index 71d4ce5e305068c1977750e3b3aa933851a7adc3..047aa079af74bbc84dc7143c73ed77dc5c652f81 100644
--- a/libraries/technology/ddr/tech_ddr_arria10.vhd
+++ b/libraries/technology/ddr/tech_ddr_arria10.vhd
@@ -90,7 +90,7 @@ begin
ref_rst_n <= not ref_rst;
ctlr_gen_rst <= not ctlr_gen_rst_n;
- gen_ip_arria10_ddr4_4g_2000 : if g_tech_ddr.name ="DDR4 " and c_gigabytes = 4 and g_tech_ddr.mts = 2000 generate
+ gen_ip_arria10_ddr4_4g_2000 : if g_tech_ddr.name ="DDR4 " and c_gigabytes = 4 and g_tech_ddr.mts = 2000 generate
phy_ou.cs_n(1) <= '1';
phy_ou.cke(1) <= '0';
@@ -147,7 +147,7 @@ begin
end generate;
- gen_ip_arria10_ddr4_4g_1600 : if g_tech_ddr.name ="DDR4 " and c_gigabytes = 4 and g_tech_ddr.mts = 1600 generate
+ gen_ip_arria10_ddr4_4g_1600 : if g_tech_ddr.name ="DDR4 " and c_gigabytes = 4 and g_tech_ddr.mts = 1600 generate
phy_ou.cs_n(1) <= '1';
phy_ou.cke(1) <= '0';
diff --git a/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd b/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd
index 5f3cb1b6f674b18b6409c6947c76c3e9d92b0929..738e75c7b15d85c3142885988b829637aeb5d95f 100644
--- a/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd
+++ b/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd
@@ -93,7 +93,7 @@ begin
ref_rst_n <= not ref_rst;
ctlr_gen_rst <= not ctlr_gen_rst_n;
- gen_ip_arria10_e1sg_ddr4_4g_2000 : if g_tech_ddr.name ="DDR4 " and c_gigabytes = 4 and g_tech_ddr.mts = 2000 generate
+ gen_ip_arria10_e1sg_ddr4_4g_2000 : if g_tech_ddr.name ="DDR4 " and c_gigabytes = 4 and g_tech_ddr.mts = 2000 generate
phy_ou.cs_n(1) <= '1';
phy_ou.cke(1) <= '0';
@@ -150,7 +150,7 @@ begin
end generate;
- gen_ip_arria10_e1sg_ddr4_4g_1600 : if g_tech_ddr.name ="DDR4 " and c_gigabytes = 4 and g_tech_ddr.mts = 1600 generate
+ gen_ip_arria10_e1sg_ddr4_4g_1600 : if g_tech_ddr.name ="DDR4 " and c_gigabytes = 4 and g_tech_ddr.mts = 1600 generate
phy_ou.cs_n(1) <= '1';
phy_ou.cke(1) <= '0';
@@ -207,7 +207,7 @@ begin
end generate;
- gen_ip_arria10_e1sg_ddr4_8g_1600 : if g_tech_ddr.name ="DDR4 " and c_gigabytes = 8 and g_tech_ddr.mts = 1600 generate
+ gen_ip_arria10_e1sg_ddr4_8g_1600 : if g_tech_ddr.name ="DDR4 " and c_gigabytes = 8 and g_tech_ddr.mts = 1600 generate
u_ip_arria10_e1sg_ddr4_8g_1600 : ip_arria10_e1sg_ddr4_8g_1600
port map (
@@ -260,7 +260,7 @@ begin
end generate;
- gen_ip_arria10_e1sg_ddr4_16g_1600 : if g_tech_ddr.name ="DDR4 " and c_gigabytes = 16 and g_tech_ddr.mts = 1600 generate
+ gen_ip_arria10_e1sg_ddr4_16g_1600 : if g_tech_ddr.name ="DDR4 " and c_gigabytes = 16 and g_tech_ddr.mts = 1600 generate
u_ip_arria10_e1sg_ddr4_16g_1600 : ip_arria10_e1sg_ddr4_16g_1600
port map (
diff --git a/libraries/technology/ddr/tech_ddr_arria10_e2sg.vhd b/libraries/technology/ddr/tech_ddr_arria10_e2sg.vhd
index 11139fab70bd3642874fb67e0d2a99819fc66c94..077900bd8aa92443f77629a7c65f7f174b2494ab 100644
--- a/libraries/technology/ddr/tech_ddr_arria10_e2sg.vhd
+++ b/libraries/technology/ddr/tech_ddr_arria10_e2sg.vhd
@@ -98,7 +98,7 @@ begin
ctlr_gen_rst <= not ctlr_gen_rst_n;
- gen_ip_arria10_e2sg_ddr4_8g_1600 : if g_tech_ddr.name ="DDR4 " and c_gigabytes = 8 and g_tech_ddr.mts = 1600 generate
+ gen_ip_arria10_e2sg_ddr4_8g_1600 : if g_tech_ddr.name ="DDR4 " and c_gigabytes = 8 and g_tech_ddr.mts = 1600 generate
u_ip_arria10_e2sg_ddr4_8g_1600 : ip_arria10_e2sg_ddr4_8g_1600
port map (
@@ -152,7 +152,7 @@ begin
end generate;
- gen_ip_arria10_e2sg_ddr4_8g_2400 : if g_tech_ddr.name ="DDR4 " and c_gigabytes = 8 and g_tech_ddr.mts = 2400 generate
+ gen_ip_arria10_e2sg_ddr4_8g_2400 : if g_tech_ddr.name ="DDR4 " and c_gigabytes = 8 and g_tech_ddr.mts = 2400 generate
u_ip_arria10_e2sg_ddr4_8g_2400 : ip_arria10_e2sg_ddr4_8g_2400
port map (
@@ -206,7 +206,7 @@ begin
end generate;
- gen_ip_arria10_e2sg_ddr4_16g_1600_64b : if g_tech_ddr.name ="DDR4 " and c_gigabytes = 16 and g_tech_ddr.mts = 1600 and g_tech_ddr.dq_w = 64 generate
+ gen_ip_arria10_e2sg_ddr4_16g_1600_64b : if g_tech_ddr.name ="DDR4 " and c_gigabytes = 16 and g_tech_ddr.mts = 1600 and g_tech_ddr.dq_w = 64 generate
u_ip_arria10_e2sg_ddr4_16g_1600_64b : ip_arria10_e2sg_ddr4_16g_1600_64b
port map (
@@ -260,7 +260,7 @@ begin
end generate;
- gen_ip_arria10_e2sg_ddr4_16g_1600_72b : if g_tech_ddr.name ="DDR4 " and c_gigabytes = 16 and g_tech_ddr.mts = 1600 and g_tech_ddr.dq_w = 72 generate
+ gen_ip_arria10_e2sg_ddr4_16g_1600_72b : if g_tech_ddr.name ="DDR4 " and c_gigabytes = 16 and g_tech_ddr.mts = 1600 and g_tech_ddr.dq_w = 72 generate
u_ip_arria10_e2sg_ddr4_16g_1600_72b : ip_arria10_e2sg_ddr4_16g_1600_72b
port map (
diff --git a/libraries/technology/ddr/tech_ddr_arria10_e3sge3.vhd b/libraries/technology/ddr/tech_ddr_arria10_e3sge3.vhd
index b26c2529cde69843b7084de6577f453715111c54..e17e0abaa6e5ca00fde2bd6c442b50fadddf7487 100644
--- a/libraries/technology/ddr/tech_ddr_arria10_e3sge3.vhd
+++ b/libraries/technology/ddr/tech_ddr_arria10_e3sge3.vhd
@@ -92,7 +92,7 @@ begin
ref_rst_n <= not ref_rst;
ctlr_gen_rst <= not ctlr_gen_rst_n;
- gen_ip_arria10_e3sge3_ddr4_4g_2000 : if g_tech_ddr.name ="DDR4 " and c_gigabytes = 4 and g_tech_ddr.mts = 2000 generate
+ gen_ip_arria10_e3sge3_ddr4_4g_2000 : if g_tech_ddr.name ="DDR4 " and c_gigabytes = 4 and g_tech_ddr.mts = 2000 generate
phy_ou.cs_n(1) <= '1';
phy_ou.cke(1) <= '0';
@@ -149,7 +149,7 @@ begin
end generate;
- gen_ip_arria10_e3sge3_ddr4_4g_1600 : if g_tech_ddr.name ="DDR4 " and c_gigabytes = 4 and g_tech_ddr.mts = 1600 generate
+ gen_ip_arria10_e3sge3_ddr4_4g_1600 : if g_tech_ddr.name ="DDR4 " and c_gigabytes = 4 and g_tech_ddr.mts = 1600 generate
phy_ou.cs_n(1) <= '1';
phy_ou.cke(1) <= '0';
@@ -206,7 +206,7 @@ begin
end generate;
- gen_ip_arria10_e3sge3_ddr4_8g_1600 : if g_tech_ddr.name ="DDR4 " and c_gigabytes = 8 and g_tech_ddr.mts = 1600 generate
+ gen_ip_arria10_e3sge3_ddr4_8g_1600 : if g_tech_ddr.name ="DDR4 " and c_gigabytes = 8 and g_tech_ddr.mts = 1600 generate
u_ip_arria10_e3sge3_ddr4_8g_1600 : ip_arria10_e3sge3_ddr4_8g_1600
port map (
diff --git a/libraries/technology/ddr/tech_ddr_mem_model.vhd b/libraries/technology/ddr/tech_ddr_mem_model.vhd
index 2d2a7b30ebe5b717ae71bc1fa26c150515fd2157..9b8ae9791b72dad7124c92f46aa2b22b61475aab 100644
--- a/libraries/technology/ddr/tech_ddr_mem_model.vhd
+++ b/libraries/technology/ddr/tech_ddr_mem_model.vhd
@@ -66,7 +66,7 @@ architecture str of tech_ddr_memory_model is
begin
- gen_ip_stratixiv_ddr_memory_model : if g_tech_ddr.name ="DDR3 " generate
+ gen_ip_stratixiv_ddr_memory_model : if g_tech_ddr.name ="DDR3 " generate
u_ip_stratixiv_ddr_memory_model : alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en
generic map (
MEM_IF_CLK_EN_WIDTH => g_tech_ddr.cke_w,
@@ -114,7 +114,7 @@ begin
);
end generate;
- gen_ip_arria10_ddr_memory_model : if g_tech_ddr.name ="DDR4 " and c_gigabytes = 4 generate
+ gen_ip_arria10_ddr_memory_model : if g_tech_ddr.name ="DDR4 " and c_gigabytes = 4 generate
u_ip_arria10_ddr_memory_model : ed_sim_altera_emif_mem_model_141_z3tvrmq
port map (
mem_ck => mem4_in.ck(g_tech_ddr.ck_w - 1 downto 0), -- mem_conduit_end.mem_ck
@@ -136,4 +136,4 @@ begin
);
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/technology/ddr/tech_ddr_pkg.vhd b/libraries/technology/ddr/tech_ddr_pkg.vhd
index e2a59c77931f55d8e944244ab734b9f13d7104c8..1c710f06ffe7d9d56638eae1504aae5f40c98bf1 100644
--- a/libraries/technology/ddr/tech_ddr_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_pkg.vhd
@@ -188,7 +188,7 @@ package tech_ddr_pkg is
afi_reset_n : std_logic;
end record;
- constant c_tech_ddr3_phy_terminationcontrol_x : t_tech_ddr3_phy_terminationcontrol := ((others => 'x'), (others => 'x'),'x','x','x','x','X','X','X', (others => 'X'), 'X', 'X', 'X');
+ constant c_tech_ddr3_phy_terminationcontrol_x : t_tech_ddr3_phy_terminationcontrol := ((others => 'x'), (others => 'x'),'x','x','x','x','x','x','x', (others => 'x'), 'x', 'x', 'x');
constant c_tech_ddr3_phy_terminationcontrol_rst : t_tech_ddr3_phy_terminationcontrol := ((others => '0'), (others => '0'),'0','0','0','0','0','0','0', (others => '0'), '0', '0', '0');
constant c_tech_ddr3_phy_in_x : t_tech_ddr3_phy_in := ('x', 'x', 'x');
@@ -219,8 +219,8 @@ package body tech_ddr_pkg is
function func_tech_ddr_dq_address_w(c_ddr : t_c_tech_ddr) return natural is
begin
- if c_ddr.name ="DDR3 " then return c_ddr.cs_w_w + c_ddr.ba_w + c_ddr.a_row_w + c_ddr.a_col_w; end if; -- PHY address
- if c_ddr.name ="DDR4 " then return c_ddr.cs_w_w + c_ddr.ba_w + c_ddr.a_row_w + c_ddr.a_col_w + c_ddr.bg_w; end if; -- PHY address
+ if c_ddr.name ="DDR3 " then return c_ddr.cs_w_w + c_ddr.ba_w + c_ddr.a_row_w + c_ddr.a_col_w; end if; -- PHY address
+ if c_ddr.name ="DDR4 " then return c_ddr.cs_w_w + c_ddr.ba_w + c_ddr.a_row_w + c_ddr.a_col_w + c_ddr.bg_w; end if; -- PHY address
end;
function func_tech_ddr_ctlr_address_w(c_ddr : t_c_tech_ddr) return natural is
@@ -284,4 +284,4 @@ package body tech_ddr_pkg is
return vec_64b;
end;
-end tech_ddr_pkg;
+end tech_ddr_pkg;
\ No newline at end of file
diff --git a/libraries/technology/ddr/tech_ddr_stratixiv.vhd b/libraries/technology/ddr/tech_ddr_stratixiv.vhd
index ecc97812567b2616e9dd56bc7ad0185cc6378679..2ee7a0129e8584e77c6de9c573203d354ccd71a4 100644
--- a/libraries/technology/ddr/tech_ddr_stratixiv.vhd
+++ b/libraries/technology/ddr/tech_ddr_stratixiv.vhd
@@ -95,7 +95,7 @@ begin
ref_rst_n <= not ref_rst;
- gen_ip_stratixiv_ddr3_uphy_4g_800_master : if g_tech_ddr.name ="DDR3 " and c_gigabytes = 4 and g_tech_ddr.mts = 800 and g_tech_ddr.master = TRUE and g_tech_ddr.rank ="DUAL " generate
+ gen_ip_stratixiv_ddr3_uphy_4g_800_master : if g_tech_ddr.name ="DDR3 " and c_gigabytes = 4 and g_tech_ddr.mts = 800 and g_tech_ddr.master = TRUE and g_tech_ddr.rank ="DUAL " generate
u_ip_stratixiv_ddr3_uphy_4g_800_master : ip_stratixiv_ddr3_uphy_4g_800_master
port map (
pll_ref_clk => ref_clk, -- pll_ref_clk.clk
@@ -147,7 +147,7 @@ begin
);
end generate;
- gen_ip_stratixiv_ddr3_uphy_4g_800_slave : if g_tech_ddr.name ="DDR3 " and c_gigabytes = 4 and g_tech_ddr.mts = 800 and g_tech_ddr.master = FALSE and g_tech_ddr.rank ="DUAL " generate
+ gen_ip_stratixiv_ddr3_uphy_4g_800_slave : if g_tech_ddr.name ="DDR3 " and c_gigabytes = 4 and g_tech_ddr.mts = 800 and g_tech_ddr.master = FALSE and g_tech_ddr.rank ="DUAL " generate
u_ip_stratixiv_ddr3_uphy_4g_800_slave : ip_stratixiv_ddr3_uphy_4g_800_slave
port map (
pll_ref_clk => ref_clk, -- pll_ref_clk.clk
@@ -197,7 +197,7 @@ begin
);
end generate;
- gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master : if g_tech_ddr.name ="DDR3 " and c_gigabytes = 4 and g_tech_ddr.mts = 800 and g_tech_ddr.master = TRUE and g_tech_ddr.rank ="SINGLE " generate
+ gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master : if g_tech_ddr.name ="DDR3 " and c_gigabytes = 4 and g_tech_ddr.mts = 800 and g_tech_ddr.master = TRUE and g_tech_ddr.rank ="SINGLE " generate
u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master : ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
port map (
pll_ref_clk => ref_clk, -- pll_ref_clk.clk
@@ -254,7 +254,7 @@ begin
end generate;
- gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave : if g_tech_ddr.name ="DDR3 " and c_gigabytes = 4 and g_tech_ddr.mts = 800 and g_tech_ddr.master = FALSE and g_tech_ddr.rank ="SINGLE " generate
+ gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave : if g_tech_ddr.name ="DDR3 " and c_gigabytes = 4 and g_tech_ddr.mts = 800 and g_tech_ddr.master = FALSE and g_tech_ddr.rank ="SINGLE " generate
u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave : ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
port map (
pll_ref_clk => ref_clk, -- pll_ref_clk.clk
@@ -309,7 +309,7 @@ begin
end generate;
- gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800 : if g_tech_ddr.name ="DDR3 " and c_gigabytes = 16 and g_tech_ddr.mts = 800 and g_tech_ddr.master = TRUE and g_tech_ddr.rank ="DUAL " generate
+ gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800 : if g_tech_ddr.name ="DDR3 " and c_gigabytes = 16 and g_tech_ddr.mts = 800 and g_tech_ddr.master = TRUE and g_tech_ddr.rank ="DUAL " generate
u_ip_stratixiv_ddr3_uphy_16g_dual_rank_800 : ip_stratixiv_ddr3_uphy_16g_dual_rank_800
port map (
pll_ref_clk => ref_clk, -- pll_ref_clk.clk
diff --git a/libraries/technology/fifo/tech_fifo_component_pkg.vhd b/libraries/technology/fifo/tech_fifo_component_pkg.vhd
index 71eff608606fd9bf55bedb065f471534b7f9b11d..0483ba63db5eb417cc5326c8129503b4ba44a0b4 100644
--- a/libraries/technology/fifo/tech_fifo_component_pkg.vhd
+++ b/libraries/technology/fifo/tech_fifo_component_pkg.vhd
@@ -1,4 +1,3 @@
-<<<<<<< HEAD
-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
@@ -288,7 +287,7 @@ package tech_fifo_component_pkg is
);
end component;
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
-- ip_arria10_e2sg
-----------------------------------------------------------------------------
@@ -353,425 +352,67 @@ package tech_fifo_component_pkg is
);
end component;
+ -----------------------------------------------------------------------------
+ -- ip_ultrascale
+ -----------------------------------------------------------------------------
+
+ component ip_ultrascale_fifo_sc is
+ generic (
+ g_dat_w : natural := 20;
+ g_nof_words : natural := 1024
+ );
+ port (
+ aclr : in std_logic ;
+ clock : in std_logic ;
+ data : in std_logic_vector (g_dat_w - 1 downto 0);
+ rdreq : in std_logic ;
+ wrreq : in std_logic ;
+ empty : out std_logic ;
+ full : out std_logic ;
+ q : out std_logic_vector (g_dat_w - 1 downto 0) ;
+ usedw : out std_logic_vector (tech_ceil_log2(g_nof_words) - 1 downto 0)
+ );
+ end component;
+
+ component ip_ultrascale_fifo_dc is
+ generic (
+ g_dat_w : natural := 20;
+ g_nof_words : natural := 1024
+ );
+ port (
+ aclr : in std_logic := '0';
+ data : in std_logic_vector (g_dat_w - 1 downto 0);
+ rdclk : in std_logic ;
+ rdreq : in std_logic ;
+ wrclk : in std_logic ;
+ wrreq : in std_logic ;
+ q : out std_logic_vector (g_dat_w - 1 downto 0);
+ rdempty : out std_logic ;
+ rdusedw : out std_logic_vector (tech_ceil_log2(g_nof_words) - 1 downto 0);
+ wrfull : out std_logic ;
+ wrusedw : out std_logic_vector (tech_ceil_log2(g_nof_words) - 1 downto 0)
+ );
+ end component;
+
+ component ip_ultrascale_fifo_dc_mixed_widths is
+ generic (
+ g_nof_words : natural := 1024; -- FIFO size in nof wr_dat words
+ g_wrdat_w : natural := 20;
+ g_rddat_w : natural := 10
+ );
+ port (
+ aclr : in std_logic := '0';
+ data : in std_logic_vector (g_wrdat_w - 1 downto 0);
+ rdclk : in std_logic ;
+ rdreq : in std_logic ;
+ wrclk : in std_logic ;
+ wrreq : in std_logic ;
+ q : out std_logic_vector (g_rddat_w - 1 downto 0);
+ rdempty : out std_logic ;
+ rdusedw : out std_logic_vector (tech_ceil_log2(g_nof_words * g_wrdat_w / g_rddat_w) - 1 downto 0);
+ wrfull : out std_logic ;
+ wrusedw : out std_logic_vector (tech_ceil_log2(g_nof_words) - 1 downto 0)
+ );
+ end component;
-end tech_fifo_component_pkg;
-=======
--------------------------------------------------------------------------------
---
--- Copyright (C) 2014
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
--- Purpose: IP components declarations for various devices that get wrapped by the tech components
-
-LIBRARY IEEE, technology_lib;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE technology_lib.technology_pkg.ALL;
-
-PACKAGE tech_fifo_component_pkg IS
-
- -----------------------------------------------------------------------------
- -- ip_stratixiv
- -----------------------------------------------------------------------------
-
- COMPONENT ip_stratixiv_fifo_sc IS
- GENERIC (
- g_use_eab : STRING := "ON";
- g_dat_w : NATURAL;
- g_nof_words : NATURAL
- );
- PORT (
- aclr : IN STD_LOGIC;
- clock : IN STD_LOGIC;
- data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdreq : IN STD_LOGIC;
- wrreq : IN STD_LOGIC;
- empty : OUT STD_LOGIC;
- full : OUT STD_LOGIC;
- q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- usedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
- );
- END COMPONENT;
-
- COMPONENT ip_stratixiv_fifo_dc IS
- GENERIC (
- g_dat_w : NATURAL;
- g_nof_words : NATURAL
- );
- PORT (
- aclr : IN STD_LOGIC := '0';
- data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdclk : IN STD_LOGIC;
- rdreq : IN STD_LOGIC;
- wrclk : IN STD_LOGIC;
- wrreq : IN STD_LOGIC;
- q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdempty : OUT STD_LOGIC;
- rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
- wrfull : OUT STD_LOGIC;
- wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
- );
- END COMPONENT;
-
- COMPONENT ip_stratixiv_fifo_dc_mixed_widths IS
- GENERIC (
- g_nof_words : NATURAL; -- FIFO size in nof wr_dat words
- g_wrdat_w : NATURAL;
- g_rddat_w : NATURAL
- );
- PORT (
- aclr : IN STD_LOGIC := '0';
- data : IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
- rdclk : IN STD_LOGIC;
- rdreq : IN STD_LOGIC;
- wrclk : IN STD_LOGIC;
- wrreq : IN STD_LOGIC;
- q : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
- rdempty : OUT STD_LOGIC;
- rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
- wrfull : OUT STD_LOGIC;
- wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
- );
- END COMPONENT;
-
-
- -----------------------------------------------------------------------------
- -- ip_arria10
- -----------------------------------------------------------------------------
-
- COMPONENT ip_arria10_fifo_sc IS
- GENERIC (
- g_use_eab : STRING := "ON";
- g_dat_w : NATURAL := 20;
- g_nof_words : NATURAL := 1024
- );
- PORT (
- aclr : IN STD_LOGIC ;
- clock : IN STD_LOGIC ;
- data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdreq : IN STD_LOGIC ;
- wrreq : IN STD_LOGIC ;
- empty : OUT STD_LOGIC ;
- full : OUT STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
- usedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
- );
- END COMPONENT;
-
- COMPONENT ip_arria10_fifo_dc IS
- GENERIC (
- g_use_eab : STRING := "ON";
- g_dat_w : NATURAL := 20;
- g_nof_words : NATURAL := 1024
- );
- PORT (
- aclr : IN STD_LOGIC := '0';
- data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdclk : IN STD_LOGIC ;
- rdreq : IN STD_LOGIC ;
- wrclk : IN STD_LOGIC ;
- wrreq : IN STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdempty : OUT STD_LOGIC ;
- rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
- wrfull : OUT STD_LOGIC ;
- wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
- );
- END COMPONENT;
-
- COMPONENT ip_arria10_fifo_dc_mixed_widths IS
- GENERIC (
- g_nof_words : NATURAL := 1024; -- FIFO size in nof wr_dat words
- g_wrdat_w : NATURAL := 20;
- g_rddat_w : NATURAL := 10
- );
- PORT (
- aclr : IN STD_LOGIC := '0';
- data : IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
- rdclk : IN STD_LOGIC ;
- rdreq : IN STD_LOGIC ;
- wrclk : IN STD_LOGIC ;
- wrreq : IN STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
- rdempty : OUT STD_LOGIC ;
- rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
- wrfull : OUT STD_LOGIC ;
- wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
- );
- END COMPONENT;
-
- -----------------------------------------------------------------------------
- -- ip_arria10_e3sge3
- -----------------------------------------------------------------------------
-
- COMPONENT ip_arria10_e3sge3_fifo_sc IS
- GENERIC (
- g_use_eab : STRING := "ON";
- g_dat_w : NATURAL := 20;
- g_nof_words : NATURAL := 1024
- );
- PORT (
- aclr : IN STD_LOGIC ;
- clock : IN STD_LOGIC ;
- data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdreq : IN STD_LOGIC ;
- wrreq : IN STD_LOGIC ;
- empty : OUT STD_LOGIC ;
- full : OUT STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
- usedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
- );
- END COMPONENT;
-
- COMPONENT ip_arria10_e3sge3_fifo_dc IS
- GENERIC (
- g_use_eab : STRING := "ON";
- g_dat_w : NATURAL := 20;
- g_nof_words : NATURAL := 1024
- );
- PORT (
- aclr : IN STD_LOGIC := '0';
- data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdclk : IN STD_LOGIC ;
- rdreq : IN STD_LOGIC ;
- wrclk : IN STD_LOGIC ;
- wrreq : IN STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdempty : OUT STD_LOGIC ;
- rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
- wrfull : OUT STD_LOGIC ;
- wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
- );
- END COMPONENT;
-
- COMPONENT ip_arria10_e3sge3_fifo_dc_mixed_widths IS
- GENERIC (
- g_nof_words : NATURAL := 1024; -- FIFO size in nof wr_dat words
- g_wrdat_w : NATURAL := 20;
- g_rddat_w : NATURAL := 10
- );
- PORT (
- aclr : IN STD_LOGIC := '0';
- data : IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
- rdclk : IN STD_LOGIC ;
- rdreq : IN STD_LOGIC ;
- wrclk : IN STD_LOGIC ;
- wrreq : IN STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
- rdempty : OUT STD_LOGIC ;
- rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
- wrfull : OUT STD_LOGIC ;
- wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
- );
- END COMPONENT;
-
- -----------------------------------------------------------------------------
- -- ip_arria10_e1sg
- -----------------------------------------------------------------------------
-
- COMPONENT ip_arria10_e1sg_fifo_sc IS
- GENERIC (
- g_use_eab : STRING := "ON";
- g_dat_w : NATURAL := 20;
- g_nof_words : NATURAL := 1024
- );
- PORT (
- aclr : IN STD_LOGIC ;
- clock : IN STD_LOGIC ;
- data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdreq : IN STD_LOGIC ;
- wrreq : IN STD_LOGIC ;
- empty : OUT STD_LOGIC ;
- full : OUT STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
- usedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
- );
- END COMPONENT;
-
- COMPONENT ip_arria10_e1sg_fifo_dc IS
- GENERIC (
- g_use_eab : STRING := "ON";
- g_dat_w : NATURAL := 20;
- g_nof_words : NATURAL := 1024
- );
- PORT (
- aclr : IN STD_LOGIC := '0';
- data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdclk : IN STD_LOGIC ;
- rdreq : IN STD_LOGIC ;
- wrclk : IN STD_LOGIC ;
- wrreq : IN STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdempty : OUT STD_LOGIC ;
- rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
- wrfull : OUT STD_LOGIC ;
- wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
- );
- END COMPONENT;
-
- COMPONENT ip_arria10_e1sg_fifo_dc_mixed_widths IS
- GENERIC (
- g_nof_words : NATURAL := 1024; -- FIFO size in nof wr_dat words
- g_wrdat_w : NATURAL := 20;
- g_rddat_w : NATURAL := 10
- );
- PORT (
- aclr : IN STD_LOGIC := '0';
- data : IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
- rdclk : IN STD_LOGIC ;
- rdreq : IN STD_LOGIC ;
- wrclk : IN STD_LOGIC ;
- wrreq : IN STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
- rdempty : OUT STD_LOGIC ;
- rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
- wrfull : OUT STD_LOGIC ;
- wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
- );
- END COMPONENT;
-
- -----------------------------------------------------------------------------
- -- ip_arria10_e2sg
- -----------------------------------------------------------------------------
-
- COMPONENT ip_arria10_e2sg_fifo_sc IS
- GENERIC (
- g_use_eab : STRING := "ON";
- g_dat_w : NATURAL := 20;
- g_nof_words : NATURAL := 1024
- );
- PORT (
- aclr : IN STD_LOGIC ;
- clock : IN STD_LOGIC ;
- data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdreq : IN STD_LOGIC ;
- wrreq : IN STD_LOGIC ;
- empty : OUT STD_LOGIC ;
- full : OUT STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
- usedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
- );
- END COMPONENT;
-
- COMPONENT ip_arria10_e2sg_fifo_dc IS
- GENERIC (
- g_use_eab : STRING := "ON";
- g_dat_w : NATURAL := 20;
- g_nof_words : NATURAL := 1024
- );
- PORT (
- aclr : IN STD_LOGIC := '0';
- data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdclk : IN STD_LOGIC ;
- rdreq : IN STD_LOGIC ;
- wrclk : IN STD_LOGIC ;
- wrreq : IN STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdempty : OUT STD_LOGIC ;
- rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
- wrfull : OUT STD_LOGIC ;
- wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
- );
- END COMPONENT;
-
- COMPONENT ip_arria10_e2sg_fifo_dc_mixed_widths IS
- GENERIC (
- g_nof_words : NATURAL := 1024; -- FIFO size in nof wr_dat words
- g_wrdat_w : NATURAL := 20;
- g_rddat_w : NATURAL := 10
- );
- PORT (
- aclr : IN STD_LOGIC := '0';
- data : IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
- rdclk : IN STD_LOGIC ;
- rdreq : IN STD_LOGIC ;
- wrclk : IN STD_LOGIC ;
- wrreq : IN STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
- rdempty : OUT STD_LOGIC ;
- rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
- wrfull : OUT STD_LOGIC ;
- wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
- );
- END COMPONENT;
-
- -----------------------------------------------------------------------------
- -- ip_ultrascale
- -----------------------------------------------------------------------------
-
- COMPONENT ip_ultrascale_fifo_sc IS
- GENERIC (
- g_dat_w : NATURAL := 20;
- g_nof_words : NATURAL := 1024
- );
- PORT (
- aclr : IN STD_LOGIC ;
- clock : IN STD_LOGIC ;
- data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdreq : IN STD_LOGIC ;
- wrreq : IN STD_LOGIC ;
- empty : OUT STD_LOGIC ;
- full : OUT STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
- usedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
- );
- END COMPONENT;
-
- COMPONENT ip_ultrascale_fifo_dc IS
- GENERIC (
- g_dat_w : NATURAL := 20;
- g_nof_words : NATURAL := 1024
- );
- PORT (
- aclr : IN STD_LOGIC := '0';
- data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdclk : IN STD_LOGIC ;
- rdreq : IN STD_LOGIC ;
- wrclk : IN STD_LOGIC ;
- wrreq : IN STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdempty : OUT STD_LOGIC ;
- rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
- wrfull : OUT STD_LOGIC ;
- wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
- );
- END COMPONENT;
-
- COMPONENT ip_ultrascale_fifo_dc_mixed_widths IS
- GENERIC (
- g_nof_words : NATURAL := 1024; -- FIFO size in nof wr_dat words
- g_wrdat_w : NATURAL := 20;
- g_rddat_w : NATURAL := 10
- );
- PORT (
- aclr : IN STD_LOGIC := '0';
- data : IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
- rdclk : IN STD_LOGIC ;
- rdreq : IN STD_LOGIC ;
- wrclk : IN STD_LOGIC ;
- wrreq : IN STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
- rdempty : OUT STD_LOGIC ;
- rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
- wrfull : OUT STD_LOGIC ;
- wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
- );
- END COMPONENT;
-
-END tech_fifo_component_pkg;
->>>>>>> master
+end tech_fifo_component_pkg;
\ No newline at end of file
diff --git a/libraries/technology/fifo/tech_fifo_dc.vhd b/libraries/technology/fifo/tech_fifo_dc.vhd
index d8498b3503c3dc346fc167d2547dc173df452bdd..8deeb1216eb9fc79e6c11605fc128e263ae02f12 100644
--- a/libraries/technology/fifo/tech_fifo_dc.vhd
+++ b/libraries/technology/fifo/tech_fifo_dc.vhd
@@ -1,4 +1,3 @@
-<<<<<<< HEAD
-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
@@ -32,6 +31,7 @@ library ip_arria10_fifo_lib;
library ip_arria10_e3sge3_fifo_lib;
library ip_arria10_e1sg_fifo_lib;
library ip_arria10_e2sg_fifo_lib;
+library ip_ultrascale_fifo_lib;
entity tech_fifo_dc is
generic (
@@ -90,105 +90,10 @@ begin
port map (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
end generate;
-end architecture;
-=======
--------------------------------------------------------------------------------
---
--- Copyright (C) 2014
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
-LIBRARY ieee, technology_lib;
-USE ieee.std_logic_1164.all;
-USE work.tech_fifo_component_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
-USE technology_lib.technology_select_pkg.ALL;
-
--- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_stratixiv_fifo_lib;
-LIBRARY ip_arria10_fifo_lib;
-LIBRARY ip_arria10_e3sge3_fifo_lib;
-LIBRARY ip_arria10_e1sg_fifo_lib;
-LIBRARY ip_arria10_e2sg_fifo_lib;
-LIBRARY ip_ultrascale_fifo_lib;
-
-ENTITY tech_fifo_dc IS
- GENERIC (
- g_technology : NATURAL := c_tech_select_default;
- g_use_eab : STRING := "ON";
- g_dat_w : NATURAL;
- g_nof_words : NATURAL
- );
- PORT (
- aclr : IN STD_LOGIC := '0';
- data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdclk : IN STD_LOGIC;
- rdreq : IN STD_LOGIC;
- wrclk : IN STD_LOGIC;
- wrreq : IN STD_LOGIC;
- q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdempty : OUT STD_LOGIC;
- rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
- wrfull : OUT STD_LOGIC;
- wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
- );
-END tech_fifo_dc;
-
-
-ARCHITECTURE str OF tech_fifo_dc IS
-
-BEGIN
-
- gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
- u0 : ip_stratixiv_fifo_dc
- GENERIC MAP (g_dat_w, g_nof_words)
- PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
- END GENERATE;
-
- gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
- u0 : ip_arria10_fifo_dc
- GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
- PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
- END GENERATE;
-
- gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
- u0 : ip_arria10_e3sge3_fifo_dc
- GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
- PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
- END GENERATE;
-
- gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
- u0 : ip_arria10_e1sg_fifo_dc
- GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
- PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
- END GENERATE;
-
- gen_ip_arria10_e2sg : IF g_technology=c_tech_arria10_e2sg GENERATE
- u0 : ip_arria10_e2sg_fifo_dc
- GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
- PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
- END GENERATE;
-
- gen_ip_ultrascale : IF g_technology=c_tech_ultrascale GENERATE
- u0 : ip_ultrascale_fifo_dc
- GENERIC MAP (g_dat_w, g_nof_words)
- PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
- END GENERATE;
-
-END ARCHITECTURE;
->>>>>>> master
+ gen_ip_ultrascale : if g_technology = c_tech_ultrascale generate
+ u0 : ip_ultrascale_fifo_dc
+ generic map (g_dat_w, g_nof_words)
+ port map (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
+ end generate;
+
+end architecture;
\ No newline at end of file
diff --git a/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd b/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
index d2d738466bb192d08c52e98f1b67c7e91c3fae75..f89d0a918c365969c826309bc24b3ed5f65e8871 100644
--- a/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
+++ b/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
@@ -1,4 +1,3 @@
-<<<<<<< HEAD
-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
@@ -32,6 +31,7 @@ library ip_arria10_fifo_lib;
library ip_arria10_e3sge3_fifo_lib;
library ip_arria10_e1sg_fifo_lib;
library ip_arria10_e2sg_fifo_lib;
+library ip_ultrascale_fifo_lib;
entity tech_fifo_dc_mixed_widths is
generic (
@@ -90,105 +90,10 @@ begin
port map (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
end generate;
-end architecture;
-=======
--------------------------------------------------------------------------------
---
--- Copyright (C) 2014
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
-LIBRARY ieee, technology_lib;
-USE ieee.std_logic_1164.all;
-USE work.tech_fifo_component_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
-USE technology_lib.technology_select_pkg.ALL;
-
--- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_stratixiv_fifo_lib;
-LIBRARY ip_arria10_fifo_lib;
-LIBRARY ip_arria10_e3sge3_fifo_lib;
-LIBRARY ip_arria10_e1sg_fifo_lib;
-LIBRARY ip_arria10_e2sg_fifo_lib;
-LIBRARY ip_ultrascale_fifo_lib;
-
-ENTITY tech_fifo_dc_mixed_widths IS
- GENERIC (
- g_technology : NATURAL := c_tech_select_default;
- g_nof_words : NATURAL; -- FIFO size in nof wr_dat words
- g_wrdat_w : NATURAL;
- g_rddat_w : NATURAL
- );
- PORT (
- aclr : IN STD_LOGIC := '0';
- data : IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
- rdclk : IN STD_LOGIC;
- rdreq : IN STD_LOGIC;
- wrclk : IN STD_LOGIC;
- wrreq : IN STD_LOGIC;
- q : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
- rdempty : OUT STD_LOGIC;
- rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
- wrfull : OUT STD_LOGIC;
- wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
- );
-END tech_fifo_dc_mixed_widths;
-
-
-ARCHITECTURE str OF tech_fifo_dc_mixed_widths IS
-
-BEGIN
-
- gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
- u0 : ip_stratixiv_fifo_dc_mixed_widths
- GENERIC MAP (g_nof_words, g_wrdat_w, g_rddat_w)
- PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
- END GENERATE;
-
- gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
- u0 : ip_arria10_fifo_dc_mixed_widths
- GENERIC MAP (g_nof_words, g_wrdat_w, g_rddat_w)
- PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
- END GENERATE;
-
- gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
- u0 : ip_arria10_e3sge3_fifo_dc_mixed_widths
- GENERIC MAP (g_nof_words, g_wrdat_w, g_rddat_w)
- PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
- END GENERATE;
-
- gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
- u0 : ip_arria10_e1sg_fifo_dc_mixed_widths
- GENERIC MAP (g_nof_words, g_wrdat_w, g_rddat_w)
- PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
- END GENERATE;
-
- gen_ip_arria10_e2sg : IF g_technology=c_tech_arria10_e2sg GENERATE
- u0 : ip_arria10_e2sg_fifo_dc_mixed_widths
- GENERIC MAP (g_nof_words, g_wrdat_w, g_rddat_w)
- PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
- END GENERATE;
-
- gen_ip_ultrascale : IF g_technology=c_tech_ultrascale GENERATE
- u0 : ip_ultrascale_fifo_dc_mixed_widths
- GENERIC MAP (g_nof_words, g_wrdat_w, g_rddat_w)
- PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
- END GENERATE;
-
-END ARCHITECTURE;
->>>>>>> master
+ gen_ip_ultrascale : if g_technology = c_tech_ultrascale generate
+ u0 : ip_ultrascale_fifo_dc_mixed_widths
+ generic map (g_nof_words, g_wrdat_w, g_rddat_w)
+ port map (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
+ end generate;
+
+end architecture;
\ No newline at end of file
diff --git a/libraries/technology/fifo/tech_fifo_sc.vhd b/libraries/technology/fifo/tech_fifo_sc.vhd
index 275e5eafd6c99850edce7739ad16701c7f4e385c..96f625e82700edf5fed6a3648317122afa0f69ca 100644
--- a/libraries/technology/fifo/tech_fifo_sc.vhd
+++ b/libraries/technology/fifo/tech_fifo_sc.vhd
@@ -1,4 +1,3 @@
-<<<<<<< HEAD
-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
@@ -32,6 +31,7 @@ library ip_arria10_fifo_lib;
library ip_arria10_e3sge3_fifo_lib;
library ip_arria10_e1sg_fifo_lib;
library ip_arria10_e2sg_fifo_lib;
+library ip_ultrascale_fifo_lib;
entity tech_fifo_sc is
generic (
@@ -88,103 +88,10 @@ begin
port map (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
end generate;
-end architecture;
-=======
--------------------------------------------------------------------------------
---
--- Copyright (C) 2014
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
-LIBRARY ieee, technology_lib;
-USE ieee.std_logic_1164.all;
-USE work.tech_fifo_component_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
-USE technology_lib.technology_select_pkg.ALL;
-
--- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_stratixiv_fifo_lib;
-LIBRARY ip_arria10_fifo_lib;
-LIBRARY ip_arria10_e3sge3_fifo_lib;
-LIBRARY ip_arria10_e1sg_fifo_lib;
-LIBRARY ip_arria10_e2sg_fifo_lib;
-LIBRARY ip_ultrascale_fifo_lib;
-
-ENTITY tech_fifo_sc IS
- GENERIC (
- g_technology : NATURAL := c_tech_select_default;
- g_use_eab : STRING := "ON";
- g_dat_w : NATURAL;
- g_nof_words : NATURAL
- );
- PORT (
- aclr : IN STD_LOGIC;
- clock : IN STD_LOGIC;
- data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdreq : IN STD_LOGIC;
- wrreq : IN STD_LOGIC;
- empty : OUT STD_LOGIC;
- full : OUT STD_LOGIC;
- q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- usedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
- );
-END tech_fifo_sc;
-
-
-ARCHITECTURE str OF tech_fifo_sc IS
-
-BEGIN
-
- gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
- u0 : ip_stratixiv_fifo_sc
- GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
- PORT MAP (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
- END GENERATE;
-
- gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
- u0 : ip_arria10_fifo_sc
- GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
- PORT MAP (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
- END GENERATE;
-
- gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
- u0 : ip_arria10_e3sge3_fifo_sc
- GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
- PORT MAP (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
- END GENERATE;
-
- gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
- u0 : ip_arria10_e1sg_fifo_sc
- GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
- PORT MAP (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
- END GENERATE;
-
- gen_ip_arria10_e2sg : IF g_technology=c_tech_arria10_e2sg GENERATE
- u0 : ip_arria10_e2sg_fifo_sc
- GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
- PORT MAP (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
- END GENERATE;
-
- gen_ip_ultrascale : IF g_technology=c_tech_ultrascale GENERATE
- u0 : ip_ultrascale_fifo_sc
- GENERIC MAP (g_dat_w, g_nof_words)
- PORT MAP (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
- END GENERATE;
-
-END ARCHITECTURE;
->>>>>>> master
+ gen_ip_ultrascale : if g_technology = c_tech_ultrascale generate
+ u0 : ip_ultrascale_fifo_sc
+ generic map (g_dat_w, g_nof_words)
+ port map (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
+ end generate;
+
+end architecture;
\ No newline at end of file
diff --git a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens_component_pkg.vhd b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens_component_pkg.vhd
index 6c984db2000da0a5a34511719ecf331862bc0cd0..e3e1fca9a848de99316a951597030e73cec9dd20 100644
--- a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens_component_pkg.vhd
+++ b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens_component_pkg.vhd
@@ -62,4 +62,4 @@ package tech_fpga_temp_sens_component_pkg is
);
end component;
-end tech_fpga_temp_sens_component_pkg;
+end tech_fpga_temp_sens_component_pkg;
\ No newline at end of file
diff --git a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens_component_pkg.vhd b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens_component_pkg.vhd
index 092840e9e0cf5fdfaa3360432350a270d9c1f6e6..53ba20b1e0fc972be0f269e5d0338913906a4508 100644
--- a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens_component_pkg.vhd
+++ b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens_component_pkg.vhd
@@ -98,4 +98,4 @@ package tech_fpga_voltage_sens_component_pkg is
);
end component;
-end tech_fpga_voltage_sens_component_pkg;
+end tech_fpga_voltage_sens_component_pkg;
\ No newline at end of file
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
index ea8152f0d2a3f499df044b693ef258639398f6b7..dc678d15cfea0b5087b0d6949c969ebc29852bb9 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
@@ -101,4 +101,4 @@ begin
);
end generate;
-end architecture;
+end architecture;
\ No newline at end of file
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_component_pkg.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_component_pkg.vhd
index 48678650c102e6cbe4ac06186ad6e949d4ef9d0e..4a9856c732e6271c434e078d0612fdbb4ba6e9fc 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_component_pkg.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_component_pkg.vhd
@@ -150,4 +150,4 @@ package tech_fractional_pll_component_pkg is
);
end component;
-end tech_fractional_pll_component_pkg;
+end tech_fractional_pll_component_pkg;
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10/eth_10g/ip_arria10_eth_10g.vhd b/libraries/technology/ip_arria10/eth_10g/ip_arria10_eth_10g.vhd
index d9afda9e0a98d213fb9ca4ec16702e095b9ece52..07d3900c04c881f2c37bbeb6be0bc4c1e9c1588d 100644
--- a/libraries/technology/ip_arria10/eth_10g/ip_arria10_eth_10g.vhd
+++ b/libraries/technology/ip_arria10/eth_10g/ip_arria10_eth_10g.vhd
@@ -136,8 +136,8 @@ end ip_arria10_eth_10g;
architecture str of ip_arria10_eth_10g is
-- Enable or disable the conditions that must be ok to release tx_snk_out_arr xon
- constant c_check_link_status : boolean := g_direction /="TX_ONLY ";
- constant c_check_xgmii_tx_ready : boolean := g_direction /="RX_ONLY ";
+ constant c_check_link_status : boolean := g_direction /="TX_ONLY ";
+ constant c_check_xgmii_tx_ready : boolean := g_direction /="RX_ONLY ";
signal i_tx_snk_out_arr : t_dp_siso_arr(g_nof_channels - 1 downto 0);
@@ -185,7 +185,7 @@ begin
if c_check_xgmii_tx_ready = TRUE then v_xgmii_tx_ready := xgmii_tx_ready_arr(I); end if;
-- Now apply the conditions to xon
- if v_xgmii_tx_ready = '1' and v_xgmii_link_status ="00 " then
+ if v_xgmii_tx_ready = '1' and v_xgmii_link_status ="00 " then
i_tx_snk_out_arr(I).xon <= '1'; -- XON when Tx PHY is ready and XGMII is ok
end if;
end if;
@@ -223,7 +223,7 @@ begin
);
end generate;
- xgmii_internal_dc_arr <= xgmii_tx_dc_arr when g_direction ="TX_ONLY " else xgmii_rx_dc_arr;
+ xgmii_internal_dc_arr <= xgmii_tx_dc_arr when g_direction ="TX_ONLY " else xgmii_rx_dc_arr;
u_tech_10gbase_r : entity tech_10gbase_r_lib.tech_10gbase_r
generic map (
diff --git a/libraries/technology/ip_arria10/mult/ip_arria10_mult_rtl.vhd b/libraries/technology/ip_arria10/mult/ip_arria10_mult_rtl.vhd
index 849b024552d63c062d239e49013aa8450d454879..39be77565c9326ced1fa94af0b7b7db6fab4a616 100644
--- a/libraries/technology/ip_arria10/mult/ip_arria10_mult_rtl.vhd
+++ b/libraries/technology/ip_arria10/mult/ip_arria10_mult_rtl.vhd
@@ -116,7 +116,7 @@ begin
gen_mult : for I in 0 to g_nof_mult - 1 generate
nxt_prod((I + 1) * c_prod_w - 1 downto I * c_prod_w) <=
- std_logic_vector( signed(inp_a((I + 1) * g_in_a_w - 1 downto I * g_in_a_w)) * signed(inp_b((I + 1) * g_in_b_w - 1 downto I * g_in_b_w))) when g_representation ="signed " else
+ std_logic_vector( signed(inp_a((I + 1) * g_in_a_w - 1 downto I * g_in_a_w)) * signed(inp_b((I + 1) * g_in_b_w - 1 downto I * g_in_b_w))) when g_representation ="signed " else
std_logic_vector(unsigned(inp_a((I + 1) * g_in_a_w - 1 downto I * g_in_a_w)) * unsigned(inp_b((I + 1) * g_in_b_w - 1 downto I * g_in_b_w)));
end generate;
diff --git a/libraries/technology/ip_arria10/ram/ip_arria10_ram_crwk_crw.vhd b/libraries/technology/ip_arria10/ram/ip_arria10_ram_crwk_crw.vhd
index 27394129fe138f1fc870ae4a6cb01cad924bfadb..9ee5672052ebc952ae8e52e93109a1ac52dd16cd 100644
--- a/libraries/technology/ip_arria10/ram/ip_arria10_ram_crwk_crw.vhd
+++ b/libraries/technology/ip_arria10/ram/ip_arria10_ram_crwk_crw.vhd
@@ -138,4 +138,4 @@ begin
q_b => q_b
);
-end SYN;
+end SYN;
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10/ram/ip_arria10_simple_dual_port_ram_single_clock.vhd b/libraries/technology/ip_arria10/ram/ip_arria10_simple_dual_port_ram_single_clock.vhd
index 6c79ed58e7712822decc81161c603f56e66a9974..e14a9f1e866d0860224997a3dc432ae2c5b1562f 100644
--- a/libraries/technology/ip_arria10/ram/ip_arria10_simple_dual_port_ram_single_clock.vhd
+++ b/libraries/technology/ip_arria10/ram/ip_arria10_simple_dual_port_ram_single_clock.vhd
@@ -72,4 +72,4 @@ begin
end if;
end process;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy.vhd b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy.vhd
index 4cb760cf16dd375a869d5944d9b74278c25198ad..e0cc256343e41d6d1e245ffd7159312985345045 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy.vhd
@@ -116,4 +116,4 @@ begin
--vhdl renameroo for output signals
readdata <= internal_readdata;
-end europa;
+end europa;
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_180_xymx6za.vhd b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_180_xymx6za.vhd
index 75ebce007e1db793fd50176191e16ae41af1fa08..5a8cb5a23aeebe2e54561e81fa49862260a59575 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_180_xymx6za.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_180_xymx6za.vhd
@@ -116,4 +116,4 @@ begin
--vhdl renameroo for output signals
readdata <= internal_readdata;
-end europa;
+end europa;
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400_inst.vhd b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400_inst.vhd
index bc9c643d3f90e90240dc15c5dc377f23301c82c7..16e51d04dfe22f73d21a6b8bd5881fed03e7f87a 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400_inst.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400_inst.vhd
@@ -69,4 +69,4 @@
pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk_clock_sink.clk
local_cal_success => CONNECTED_TO_local_cal_success, -- status_conduit_end.local_cal_success
local_cal_fail => CONNECTED_TO_local_cal_fail -- .local_cal_fail
- );
+ );
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e1sg/eth_10g/ip_arria10_e1sg_eth_10g.vhd b/libraries/technology/ip_arria10_e1sg/eth_10g/ip_arria10_e1sg_eth_10g.vhd
index 08bda8fba262d6ec76a73626c29013dc82e6b3bb..fb9930b6b0e6289e7cb0708cf7974ced66dcca77 100644
--- a/libraries/technology/ip_arria10_e1sg/eth_10g/ip_arria10_e1sg_eth_10g.vhd
+++ b/libraries/technology/ip_arria10_e1sg/eth_10g/ip_arria10_e1sg_eth_10g.vhd
@@ -191,7 +191,7 @@ begin
if c_check_xgmii_tx_ready = TRUE then v_xgmii_tx_ready := xgmii_tx_ready_arr(I); end if;
-- Now apply the conditions to xon
- if v_xgmii_tx_ready = '1' and v_xgmii_link_status ="00 " then
+ if v_xgmii_tx_ready = '1' and v_xgmii_link_status ="00 " then
i_tx_snk_out_arr(I).xon <= '1'; -- XON when Tx PHY is ready and XGMII is ok
end if;
end if;
@@ -229,7 +229,7 @@ begin
);
end generate;
- xgmii_internal_dc_arr <= xgmii_tx_dc_arr when g_direction ="TX_ONLY " else xgmii_rx_dc_arr;
+ xgmii_internal_dc_arr <= xgmii_tx_dc_arr when g_direction ="TX_ONLY " else xgmii_rx_dc_arr;
u_tech_10gbase_r : entity tech_10gbase_r_lib.tech_10gbase_r
generic map (
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
index 4448ba392bfd3122858cc77a84ebbf1a4fa21a21..2f9616f27406222c89da421d189208e481efffd1 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
@@ -526,5 +526,4 @@ begin
miso_arr => jesd204b_miso_arr
);
-end str;
-
+end str;
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.vhd
index f9e439242f41ac8bdf3fa0af47ed077a63259f34..2dac63cceb0e250b55544a8ed5441515ae26b0cb 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.vhd
@@ -138,4 +138,4 @@ begin
q_b => q_b
);
-end SYN;
+end SYN;
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw/ip_arria10_e1sg_ram_crwk_crw_inst.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw/ip_arria10_e1sg_ram_crwk_crw_inst.vhd
index 4e479e24d872cc3bc9f399f7acd4562865d86381..28e4212299d0eb29221ec347c9f437a6f58b34da 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw/ip_arria10_e1sg_ram_crwk_crw_inst.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw/ip_arria10_e1sg_ram_crwk_crw_inst.vhd
@@ -29,4 +29,4 @@
rden_b => CONNECTED_TO_rden_b, -- .rden_b
q_a => CONNECTED_TO_q_a, -- ram_output.dataout_a
q_b => CONNECTED_TO_q_b -- .dataout_b
- );
+ );
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw/ram_2port_170/sim/ip_arria10_e1sg_ram_crwk_crw_ram_2port_170_qaianri.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw/ram_2port_170/sim/ip_arria10_e1sg_ram_crwk_crw_ram_2port_170_qaianri.vhd
index 0195e45b1ccc94965380e33815d42dc416a77bdd..2a4eebc154f16bb185044c56fd91ac7894adaab8 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw/ram_2port_170/sim/ip_arria10_e1sg_ram_crwk_crw_ram_2port_170_qaianri.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw/ram_2port_170/sim/ip_arria10_e1sg_ram_crwk_crw_ram_2port_170_qaianri.vhd
@@ -95,4 +95,4 @@ begin
-end SYN;
+end SYN;
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_simple_dual_port_ram_single_clock.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_simple_dual_port_ram_single_clock.vhd
index 60c03373d7fc0320df44e4de60ebbe98e22dc81e..a2236c35e559c770dbad57ffea38a7d0aa3e2cc1 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_simple_dual_port_ram_single_clock.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_simple_dual_port_ram_single_clock.vhd
@@ -72,4 +72,4 @@ begin
end if;
end process;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3_inst.vhd b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3_inst.vhd
index e657271557d8e4e95cd72d19f2d643738e7bec32..854ca2f6f193dc52466d2f80a4ccb440d5e79d89 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3_inst.vhd
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3_inst.vhd
@@ -33,4 +33,4 @@
tx_cal_busy => CONNECTED_TO_tx_cal_busy, -- tx_cal_busy.tx_cal_busy
tx_digitalreset => CONNECTED_TO_tx_digitalreset, -- tx_digitalreset.tx_digitalreset
tx_ready => CONNECTED_TO_tx_ready -- tx_ready.tx_ready
- );
+ );
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600_inst.vhd b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600_inst.vhd
index 3e681c55b81121a371e47ad70c127d51b59ba67b..e17ee5e535f532a4ea6850d58872465848174aeb 100644
--- a/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600_inst.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600_inst.vhd
@@ -87,4 +87,4 @@
mmr_slave_burstcount_0 => CONNECTED_TO_mmr_slave_burstcount_0, -- .burstcount
mmr_slave_beginbursttransfer_0 => CONNECTED_TO_mmr_slave_beginbursttransfer_0, -- .beginbursttransfer
mmr_slave_readdatavalid_0 => CONNECTED_TO_mmr_slave_readdatavalid_0 -- .readdatavalid
- );
+ );
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e2sg/eth_10g/ip_arria10_e2sg_eth_10g.vhd b/libraries/technology/ip_arria10_e2sg/eth_10g/ip_arria10_e2sg_eth_10g.vhd
index 8cd46fb79b088b5bbee7db432e48d458c5f7a0f7..6f119c2df97d9dd9598e6cc238745f88c8e19c7c 100644
--- a/libraries/technology/ip_arria10_e2sg/eth_10g/ip_arria10_e2sg_eth_10g.vhd
+++ b/libraries/technology/ip_arria10_e2sg/eth_10g/ip_arria10_e2sg_eth_10g.vhd
@@ -191,7 +191,7 @@ begin
if c_check_xgmii_tx_ready = TRUE then v_xgmii_tx_ready := xgmii_tx_ready_arr(I); end if;
-- Now apply the conditions to xon
- if v_xgmii_tx_ready = '1' and v_xgmii_link_status ="00 " then
+ if v_xgmii_tx_ready = '1' and v_xgmii_link_status ="00 " then
i_tx_snk_out_arr(I).xon <= '1'; -- XON when Tx PHY is ready and XGMII is ok
end if;
end if;
@@ -229,7 +229,7 @@ begin
);
end generate;
- xgmii_internal_dc_arr <= xgmii_tx_dc_arr when g_direction ="TX_ONLY " else xgmii_rx_dc_arr;
+ xgmii_internal_dc_arr <= xgmii_tx_dc_arr when g_direction ="TX_ONLY " else xgmii_rx_dc_arr;
u_tech_10gbase_r : entity tech_10gbase_r_lib.tech_10gbase_r
generic map (
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
index def1bc468886ad33a7e9c7b624e1a8b3f1c9138d..9899e63bddce2c8875b2bf6c94dd0d7529423458 100644
--- a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
@@ -526,5 +526,4 @@ begin
miso_arr => jesd204b_miso_arr
);
-end str;
-
+end str;
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw_inst.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw_inst.vhd
index 70f064f953304adcb7a676d2de45349cfd99cfc8..d2b05270900ca221022a14d76464c5cd09fab736 100644
--- a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw_inst.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw_inst.vhd
@@ -25,4 +25,4 @@
wren_b => CONNECTED_TO_wren_b, -- wren_b.wren_b
clock_a => CONNECTED_TO_clock_a, -- clock_a.clk
clock_b => CONNECTED_TO_clock_b -- clock_b.clk
- );
+ );
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ram_2port_2000/sim/ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ram_2port_2000/sim/ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey.vhd
index 050a75b17a8f365d2a836a492a68e0ac5ad9b3e2..ef0bf09adcf3c91103fb846ec5f634b218c86427 100644
--- a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ram_2port_2000/sim/ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ram_2port_2000/sim/ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey.vhd
@@ -90,4 +90,4 @@ begin
-end SYN;
+end SYN;
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crwk_crw.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crwk_crw.vhd
index 4342b44b5b5b5f429344637eae7440eadadfa006..3fbfbda2ba0a11cfc35715118a881bb0b7224841 100644
--- a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crwk_crw.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crwk_crw.vhd
@@ -138,4 +138,4 @@ begin
q_b => q_b
);
-end SYN;
+end SYN;
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_simple_dual_port_ram_single_clock.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_simple_dual_port_ram_single_clock.vhd
index 50df8cac1fa49f979d061e6ff1f71ddab37dcf29..45f392f38661fe728be8956454a7aa5df6f6040e 100644
--- a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_simple_dual_port_ram_single_clock.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_simple_dual_port_ram_single_clock.vhd
@@ -72,4 +72,4 @@ begin
end if;
end process;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e3sge3/eth_10g/ip_arria10_e3sge3_eth_10g.vhd b/libraries/technology/ip_arria10_e3sge3/eth_10g/ip_arria10_e3sge3_eth_10g.vhd
index 954b4070ca86d12cb4107b5e430da5488c2b11c8..f7fbcecd76cd71c260baf2bc806eece4e43742df 100644
--- a/libraries/technology/ip_arria10_e3sge3/eth_10g/ip_arria10_e3sge3_eth_10g.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/eth_10g/ip_arria10_e3sge3_eth_10g.vhd
@@ -140,8 +140,8 @@ end ip_arria10_e3sge3_eth_10g;
architecture str of ip_arria10_e3sge3_eth_10g is
-- Enable or disable the conditions that must be ok to release tx_snk_out_arr xon
- constant c_check_link_status : boolean := g_direction /="TX_ONLY ";
- constant c_check_xgmii_tx_ready : boolean := g_direction /="RX_ONLY ";
+ constant c_check_link_status : boolean := g_direction /="TX_ONLY ";
+ constant c_check_xgmii_tx_ready : boolean := g_direction /="RX_ONLY ";
signal i_tx_snk_out_arr : t_dp_siso_arr(g_nof_channels - 1 downto 0);
@@ -189,7 +189,7 @@ begin
if c_check_xgmii_tx_ready = TRUE then v_xgmii_tx_ready := xgmii_tx_ready_arr(I); end if;
-- Now apply the conditions to xon
- if v_xgmii_tx_ready = '1' and v_xgmii_link_status ="00 " then
+ if v_xgmii_tx_ready = '1' and v_xgmii_link_status ="00 " then
i_tx_snk_out_arr(I).xon <= '1'; -- XON when Tx PHY is ready and XGMII is ok
end if;
end if;
@@ -227,7 +227,7 @@ begin
);
end generate;
- xgmii_internal_dc_arr <= xgmii_tx_dc_arr when g_direction ="TX_ONLY " else xgmii_rx_dc_arr;
+ xgmii_internal_dc_arr <= xgmii_tx_dc_arr when g_direction ="TX_ONLY " else xgmii_rx_dc_arr;
u_tech_10gbase_r : entity tech_10gbase_r_lib.tech_10gbase_r
generic map (
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crwk_crw.vhd b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crwk_crw.vhd
index eaf615e5c92df35e3e93105c39ddfd613ceb4d1e..dc243ea844bdd38c29016d6ed01383f1c6bd6520 100644
--- a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crwk_crw.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crwk_crw.vhd
@@ -138,4 +138,4 @@ begin
q_b => q_b
);
-end SYN;
+end SYN;
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_simple_dual_port_ram_single_clock.vhd b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_simple_dual_port_ram_single_clock.vhd
index 1a898cb6728543af4e30b5e57bf5416347690502..8b61f85ddd2bff56c65220ffc8e4750fda62e8c5 100644
--- a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_simple_dual_port_ram_single_clock.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_simple_dual_port_ram_single_clock.vhd
@@ -72,4 +72,4 @@ begin
end if;
end process;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/technology/ip_stratixiv/eth_10g/ip_stratixiv_eth_10g.vhd b/libraries/technology/ip_stratixiv/eth_10g/ip_stratixiv_eth_10g.vhd
index fcf4f7a9adcfc75587bdeb70c401ea3020e75d1f..f4772112e8bb99623d1ae6fb431a1d1179a12f47 100644
--- a/libraries/technology/ip_stratixiv/eth_10g/ip_stratixiv_eth_10g.vhd
+++ b/libraries/technology/ip_stratixiv/eth_10g/ip_stratixiv_eth_10g.vhd
@@ -134,9 +134,9 @@ end ip_stratixiv_eth_10g;
architecture str of ip_stratixiv_eth_10g is
-- Enable or disable the conditions that must be ok to release tx_snk_out_arr xon
- constant c_check_link_status : boolean := g_direction /="TX_ONLY ";
- constant c_check_rx_channelaligned : boolean := g_direction /="TX_ONLY ";
- constant c_check_xgmii_tx_ready : boolean := g_direction /="RX_ONLY ";
+ constant c_check_link_status : boolean := g_direction /="TX_ONLY ";
+ constant c_check_rx_channelaligned : boolean := g_direction /="TX_ONLY ";
+ constant c_check_xgmii_tx_ready : boolean := g_direction /="RX_ONLY ";
-- MAG_10G control status registers
signal mac_mosi_arr : t_mem_mosi_arr(g_nof_channels - 1 downto 0);
@@ -168,8 +168,8 @@ begin
tx_rst_arr_out <= i_tx_rst_arr_out;
rx_rst_arr_out <= i_rx_rst_arr_out;
- i_tx_rst_arr_out <= not txc_tx_ready_arr when g_direction /="RX_ONLY " else i_rx_rst_arr_out; -- in case of RX_ONLY use the rx rst also for tx to have an active rst release, clock domain crossing issues can be ignored
- i_rx_rst_arr_out <= not rxc_rx_ready_arr when g_direction /="TX_ONLY " else i_tx_rst_arr_out; -- in case of TX_ONLY use the tx rst also for rx to have an active rst release, clock domain crossing issues can be ignored
+ i_tx_rst_arr_out <= not txc_tx_ready_arr when g_direction /="RX_ONLY " else i_rx_rst_arr_out; -- in case of RX_ONLY use the rx rst also for tx to have an active rst release, clock domain crossing issues can be ignored
+ i_rx_rst_arr_out <= not rxc_rx_ready_arr when g_direction /="TX_ONLY " else i_tx_rst_arr_out; -- in case of TX_ONLY use the tx rst also for rx to have an active rst release, clock domain crossing issues can be ignored
xgmii_tx_ready_arr <= txc_tx_ready_arr;
@@ -191,7 +191,7 @@ begin
if c_check_xgmii_tx_ready = TRUE then v_xgmii_tx_ready := xgmii_tx_ready_arr(I); end if;
-- Now apply the conditions to xon
- if v_xgmii_tx_ready = '1' and v_txc_rx_channelaligned = '1' and v_xgmii_link_status ="00 " then
+ if v_xgmii_tx_ready = '1' and v_txc_rx_channelaligned = '1' and v_xgmii_link_status ="00 " then
tx_snk_out_arr(I).xon <= '1'; -- XON when Tx PHY is ready and XGMII is ok
end if;
end if;
@@ -227,7 +227,7 @@ begin
);
end generate;
- xgmii_internal_dc_arr <= xgmii_tx_dc_arr when g_direction ="TX_ONLY " else xgmii_rx_dc_arr;
+ xgmii_internal_dc_arr <= xgmii_tx_dc_arr when g_direction ="TX_ONLY " else xgmii_rx_dc_arr;
u_tech_xaui : entity tech_xaui_lib.tech_xaui
generic map (
diff --git a/libraries/technology/ip_stratixiv/mult/ip_stratixiv_mult_rtl.vhd b/libraries/technology/ip_stratixiv/mult/ip_stratixiv_mult_rtl.vhd
index 231abe296937ffe357d9d82eb548c54966c73b2e..cbde1e04d2310738fa4e67b603064f58a1322041 100644
--- a/libraries/technology/ip_stratixiv/mult/ip_stratixiv_mult_rtl.vhd
+++ b/libraries/technology/ip_stratixiv/mult/ip_stratixiv_mult_rtl.vhd
@@ -116,7 +116,7 @@ begin
gen_mult : for I in 0 to g_nof_mult - 1 generate
nxt_prod((I + 1) * c_prod_w - 1 downto I * c_prod_w) <=
- std_logic_vector( signed(inp_a((I + 1) * g_in_a_w - 1 downto I * g_in_a_w)) * signed(inp_b((I + 1) * g_in_b_w - 1 downto I * g_in_b_w))) when g_representation ="signed " else
+ std_logic_vector( signed(inp_a((I + 1) * g_in_a_w - 1 downto I * g_in_a_w)) * signed(inp_b((I + 1) * g_in_b_w - 1 downto I * g_in_b_w))) when g_representation ="signed " else
std_logic_vector(unsigned(inp_a((I + 1) * g_in_a_w - 1 downto I * g_in_a_w)) * unsigned(inp_b((I + 1) * g_in_b_w - 1 downto I * g_in_b_w)));
end generate;
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/tb_ip_stratixiv_phy_xaui.vhd b/libraries/technology/ip_stratixiv/phy_xaui/tb_ip_stratixiv_phy_xaui.vhd
index b009a48afd896675bec55b310c6657caaffeaa54..10319687e6954b965896b051fa6856fc5708466e 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/tb_ip_stratixiv_phy_xaui.vhd
+++ b/libraries/technology/ip_stratixiv/phy_xaui/tb_ip_stratixiv_phy_xaui.vhd
@@ -231,4 +231,4 @@ begin
end if;
end process;
-end architecture str;
+end architecture str;
\ No newline at end of file
diff --git a/libraries/technology/ip_stratixiv/transceiver/ip_stratixiv_gxb_reconfig_v101.vhd b/libraries/technology/ip_stratixiv/transceiver/ip_stratixiv_gxb_reconfig_v101.vhd
index db128afcf847cef6eac27c96a3dadcfc42b935f2..d4f7bb4c39e62d8d6a3eeee5bd636bd98098f104 100644
--- a/libraries/technology/ip_stratixiv/transceiver/ip_stratixiv_gxb_reconfig_v101.vhd
+++ b/libraries/technology/ip_stratixiv/transceiver/ip_stratixiv_gxb_reconfig_v101.vhd
@@ -75,4 +75,4 @@ begin
);
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/technology/ip_stratixiv/transceiver/ip_stratixiv_gxb_reconfig_v111.vhd b/libraries/technology/ip_stratixiv/transceiver/ip_stratixiv_gxb_reconfig_v111.vhd
index cdb2a7f4bf0099cb7d3f487f3f67458e3b44a8a7..2d36d6af53b59fe33dfba87331178cd0a184bfd2 100644
--- a/libraries/technology/ip_stratixiv/transceiver/ip_stratixiv_gxb_reconfig_v111.vhd
+++ b/libraries/technology/ip_stratixiv/transceiver/ip_stratixiv_gxb_reconfig_v111.vhd
@@ -65,4 +65,4 @@ begin
);
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/technology/ip_stratixiv/transceiver/ip_stratixiv_gxb_reconfig_v91.vhd b/libraries/technology/ip_stratixiv/transceiver/ip_stratixiv_gxb_reconfig_v91.vhd
index e1caf0230eadce06a6156b8b1ba32cd688bc320c..213cf9ae124fa9080821d0f888244873c14e4e09 100644
--- a/libraries/technology/ip_stratixiv/transceiver/ip_stratixiv_gxb_reconfig_v91.vhd
+++ b/libraries/technology/ip_stratixiv/transceiver/ip_stratixiv_gxb_reconfig_v91.vhd
@@ -83,4 +83,4 @@ begin
);
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_dc.vhd b/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_dc.vhd
index 4b901cdef5bf50e94235112398c0e13e352e4fbb..64ec598b4fd59fb84aa5a69f1e0c4b2e9d6be045 100644
--- a/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_dc.vhd
+++ b/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_dc.vhd
@@ -1,176 +1,176 @@
--------------------------------------------------------------------------------
---
--- Copyright 2023
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- Licensed under the Apache License, Version 2.0 (the "License");
--- you may not use this file except in compliance with the License.
--- You may obtain a copy of the License at
---
--- http://www.apache.org/licenses/LICENSE-2.0
---
--- Unless required by applicable law or agreed to in writing, software
--- distributed under the License is distributed on an "AS IS" BASIS,
--- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--- See the License for the specific language governing permissions and
--- limitations under the License.
---
--------------------------------------------------------------------------------
--- Purpose: Instantiate FIFO IP with generics
--- Description:
--- Copied component instantiation from Vivado XPM template
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY technology_lib;
-USE technology_lib.technology_pkg.ALL;
-
-LIBRARY xpm;
-USE xpm.vcomponents.ALL;
-
-ENTITY ip_ultrascale_fifo_dc IS
- GENERIC (
- g_dat_w : NATURAL := 20;
- g_nof_words : NATURAL := 1024
- );
- PORT (
- aclr : IN STD_LOGIC := '0';
- data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdclk : IN STD_LOGIC ;
- rdreq : IN STD_LOGIC ;
- wrclk : IN STD_LOGIC ;
- wrreq : IN STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdempty : OUT STD_LOGIC ;
- rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
- wrfull : OUT STD_LOGIC ;
- wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
- );
-END ip_ultrascale_fifo_dc;
-
-ARCHITECTURE SYN OF ip_ultrascale_fifo_dc IS
-
-BEGIN
- -- xpm_fifo_async: Asynchronous FIFO
- -- Xilinx Parameterized Macro, version 2022.1
-
- xpm_fifo_async_inst : xpm_fifo_async
- generic map (
- CASCADE_HEIGHT => 0, -- DECIMAL
- CDC_SYNC_STAGES => 3, -- DECIMAL
- DOUT_RESET_VALUE => "0", -- String
- ECC_MODE => "no_ecc", -- String
- FIFO_MEMORY_TYPE => "auto", -- String
- FIFO_READ_LATENCY => 1, -- DECIMAL
- FIFO_WRITE_DEPTH => g_nof_words, -- DECIMAL
- FULL_RESET_VALUE => 0, -- DECIMAL
- PROG_EMPTY_THRESH => 10, -- DECIMAL
- PROG_FULL_THRESH => 10, -- DECIMAL
- RD_DATA_COUNT_WIDTH => tech_ceil_log2(g_nof_words), -- DECIMAL
- READ_DATA_WIDTH => g_dat_w, -- DECIMAL
- READ_MODE => "std", -- String
- RELATED_CLOCKS => 0, -- DECIMAL
- SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
- USE_ADV_FEATURES => "0404", -- String
- WAKEUP_TIME => 0, -- DECIMAL
- WRITE_DATA_WIDTH => g_dat_w, -- DECIMAL
- WR_DATA_COUNT_WIDTH => tech_ceil_log2(g_nof_words) -- DECIMAL
- )
- port map (
- almost_empty => OPEN, -- 1-bit output: Almost Empty : When asserted, this signal indicates that
- -- only one more read can be performed before the FIFO goes to empty.
-
- almost_full => OPEN, -- 1-bit output: Almost Full: When asserted, this signal indicates that
- -- only one more write can be performed before the FIFO is full.
-
- data_valid => OPEN, -- 1-bit output: Read Data Valid: When asserted, this signal indicates
- -- that valid data is available on the output bus (dout).
-
- dbiterr => OPEN, -- 1-bit output: Double Bit Error: Indicates that the ECC decoder
- -- detected a double-bit error and data in the FIFO core is corrupted.
-
- dout => q, -- READ_DATA_WIDTH-bit output: Read Data: The output data bus is driven
- -- when reading the FIFO.
-
- empty => rdempty, -- 1-bit output: Empty Flag: When asserted, this signal indicates that
- -- the FIFO is empty. Read requests are ignored when the FIFO is empty,
- -- initiating a read while empty is not destructive to the FIFO.
-
- full => wrfull, -- 1-bit output: Full Flag: When asserted, this signal indicates that the
- -- FIFO is full. Write requests are ignored when the FIFO is full,
- -- initiating a write when the FIFO is full is not destructive to the
- -- contents of the FIFO.
-
- overflow => OPEN, -- 1-bit output: Overflow: This signal indicates that a write request
- -- (wren) during the prior clock cycle was rejected, because the FIFO is
- -- full. Overflowing the FIFO is not destructive to the contents of the
- -- FIFO.
-
- prog_empty => OPEN, -- 1-bit output: Programmable Empty: This signal is asserted when the
- -- number of words in the FIFO is less than or equal to the programmable
- -- empty threshold value. It is de-asserted when the number of words in
- -- the FIFO exceeds the programmable empty threshold value.
-
- prog_full => OPEN, -- 1-bit output: Programmable Full: This signal is asserted when the
- -- number of words in the FIFO is greater than or equal to the
- -- programmable full threshold value. It is de-asserted when the number
- -- of words in the FIFO is less than the programmable full threshold
- -- value.
-
- rd_data_count => rdusedw, -- RD_DATA_COUNT_WIDTH-bit output: Read Data Count: This bus indicates
- -- the number of words read from the FIFO.
-
- rd_rst_busy => OPEN, -- 1-bit output: Read Reset Busy: Active-High indicator that the FIFO
- -- read domain is currently in a reset state.
-
- sbiterr => OPEN, -- 1-bit output: Single Bit Error: Indicates that the ECC decoder
- -- detected and fixed a single-bit error.
-
- underflow => OPEN, -- 1-bit output: Underflow: Indicates that the read request (rd_en)
- -- during the previous clock cycle was rejected because the FIFO is
- -- empty. Under flowing the FIFO is not destructive to the FIFO.
-
- wr_ack => OPEN, -- 1-bit output: Write Acknowledge: This signal indicates that a write
- -- request (wr_en) during the prior clock cycle is succeeded.
-
- wr_data_count => wrusedw, -- WR_DATA_COUNT_WIDTH-bit output: Write Data Count: This bus indicates
- -- the number of words written into the FIFO.
-
- wr_rst_busy => OPEN, -- 1-bit output: Write Reset Busy: Active-High indicator that the FIFO
- -- write domain is currently in a reset state.
-
- din => data, -- WRITE_DATA_WIDTH-bit input: Write Data: The input data bus used when
- -- writing the FIFO.
-
- injectdbiterr => '0', -- 1-bit input: Double Bit Error Injection: Injects a double bit error if
- -- the ECC feature is used on block RAMs or UltraRAM macros.
-
- injectsbiterr => '0', -- 1-bit input: Single Bit Error Injection: Injects a single bit error if
- -- the ECC feature is used on block RAMs or UltraRAM macros.
-
- rd_clk => rdclk, -- 1-bit input: Read clock: Used for read operation. rd_clk must be a
- -- free running clock.
-
- rd_en => rdreq, -- 1-bit input: Read Enable: If the FIFO is not empty, asserting this
- -- signal causes data (on dout) to be read from the FIFO. Must be held
- -- active-low when rd_rst_busy is active high.
-
- rst => aclr, -- 1-bit input: Reset: Must be synchronous to wr_clk. The clock(s) can be
- -- unstable at the time of applying reset, but reset must be released
- -- only after the clock(s) is/are stable.
-
- sleep => '0', -- 1-bit input: Dynamic power saving: If sleep is High, the memory/fifo
- -- block is in power saving mode.
-
- wr_clk => wrclk, -- 1-bit input: Write clock: Used for write operation. wr_clk must be a
- -- free running clock.
-
- wr_en => wrreq -- 1-bit input: Write Enable: If the FIFO is not full, asserting this
- -- signal causes data (on din) to be written to the FIFO. Must be held
- -- active-low when rst or wr_rst_busy is active high.
- );
-
- -- End of xpm_fifo_async_inst instantiation
-END SYN;
+-------------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Purpose: Instantiate FIFO IP with generics
+-- Description:
+-- Copied component instantiation from Vivado XPM template
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library technology_lib;
+use technology_lib.technology_pkg.all;
+
+library xpm;
+use xpm.vcomponents.all;
+
+entity ip_ultrascale_fifo_dc is
+ generic (
+ g_dat_w : natural := 20;
+ g_nof_words : natural := 1024
+ );
+ port (
+ aclr : in std_logic := '0';
+ data : in std_logic_vector (g_dat_w - 1 downto 0);
+ rdclk : in std_logic ;
+ rdreq : in std_logic ;
+ wrclk : in std_logic ;
+ wrreq : in std_logic ;
+ q : out std_logic_vector (g_dat_w - 1 downto 0);
+ rdempty : out std_logic ;
+ rdusedw : out std_logic_vector (tech_ceil_log2(g_nof_words) - 1 downto 0);
+ wrfull : out std_logic ;
+ wrusedw : out std_logic_vector (tech_ceil_log2(g_nof_words) - 1 downto 0)
+ );
+end ip_ultrascale_fifo_dc;
+
+architecture SYN of ip_ultrascale_fifo_dc is
+
+begin
+ -- xpm_fifo_async: Asynchronous FIFO
+ -- Xilinx Parameterized Macro, version 2022.1
+
+ xpm_fifo_async_inst : xpm_fifo_async
+ generic map (
+ CASCADE_HEIGHT => 0, -- DECIMAL
+ CDC_SYNC_STAGES => 3, -- DECIMAL
+ DOUT_RESET_VALUE => "0", -- String
+ ECC_MODE => "no_ecc", -- String
+ FIFO_MEMORY_TYPE => "auto", -- String
+ FIFO_READ_LATENCY => 1, -- DECIMAL
+ FIFO_WRITE_DEPTH => g_nof_words, -- DECIMAL
+ FULL_RESET_VALUE => 0, -- DECIMAL
+ PROG_EMPTY_THRESH => 10, -- DECIMAL
+ PROG_FULL_THRESH => 10, -- DECIMAL
+ RD_DATA_COUNT_WIDTH => tech_ceil_log2(g_nof_words), -- DECIMAL
+ READ_DATA_WIDTH => g_dat_w, -- DECIMAL
+ READ_MODE => "std", -- String
+ RELATED_CLOCKS => 0, -- DECIMAL
+ SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+ USE_ADV_FEATURES => "0404", -- String
+ WAKEUP_TIME => 0, -- DECIMAL
+ WRITE_DATA_WIDTH => g_dat_w, -- DECIMAL
+ WR_DATA_COUNT_WIDTH => tech_ceil_log2(g_nof_words) -- DECIMAL
+ )
+ port map (
+ almost_empty => open, -- 1-bit output: Almost Empty : When asserted, this signal indicates that
+ -- only one more read can be performed before the FIFO goes to empty.
+
+ almost_full => open, -- 1-bit output: Almost Full: When asserted, this signal indicates that
+ -- only one more write can be performed before the FIFO is full.
+
+ data_valid => open, -- 1-bit output: Read Data Valid: When asserted, this signal indicates
+ -- that valid data is available on the output bus (dout).
+
+ dbiterr => open, -- 1-bit output: Double Bit Error: Indicates that the ECC decoder
+ -- detected a double-bit error and data in the FIFO core is corrupted.
+
+ dout => q, -- READ_DATA_WIDTH-bit output: Read Data: The output data bus is driven
+ -- when reading the FIFO.
+
+ empty => rdempty, -- 1-bit output: Empty Flag: When asserted, this signal indicates that
+ -- the FIFO is empty. Read requests are ignored when the FIFO is empty,
+ -- initiating a read while empty is not destructive to the FIFO.
+
+ full => wrfull, -- 1-bit output: Full Flag: When asserted, this signal indicates that the
+ -- FIFO is full. Write requests are ignored when the FIFO is full,
+ -- initiating a write when the FIFO is full is not destructive to the
+ -- contents of the FIFO.
+
+ overflow => open, -- 1-bit output: Overflow: This signal indicates that a write request
+ -- (wren) during the prior clock cycle was rejected, because the FIFO is
+ -- full. Overflowing the FIFO is not destructive to the contents of the
+ -- FIFO.
+
+ prog_empty => open, -- 1-bit output: Programmable Empty: This signal is asserted when the
+ -- number of words in the FIFO is less than or equal to the programmable
+ -- empty threshold value. It is de-asserted when the number of words in
+ -- the FIFO exceeds the programmable empty threshold value.
+
+ prog_full => open, -- 1-bit output: Programmable Full: This signal is asserted when the
+ -- number of words in the FIFO is greater than or equal to the
+ -- programmable full threshold value. It is de-asserted when the number
+ -- of words in the FIFO is less than the programmable full threshold
+ -- value.
+
+ rd_data_count => rdusedw, -- RD_DATA_COUNT_WIDTH-bit output: Read Data Count: This bus indicates
+ -- the number of words read from the FIFO.
+
+ rd_rst_busy => open, -- 1-bit output: Read Reset Busy: Active-High indicator that the FIFO
+ -- read domain is currently in a reset state.
+
+ sbiterr => open, -- 1-bit output: Single Bit Error: Indicates that the ECC decoder
+ -- detected and fixed a single-bit error.
+
+ underflow => open, -- 1-bit output: Underflow: Indicates that the read request (rd_en)
+ -- during the previous clock cycle was rejected because the FIFO is
+ -- empty. Under flowing the FIFO is not destructive to the FIFO.
+
+ wr_ack => open, -- 1-bit output: Write Acknowledge: This signal indicates that a write
+ -- request (wr_en) during the prior clock cycle is succeeded.
+
+ wr_data_count => wrusedw, -- WR_DATA_COUNT_WIDTH-bit output: Write Data Count: This bus indicates
+ -- the number of words written into the FIFO.
+
+ wr_rst_busy => open, -- 1-bit output: Write Reset Busy: Active-High indicator that the FIFO
+ -- write domain is currently in a reset state.
+
+ din => data, -- WRITE_DATA_WIDTH-bit input: Write Data: The input data bus used when
+ -- writing the FIFO.
+
+ injectdbiterr => '0', -- 1-bit input: Double Bit Error Injection: Injects a double bit error if
+ -- the ECC feature is used on block RAMs or UltraRAM macros.
+
+ injectsbiterr => '0', -- 1-bit input: Single Bit Error Injection: Injects a single bit error if
+ -- the ECC feature is used on block RAMs or UltraRAM macros.
+
+ rd_clk => rdclk, -- 1-bit input: Read clock: Used for read operation. rd_clk must be a
+ -- free running clock.
+
+ rd_en => rdreq, -- 1-bit input: Read Enable: If the FIFO is not empty, asserting this
+ -- signal causes data (on dout) to be read from the FIFO. Must be held
+ -- active-low when rd_rst_busy is active high.
+
+ rst => aclr, -- 1-bit input: Reset: Must be synchronous to wr_clk. The clock(s) can be
+ -- unstable at the time of applying reset, but reset must be released
+ -- only after the clock(s) is/are stable.
+
+ sleep => '0', -- 1-bit input: Dynamic power saving: If sleep is High, the memory/fifo
+ -- block is in power saving mode.
+
+ wr_clk => wrclk, -- 1-bit input: Write clock: Used for write operation. wr_clk must be a
+ -- free running clock.
+
+ wr_en => wrreq -- 1-bit input: Write Enable: If the FIFO is not full, asserting this
+ -- signal causes data (on din) to be written to the FIFO. Must be held
+ -- active-low when rst or wr_rst_busy is active high.
+ );
+
+ -- End of xpm_fifo_async_inst instantiation
+end SYN;
\ No newline at end of file
diff --git a/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_dc_mixed_widths.vhd b/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_dc_mixed_widths.vhd
index 936d0862322feb8db23d0f3b64dfc56c0c0bfc70..757b4f18188d3106937335c23076023e63207e30 100644
--- a/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_dc_mixed_widths.vhd
+++ b/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_dc_mixed_widths.vhd
@@ -1,178 +1,178 @@
--------------------------------------------------------------------------------
---
--- Copyright 2023
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- Licensed under the Apache License, Version 2.0 (the "License");
--- you may not use this file except in compliance with the License.
--- You may obtain a copy of the License at
---
--- http://www.apache.org/licenses/LICENSE-2.0
---
--- Unless required by applicable law or agreed to in writing, software
--- distributed under the License is distributed on an "AS IS" BASIS,
--- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--- See the License for the specific language governing permissions and
--- limitations under the License.
---
--------------------------------------------------------------------------------
--- Purpose: Instantiate FIFO IP with generics
--- Description:
--- Copied component instantiation from Vivado XPM template
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY technology_lib;
-USE technology_lib.technology_pkg.ALL;
-
-LIBRARY xpm;
-USE xpm.vcomponents.ALL;
-
-ENTITY ip_ultrascale_fifo_dc_mixed_widths IS
- GENERIC (
- g_nof_words : NATURAL := 1024; -- FIFO size in nof wr_dat words
- g_wrdat_w : NATURAL := 20;
- g_rddat_w : NATURAL := 10
- );
- PORT (
- aclr : IN STD_LOGIC := '0';
- data : IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
- rdclk : IN STD_LOGIC ;
- rdreq : IN STD_LOGIC ;
- wrclk : IN STD_LOGIC ;
- wrreq : IN STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
- rdempty : OUT STD_LOGIC ;
- rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
- wrfull : OUT STD_LOGIC ;
- wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
- );
-END ip_ultrascale_fifo_dc_mixed_widths;
-
-ARCHITECTURE SYN OF ip_ultrascale_fifo_dc_mixed_widths IS
-
-BEGIN
- -- xpm_fifo_async: Asynchronous FIFO
- -- Xilinx Parameterized Macro, version 2022.1
-
- xpm_fifo_async_inst : xpm_fifo_async
- generic map (
- CASCADE_HEIGHT => 0, -- DECIMAL
- CDC_SYNC_STAGES => 3, -- DECIMAL
- DOUT_RESET_VALUE => "0", -- String
- ECC_MODE => "no_ecc", -- String
- FIFO_MEMORY_TYPE => "auto", -- String
- FIFO_READ_LATENCY => 1, -- DECIMAL
- FIFO_WRITE_DEPTH => g_nof_words, -- DECIMAL
- FULL_RESET_VALUE => 0, -- DECIMAL
- PROG_EMPTY_THRESH => 10, -- DECIMAL
- PROG_FULL_THRESH => 10, -- DECIMAL
- RD_DATA_COUNT_WIDTH => tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w), -- DECIMAL
- READ_DATA_WIDTH => g_rddat_w, -- DECIMAL
- READ_MODE => "std", -- String
- RELATED_CLOCKS => 0, -- DECIMAL
- SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
- USE_ADV_FEATURES => "0404", -- String
- WAKEUP_TIME => 0, -- DECIMAL
- WRITE_DATA_WIDTH => g_wrdat_w, -- DECIMAL
- WR_DATA_COUNT_WIDTH => tech_ceil_log2(g_nof_words) -- DECIMAL
- )
- port map (
- almost_empty => OPEN, -- 1-bit output: Almost Empty : When asserted, this signal indicates that
- -- only one more read can be performed before the FIFO goes to empty.
-
- almost_full => OPEN, -- 1-bit output: Almost Full: When asserted, this signal indicates that
- -- only one more write can be performed before the FIFO is full.
-
- data_valid => OPEN, -- 1-bit output: Read Data Valid: When asserted, this signal indicates
- -- that valid data is available on the output bus (dout).
-
- dbiterr => OPEN, -- 1-bit output: Double Bit Error: Indicates that the ECC decoder
- -- detected a double-bit error and data in the FIFO core is corrupted.
-
- dout => q, -- READ_DATA_WIDTH-bit output: Read Data: The output data bus is driven
- -- when reading the FIFO.
-
- empty => rdempty, -- 1-bit output: Empty Flag: When asserted, this signal indicates that
- -- the FIFO is empty. Read requests are ignored when the FIFO is empty,
- -- initiating a read while empty is not destructive to the FIFO.
-
- full => wrfull, -- 1-bit output: Full Flag: When asserted, this signal indicates that the
- -- FIFO is full. Write requests are ignored when the FIFO is full,
- -- initiating a write when the FIFO is full is not destructive to the
- -- contents of the FIFO.
-
- overflow => OPEN, -- 1-bit output: Overflow: This signal indicates that a write request
- -- (wren) during the prior clock cycle was rejected, because the FIFO is
- -- full. Overflowing the FIFO is not destructive to the contents of the
- -- FIFO.
-
- prog_empty => OPEN, -- 1-bit output: Programmable Empty: This signal is asserted when the
- -- number of words in the FIFO is less than or equal to the programmable
- -- empty threshold value. It is de-asserted when the number of words in
- -- the FIFO exceeds the programmable empty threshold value.
-
- prog_full => OPEN, -- 1-bit output: Programmable Full: This signal is asserted when the
- -- number of words in the FIFO is greater than or equal to the
- -- programmable full threshold value. It is de-asserted when the number
- -- of words in the FIFO is less than the programmable full threshold
- -- value.
-
- rd_data_count => rdusedw, -- RD_DATA_COUNT_WIDTH-bit output: Read Data Count: This bus indicates
- -- the number of words read from the FIFO.
-
- rd_rst_busy => OPEN, -- 1-bit output: Read Reset Busy: Active-High indicator that the FIFO
- -- read domain is currently in a reset state.
-
- sbiterr => OPEN, -- 1-bit output: Single Bit Error: Indicates that the ECC decoder
- -- detected and fixed a single-bit error.
-
- underflow => OPEN, -- 1-bit output: Underflow: Indicates that the read request (rd_en)
- -- during the previous clock cycle was rejected because the FIFO is
- -- empty. Under flowing the FIFO is not destructive to the FIFO.
-
- wr_ack => OPEN, -- 1-bit output: Write Acknowledge: This signal indicates that a write
- -- request (wr_en) during the prior clock cycle is succeeded.
-
- wr_data_count => wrusedw, -- WR_DATA_COUNT_WIDTH-bit output: Write Data Count: This bus indicates
- -- the number of words written into the FIFO.
-
- wr_rst_busy => OPEN, -- 1-bit output: Write Reset Busy: Active-High indicator that the FIFO
- -- write domain is currently in a reset state.
-
- din => data, -- WRITE_DATA_WIDTH-bit input: Write Data: The input data bus used when
- -- writing the FIFO.
-
- injectdbiterr => '0', -- 1-bit input: Double Bit Error Injection: Injects a double bit error if
- -- the ECC feature is used on block RAMs or UltraRAM macros.
-
- injectsbiterr => '0', -- 1-bit input: Single Bit Error Injection: Injects a single bit error if
- -- the ECC feature is used on block RAMs or UltraRAM macros.
-
- rd_clk => rdclk, -- 1-bit input: Read clock: Used for read operation. rd_clk must be a
- -- free running clock.
-
- rd_en => rdreq, -- 1-bit input: Read Enable: If the FIFO is not empty, asserting this
- -- signal causes data (on dout) to be read from the FIFO. Must be held
- -- active-low when rd_rst_busy is active high.
-
- rst => aclr, -- 1-bit input: Reset: Must be synchronous to wr_clk. The clock(s) can be
- -- unstable at the time of applying reset, but reset must be released
- -- only after the clock(s) is/are stable.
-
- sleep => '0', -- 1-bit input: Dynamic power saving: If sleep is High, the memory/fifo
- -- block is in power saving mode.
-
- wr_clk => wrclk, -- 1-bit input: Write clock: Used for write operation. wr_clk must be a
- -- free running clock.
-
- wr_en => wrreq -- 1-bit input: Write Enable: If the FIFO is not full, asserting this
- -- signal causes data (on din) to be written to the FIFO. Must be held
- -- active-low when rst or wr_rst_busy is active high.
- );
-
- -- End of xpm_fifo_async_inst instantiation
-
-END SYN;
+-------------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Purpose: Instantiate FIFO IP with generics
+-- Description:
+-- Copied component instantiation from Vivado XPM template
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library technology_lib;
+use technology_lib.technology_pkg.all;
+
+library xpm;
+use xpm.vcomponents.all;
+
+entity ip_ultrascale_fifo_dc_mixed_widths is
+ generic (
+ g_nof_words : natural := 1024; -- FIFO size in nof wr_dat words
+ g_wrdat_w : natural := 20;
+ g_rddat_w : natural := 10
+ );
+ port (
+ aclr : in std_logic := '0';
+ data : in std_logic_vector (g_wrdat_w - 1 downto 0);
+ rdclk : in std_logic ;
+ rdreq : in std_logic ;
+ wrclk : in std_logic ;
+ wrreq : in std_logic ;
+ q : out std_logic_vector (g_rddat_w - 1 downto 0);
+ rdempty : out std_logic ;
+ rdusedw : out std_logic_vector (tech_ceil_log2(g_nof_words * g_wrdat_w / g_rddat_w) - 1 downto 0);
+ wrfull : out std_logic ;
+ wrusedw : out std_logic_vector (tech_ceil_log2(g_nof_words) - 1 downto 0)
+ );
+end ip_ultrascale_fifo_dc_mixed_widths;
+
+architecture SYN of ip_ultrascale_fifo_dc_mixed_widths is
+
+begin
+ -- xpm_fifo_async: Asynchronous FIFO
+ -- Xilinx Parameterized Macro, version 2022.1
+
+ xpm_fifo_async_inst : xpm_fifo_async
+ generic map (
+ CASCADE_HEIGHT => 0, -- DECIMAL
+ CDC_SYNC_STAGES => 3, -- DECIMAL
+ DOUT_RESET_VALUE => "0", -- String
+ ECC_MODE => "no_ecc", -- String
+ FIFO_MEMORY_TYPE => "auto", -- String
+ FIFO_READ_LATENCY => 1, -- DECIMAL
+ FIFO_WRITE_DEPTH => g_nof_words, -- DECIMAL
+ FULL_RESET_VALUE => 0, -- DECIMAL
+ PROG_EMPTY_THRESH => 10, -- DECIMAL
+ PROG_FULL_THRESH => 10, -- DECIMAL
+ RD_DATA_COUNT_WIDTH => tech_ceil_log2(g_nof_words * g_wrdat_w / g_rddat_w), -- DECIMAL
+ READ_DATA_WIDTH => g_rddat_w, -- DECIMAL
+ READ_MODE => "std", -- String
+ RELATED_CLOCKS => 0, -- DECIMAL
+ SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+ USE_ADV_FEATURES => "0404", -- String
+ WAKEUP_TIME => 0, -- DECIMAL
+ WRITE_DATA_WIDTH => g_wrdat_w, -- DECIMAL
+ WR_DATA_COUNT_WIDTH => tech_ceil_log2(g_nof_words) -- DECIMAL
+ )
+ port map (
+ almost_empty => open, -- 1-bit output: Almost Empty : When asserted, this signal indicates that
+ -- only one more read can be performed before the FIFO goes to empty.
+
+ almost_full => open, -- 1-bit output: Almost Full: When asserted, this signal indicates that
+ -- only one more write can be performed before the FIFO is full.
+
+ data_valid => open, -- 1-bit output: Read Data Valid: When asserted, this signal indicates
+ -- that valid data is available on the output bus (dout).
+
+ dbiterr => open, -- 1-bit output: Double Bit Error: Indicates that the ECC decoder
+ -- detected a double-bit error and data in the FIFO core is corrupted.
+
+ dout => q, -- READ_DATA_WIDTH-bit output: Read Data: The output data bus is driven
+ -- when reading the FIFO.
+
+ empty => rdempty, -- 1-bit output: Empty Flag: When asserted, this signal indicates that
+ -- the FIFO is empty. Read requests are ignored when the FIFO is empty,
+ -- initiating a read while empty is not destructive to the FIFO.
+
+ full => wrfull, -- 1-bit output: Full Flag: When asserted, this signal indicates that the
+ -- FIFO is full. Write requests are ignored when the FIFO is full,
+ -- initiating a write when the FIFO is full is not destructive to the
+ -- contents of the FIFO.
+
+ overflow => open, -- 1-bit output: Overflow: This signal indicates that a write request
+ -- (wren) during the prior clock cycle was rejected, because the FIFO is
+ -- full. Overflowing the FIFO is not destructive to the contents of the
+ -- FIFO.
+
+ prog_empty => open, -- 1-bit output: Programmable Empty: This signal is asserted when the
+ -- number of words in the FIFO is less than or equal to the programmable
+ -- empty threshold value. It is de-asserted when the number of words in
+ -- the FIFO exceeds the programmable empty threshold value.
+
+ prog_full => open, -- 1-bit output: Programmable Full: This signal is asserted when the
+ -- number of words in the FIFO is greater than or equal to the
+ -- programmable full threshold value. It is de-asserted when the number
+ -- of words in the FIFO is less than the programmable full threshold
+ -- value.
+
+ rd_data_count => rdusedw, -- RD_DATA_COUNT_WIDTH-bit output: Read Data Count: This bus indicates
+ -- the number of words read from the FIFO.
+
+ rd_rst_busy => open, -- 1-bit output: Read Reset Busy: Active-High indicator that the FIFO
+ -- read domain is currently in a reset state.
+
+ sbiterr => open, -- 1-bit output: Single Bit Error: Indicates that the ECC decoder
+ -- detected and fixed a single-bit error.
+
+ underflow => open, -- 1-bit output: Underflow: Indicates that the read request (rd_en)
+ -- during the previous clock cycle was rejected because the FIFO is
+ -- empty. Under flowing the FIFO is not destructive to the FIFO.
+
+ wr_ack => open, -- 1-bit output: Write Acknowledge: This signal indicates that a write
+ -- request (wr_en) during the prior clock cycle is succeeded.
+
+ wr_data_count => wrusedw, -- WR_DATA_COUNT_WIDTH-bit output: Write Data Count: This bus indicates
+ -- the number of words written into the FIFO.
+
+ wr_rst_busy => open, -- 1-bit output: Write Reset Busy: Active-High indicator that the FIFO
+ -- write domain is currently in a reset state.
+
+ din => data, -- WRITE_DATA_WIDTH-bit input: Write Data: The input data bus used when
+ -- writing the FIFO.
+
+ injectdbiterr => '0', -- 1-bit input: Double Bit Error Injection: Injects a double bit error if
+ -- the ECC feature is used on block RAMs or UltraRAM macros.
+
+ injectsbiterr => '0', -- 1-bit input: Single Bit Error Injection: Injects a single bit error if
+ -- the ECC feature is used on block RAMs or UltraRAM macros.
+
+ rd_clk => rdclk, -- 1-bit input: Read clock: Used for read operation. rd_clk must be a
+ -- free running clock.
+
+ rd_en => rdreq, -- 1-bit input: Read Enable: If the FIFO is not empty, asserting this
+ -- signal causes data (on dout) to be read from the FIFO. Must be held
+ -- active-low when rd_rst_busy is active high.
+
+ rst => aclr, -- 1-bit input: Reset: Must be synchronous to wr_clk. The clock(s) can be
+ -- unstable at the time of applying reset, but reset must be released
+ -- only after the clock(s) is/are stable.
+
+ sleep => '0', -- 1-bit input: Dynamic power saving: If sleep is High, the memory/fifo
+ -- block is in power saving mode.
+
+ wr_clk => wrclk, -- 1-bit input: Write clock: Used for write operation. wr_clk must be a
+ -- free running clock.
+
+ wr_en => wrreq -- 1-bit input: Write Enable: If the FIFO is not full, asserting this
+ -- signal causes data (on din) to be written to the FIFO. Must be held
+ -- active-low when rst or wr_rst_busy is active high.
+ );
+
+ -- End of xpm_fifo_async_inst instantiation
+
+end SYN;
\ No newline at end of file
diff --git a/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_sc.vhd b/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_sc.vhd
index 4184f4ab93aeca5afbd05e9581c53b822755d1ae..6e0f0be4371a961bcb5af8e42880a39f11481d88 100644
--- a/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_sc.vhd
+++ b/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_sc.vhd
@@ -1,171 +1,171 @@
--------------------------------------------------------------------------------
---
--- Copyright 2023
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- Licensed under the Apache License, Version 2.0 (the "License");
--- you may not use this file except in compliance with the License.
--- You may obtain a copy of the License at
---
--- http://www.apache.org/licenses/LICENSE-2.0
---
--- Unless required by applicable law or agreed to in writing, software
--- distributed under the License is distributed on an "AS IS" BASIS,
--- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--- See the License for the specific language governing permissions and
--- limitations under the License.
---
--------------------------------------------------------------------------------
--- Purpose: Instantiate FIFO IP with generics
--- Description:
--- Copied component instantiation from Vivado XPM template
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY technology_lib;
-USE technology_lib.technology_pkg.ALL;
-
-LIBRARY xpm;
-USE xpm.vcomponents.ALL;
-
-ENTITY ip_ultrascale_fifo_sc IS
- GENERIC (
- g_dat_w : NATURAL := 20;
- g_nof_words : NATURAL := 1024
- );
- PORT (
- aclr : IN STD_LOGIC ;
- clock : IN STD_LOGIC ;
- data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdreq : IN STD_LOGIC ;
- wrreq : IN STD_LOGIC ;
- empty : OUT STD_LOGIC ;
- full : OUT STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
- usedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
- );
-END ip_ultrascale_fifo_sc;
-
-ARCHITECTURE SYN OF ip_ultrascale_fifo_sc IS
-
-BEGIN
- -- xpm_fifo_sync: Synchronous FIFO
- -- Xilinx Parameterized Macro, version 2022.1
-
- xpm_fifo_sync_inst : xpm_fifo_sync
- generic map (
- CASCADE_HEIGHT => 0, -- DECIMAL
- DOUT_RESET_VALUE => "0", -- String
- ECC_MODE => "no_ecc", -- String
- FIFO_MEMORY_TYPE => "auto", -- String
- FIFO_READ_LATENCY => 1, -- DECIMAL
- FIFO_WRITE_DEPTH => g_nof_words, -- DECIMAL
- FULL_RESET_VALUE => 0, -- DECIMAL
- PROG_EMPTY_THRESH => 10, -- DECIMAL
- PROG_FULL_THRESH => 10, -- DECIMAL
- RD_DATA_COUNT_WIDTH => tech_ceil_log2(g_nof_words), -- DECIMAL
- READ_DATA_WIDTH => g_dat_w, -- DECIMAL
- READ_MODE => "std", -- String
- SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
- USE_ADV_FEATURES => "0404", -- String
- WAKEUP_TIME => 0, -- DECIMAL
- WRITE_DATA_WIDTH => g_dat_w, -- DECIMAL
- WR_DATA_COUNT_WIDTH => tech_ceil_log2(g_nof_words) -- DECIMAL
-
- )
- port map (
- almost_empty => OPEN, -- 1-bit output: Almost Empty : When asserted, this signal indicates that
- -- only one more read can be performed before the FIFO goes to empty.
-
- almost_full => OPEN, -- 1-bit output: Almost Full: When asserted, this signal indicates that
- -- only one more write can be performed before the FIFO is full.
-
- data_valid => OPEN, -- 1-bit output: Read Data Valid: When asserted, this signal indicates
- -- that valid data is available on the output bus (dout).
-
- dbiterr => OPEN, -- 1-bit output: Double Bit Error: Indicates that the ECC decoder
- -- detected a double-bit error and data in the FIFO core is corrupted.
-
- dout => q, -- READ_DATA_WIDTH-bit output: Read Data: The output data bus is driven
- -- when reading the FIFO.
-
- empty => empty, -- 1-bit output: Empty Flag: When asserted, this signal indicates that
- -- the FIFO is empty. Read requests are ignored when the FIFO is empty,
- -- initiating a read while empty is not destructive to the FIFO.
-
- full => full, -- 1-bit output: Full Flag: When asserted, this signal indicates that the
- -- FIFO is full. Write requests are ignored when the FIFO is full,
- -- initiating a write when the FIFO is full is not destructive to the
- -- contents of the FIFO.
-
- overflow => OPEN, -- 1-bit output: Overflow: This signal indicates that a write request
- -- (wren) during the prior clock cycle was rejected, because the FIFO is
- -- full. Overflowing the FIFO is not destructive to the contents of the
- -- FIFO.
-
- prog_empty => OPEN, -- 1-bit output: Programmable Empty: This signal is asserted when the
- -- number of words in the FIFO is less than or equal to the programmable
- -- empty threshold value. It is de-asserted when the number of words in
- -- the FIFO exceeds the programmable empty threshold value.
-
- prog_full => OPEN, -- 1-bit output: Programmable Full: This signal is asserted when the
- -- number of words in the FIFO is greater than or equal to the
- -- programmable full threshold value. It is de-asserted when the number
- -- of words in the FIFO is less than the programmable full threshold
- -- value.
-
- rd_data_count => OPEN, -- RD_DATA_COUNT_WIDTH-bit output: Read Data Count: This bus indicates
- -- the number of words read from the FIFO.
-
- rd_rst_busy => OPEN, -- 1-bit output: Read Reset Busy: Active-High indicator that the FIFO
- -- read domain is currently in a reset state.
-
- sbiterr => OPEN, -- 1-bit output: Single Bit Error: Indicates that the ECC decoder
- -- detected and fixed a single-bit error.
-
- underflow => OPEN, -- 1-bit output: Underflow: Indicates that the read request (rd_en)
- -- during the previous clock cycle was rejected because the FIFO is
- -- empty. Under flowing the FIFO is not destructive to the FIFO.
-
- wr_ack => OPEN, -- 1-bit output: Write Acknowledge: This signal indicates that a write
- -- request (wr_en) during the prior clock cycle is succeeded.
-
- wr_data_count => usedw, -- WR_DATA_COUNT_WIDTH-bit output: Write Data Count: This bus indicates
- -- the number of words written into the FIFO.
-
- wr_rst_busy => OPEN, -- 1-bit output: Write Reset Busy: Active-High indicator that the FIFO
- -- write domain is currently in a reset state.
-
- din => data, -- WRITE_DATA_WIDTH-bit input: Write Data: The input data bus used when
- -- writing the FIFO.
-
- injectdbiterr => '0', -- 1-bit input: Double Bit Error Injection: Injects a double bit error if
- -- the ECC feature is used on block RAMs or UltraRAM macros.
-
- injectsbiterr => '0', -- 1-bit input: Single Bit Error Injection: Injects a single bit error if
- -- the ECC feature is used on block RAMs or UltraRAM macros.
-
- rd_en => rdreq, -- 1-bit input: Read Enable: If the FIFO is not empty, asserting this
- -- signal causes data (on dout) to be read from the FIFO. Must be held
- -- active-low when rd_rst_busy is active high.
-
- rst => aclr, -- 1-bit input: Reset: Must be synchronous to wr_clk. The clock(s) can be
- -- unstable at the time of applying reset, but reset must be released
- -- only after the clock(s) is/are stable.
-
- sleep => '0', -- 1-bit input: Dynamic power saving: If sleep is High, the memory/fifo
- -- block is in power saving mode.
-
- wr_clk => clock, -- 1-bit input: Write clock: Used for write operation. wr_clk must be a
- -- free running clock.
-
- wr_en => wrreq -- 1-bit input: Write Enable: If the FIFO is not full, asserting this
- -- signal causes data (on din) to be written to the FIFO. Must be held
- -- active-low when rst or wr_rst_busy is active high.
- );
-
- -- End of xpm_fifo_async_inst instantiation
-
-END SYN;
+-------------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Purpose: Instantiate FIFO IP with generics
+-- Description:
+-- Copied component instantiation from Vivado XPM template
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library technology_lib;
+use technology_lib.technology_pkg.all;
+
+library xpm;
+use xpm.vcomponents.all;
+
+entity ip_ultrascale_fifo_sc is
+ generic (
+ g_dat_w : natural := 20;
+ g_nof_words : natural := 1024
+ );
+ port (
+ aclr : in std_logic ;
+ clock : in std_logic ;
+ data : in std_logic_vector (g_dat_w - 1 downto 0);
+ rdreq : in std_logic ;
+ wrreq : in std_logic ;
+ empty : out std_logic ;
+ full : out std_logic ;
+ q : out std_logic_vector (g_dat_w - 1 downto 0) ;
+ usedw : out std_logic_vector (tech_ceil_log2(g_nof_words) - 1 downto 0)
+ );
+end ip_ultrascale_fifo_sc;
+
+architecture SYN of ip_ultrascale_fifo_sc is
+
+begin
+ -- xpm_fifo_sync: Synchronous FIFO
+ -- Xilinx Parameterized Macro, version 2022.1
+
+ xpm_fifo_sync_inst : xpm_fifo_sync
+ generic map (
+ CASCADE_HEIGHT => 0, -- DECIMAL
+ DOUT_RESET_VALUE => "0", -- String
+ ECC_MODE => "no_ecc", -- String
+ FIFO_MEMORY_TYPE => "auto", -- String
+ FIFO_READ_LATENCY => 1, -- DECIMAL
+ FIFO_WRITE_DEPTH => g_nof_words, -- DECIMAL
+ FULL_RESET_VALUE => 0, -- DECIMAL
+ PROG_EMPTY_THRESH => 10, -- DECIMAL
+ PROG_FULL_THRESH => 10, -- DECIMAL
+ RD_DATA_COUNT_WIDTH => tech_ceil_log2(g_nof_words), -- DECIMAL
+ READ_DATA_WIDTH => g_dat_w, -- DECIMAL
+ READ_MODE => "std", -- String
+ SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+ USE_ADV_FEATURES => "0404", -- String
+ WAKEUP_TIME => 0, -- DECIMAL
+ WRITE_DATA_WIDTH => g_dat_w, -- DECIMAL
+ WR_DATA_COUNT_WIDTH => tech_ceil_log2(g_nof_words) -- DECIMAL
+
+ )
+ port map (
+ almost_empty => open, -- 1-bit output: Almost Empty : When asserted, this signal indicates that
+ -- only one more read can be performed before the FIFO goes to empty.
+
+ almost_full => open, -- 1-bit output: Almost Full: When asserted, this signal indicates that
+ -- only one more write can be performed before the FIFO is full.
+
+ data_valid => open, -- 1-bit output: Read Data Valid: When asserted, this signal indicates
+ -- that valid data is available on the output bus (dout).
+
+ dbiterr => open, -- 1-bit output: Double Bit Error: Indicates that the ECC decoder
+ -- detected a double-bit error and data in the FIFO core is corrupted.
+
+ dout => q, -- READ_DATA_WIDTH-bit output: Read Data: The output data bus is driven
+ -- when reading the FIFO.
+
+ empty => empty, -- 1-bit output: Empty Flag: When asserted, this signal indicates that
+ -- the FIFO is empty. Read requests are ignored when the FIFO is empty,
+ -- initiating a read while empty is not destructive to the FIFO.
+
+ full => full, -- 1-bit output: Full Flag: When asserted, this signal indicates that the
+ -- FIFO is full. Write requests are ignored when the FIFO is full,
+ -- initiating a write when the FIFO is full is not destructive to the
+ -- contents of the FIFO.
+
+ overflow => open, -- 1-bit output: Overflow: This signal indicates that a write request
+ -- (wren) during the prior clock cycle was rejected, because the FIFO is
+ -- full. Overflowing the FIFO is not destructive to the contents of the
+ -- FIFO.
+
+ prog_empty => open, -- 1-bit output: Programmable Empty: This signal is asserted when the
+ -- number of words in the FIFO is less than or equal to the programmable
+ -- empty threshold value. It is de-asserted when the number of words in
+ -- the FIFO exceeds the programmable empty threshold value.
+
+ prog_full => open, -- 1-bit output: Programmable Full: This signal is asserted when the
+ -- number of words in the FIFO is greater than or equal to the
+ -- programmable full threshold value. It is de-asserted when the number
+ -- of words in the FIFO is less than the programmable full threshold
+ -- value.
+
+ rd_data_count => open, -- RD_DATA_COUNT_WIDTH-bit output: Read Data Count: This bus indicates
+ -- the number of words read from the FIFO.
+
+ rd_rst_busy => open, -- 1-bit output: Read Reset Busy: Active-High indicator that the FIFO
+ -- read domain is currently in a reset state.
+
+ sbiterr => open, -- 1-bit output: Single Bit Error: Indicates that the ECC decoder
+ -- detected and fixed a single-bit error.
+
+ underflow => open, -- 1-bit output: Underflow: Indicates that the read request (rd_en)
+ -- during the previous clock cycle was rejected because the FIFO is
+ -- empty. Under flowing the FIFO is not destructive to the FIFO.
+
+ wr_ack => open, -- 1-bit output: Write Acknowledge: This signal indicates that a write
+ -- request (wr_en) during the prior clock cycle is succeeded.
+
+ wr_data_count => usedw, -- WR_DATA_COUNT_WIDTH-bit output: Write Data Count: This bus indicates
+ -- the number of words written into the FIFO.
+
+ wr_rst_busy => open, -- 1-bit output: Write Reset Busy: Active-High indicator that the FIFO
+ -- write domain is currently in a reset state.
+
+ din => data, -- WRITE_DATA_WIDTH-bit input: Write Data: The input data bus used when
+ -- writing the FIFO.
+
+ injectdbiterr => '0', -- 1-bit input: Double Bit Error Injection: Injects a double bit error if
+ -- the ECC feature is used on block RAMs or UltraRAM macros.
+
+ injectsbiterr => '0', -- 1-bit input: Single Bit Error Injection: Injects a single bit error if
+ -- the ECC feature is used on block RAMs or UltraRAM macros.
+
+ rd_en => rdreq, -- 1-bit input: Read Enable: If the FIFO is not empty, asserting this
+ -- signal causes data (on dout) to be read from the FIFO. Must be held
+ -- active-low when rd_rst_busy is active high.
+
+ rst => aclr, -- 1-bit input: Reset: Must be synchronous to wr_clk. The clock(s) can be
+ -- unstable at the time of applying reset, but reset must be released
+ -- only after the clock(s) is/are stable.
+
+ sleep => '0', -- 1-bit input: Dynamic power saving: If sleep is High, the memory/fifo
+ -- block is in power saving mode.
+
+ wr_clk => clock, -- 1-bit input: Write clock: Used for write operation. wr_clk must be a
+ -- free running clock.
+
+ wr_en => wrreq -- 1-bit input: Write Enable: If the FIFO is not full, asserting this
+ -- signal causes data (on din) to be written to the FIFO. Must be held
+ -- active-low when rst or wr_rst_busy is active high.
+ );
+
+ -- End of xpm_fifo_async_inst instantiation
+
+end SYN;
\ No newline at end of file
diff --git a/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_cr_cw.vhd b/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_cr_cw.vhd
index a11ea8d4288019a28d06ef3973cc95b73e00bd53..38c3b043650d2720ce87c4fbf470dc78a421934f 100644
--- a/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_cr_cw.vhd
+++ b/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_cr_cw.vhd
@@ -21,42 +21,42 @@
-- Description:
-- Copied component instantiation from Vivado XPM template
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-USE ieee.numeric_std.all;
-
-LIBRARY xpm;
-USE xpm.vcomponents.ALL;
-
-ENTITY ip_ultrascale_ram_cr_cw IS
- GENERIC (
- g_inferred : BOOLEAN := FALSE;
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 8;
- g_nof_words : NATURAL := 2**5;
- g_rd_latency : NATURAL := 1; -- choose 1 or 2
- g_init_file : STRING := "none"
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library xpm;
+use xpm.vcomponents.all;
+
+entity ip_ultrascale_ram_cr_cw is
+ generic (
+ g_inferred : boolean := FALSE;
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 8;
+ g_nof_words : natural := 2**5;
+ g_rd_latency : natural := 1; -- choose 1 or 2
+ g_init_file : string := "none"
);
- PORT
+ port
(
- data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdaddress : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
- rdclk : IN STD_LOGIC ;
- wraddress : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
- wrclk : IN STD_LOGIC := '1';
- wren : IN STD_LOGIC := '0';
- q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
+ data : in std_logic_vector (g_dat_w - 1 downto 0);
+ rdaddress : in std_logic_vector (g_adr_w - 1 downto 0);
+ rdclk : in std_logic ;
+ wraddress : in std_logic_vector (g_adr_w - 1 downto 0);
+ wrclk : in std_logic := '1';
+ wren : in std_logic := '0';
+ q : out std_logic_vector (g_dat_w - 1 downto 0)
);
-END ip_ultrascale_ram_cr_cw;
+end ip_ultrascale_ram_cr_cw;
-ARCHITECTURE SYN OF ip_ultrascale_ram_cr_cw IS
+architecture SYN of ip_ultrascale_ram_cr_cw is
-BEGIN
+begin
- ASSERT g_rd_latency=1 OR g_rd_latency=2 REPORT "ip_ultrascale_ram_cr_cw : read latency must be 1 (default) or 2" SEVERITY FAILURE;
-
- ASSERT g_inferred=FALSE REPORT "ip_ultrascale_ram_crw_crw : cannot infer RAM" SEVERITY FAILURE;
+ assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_ultrascale_ram_cr_cw : read latency must be 1 (default) or 2" severity FAILURE;
+
+ assert g_inferred = FALSE report "ip_ultrascale_ram_crw_crw : cannot infer RAM" severity FAILURE;
-- xpm_memory_sdpram: Simple Dual Port RAM
-- Xilinx Parameterized Macro, version 2022.1
@@ -91,12 +91,12 @@ BEGIN
)
port map (
- dbiterrb => OPEN, -- 1-bit output: Status signal to indicate double bit error occurrence
+ dbiterrb => open, -- 1-bit output: Status signal to indicate double bit error occurrence
-- on the data output of port A.
doutb => q, -- READ_DATA_WIDTH_B-bit output: Data output for port B read operations.
- sbiterrb => OPEN, -- 1-bit output: Status signal to indicate single bit error occurrence
+ sbiterrb => open, -- 1-bit output: Status signal to indicate single bit error occurrence
-- on the data output of port B.
addra => wraddress, -- ADDR_WIDTH_A-bit input: Address for port A write and read operations.
@@ -116,7 +116,7 @@ BEGIN
enb => '1', -- 1-bit input: Memory enable signal for port B. Must be high on clock
-- cycles when read or write operations are initiated. Pipelined
-- internally.
-
+
injectdbiterra => '0', -- 1-bit input: Controls double bit error injection on input data when
-- ECC enabled (Error injection capability is not available in
-- "decode_only" mode).
@@ -146,4 +146,4 @@ BEGIN
-- End of xpm_memory_sdpram_inst instantiation
-END SYN;
+end SYN;
\ No newline at end of file
diff --git a/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_crw_crw.vhd b/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_crw_crw.vhd
index ae4ffdc7358e18cce1b75fc74204a3576e4935fd..5d322fb38d6e80822b25c1f6bbdfb5ecb0822e09 100644
--- a/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_crw_crw.vhd
+++ b/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_crw_crw.vhd
@@ -21,45 +21,45 @@
-- Description:
-- Copied component instantiation from Vivado XPM template
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-USE ieee.numeric_std.all;
-
-LIBRARY xpm;
-USE xpm.vcomponents.ALL;
-
-ENTITY ip_ultrascale_ram_crw_crw IS
- GENERIC (
- g_inferred : BOOLEAN := FALSE;
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 8;
- g_nof_words : NATURAL := 2**5;
- g_rd_latency : NATURAL := 1; -- choose 1 or 2
- g_init_file : STRING := "none"
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library xpm;
+use xpm.vcomponents.all;
+
+entity ip_ultrascale_ram_crw_crw is
+ generic (
+ g_inferred : boolean := FALSE;
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 8;
+ g_nof_words : natural := 2**5;
+ g_rd_latency : natural := 1; -- choose 1 or 2
+ g_init_file : string := "none"
);
- PORT
+ port
(
- address_a : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
- address_b : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
- clk_a : IN STD_LOGIC := '1';
- clk_b : IN STD_LOGIC ;
- data_a : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- data_b : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- wren_a : IN STD_LOGIC := '0';
- wren_b : IN STD_LOGIC := '0';
- q_a : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- q_b : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
+ address_a : in std_logic_vector (g_adr_w - 1 downto 0);
+ address_b : in std_logic_vector (g_adr_w - 1 downto 0);
+ clk_a : in std_logic := '1';
+ clk_b : in std_logic ;
+ data_a : in std_logic_vector (g_dat_w - 1 downto 0);
+ data_b : in std_logic_vector (g_dat_w - 1 downto 0);
+ wren_a : in std_logic := '0';
+ wren_b : in std_logic := '0';
+ q_a : out std_logic_vector (g_dat_w - 1 downto 0);
+ q_b : out std_logic_vector (g_dat_w - 1 downto 0)
);
-END ip_ultrascale_ram_crw_crw;
+end ip_ultrascale_ram_crw_crw;
-ARCHITECTURE SYN OF ip_ultrascale_ram_crw_crw IS
-
-BEGIN
+architecture SYN of ip_ultrascale_ram_crw_crw is
+
+begin
+
+ assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_ultrascale_ram_crw_crw : read latency must be 1 (default) or 2" severity FAILURE;
+ assert g_inferred = FALSE report "ip_ultrascale_ram_crw_crw : cannot infer RAM" severity FAILURE;
- ASSERT g_rd_latency=1 OR g_rd_latency=2 REPORT "ip_ultrascale_ram_crw_crw : read latency must be 1 (default) or 2" SEVERITY FAILURE;
- ASSERT g_inferred=FALSE REPORT "ip_ultrascale_ram_crw_crw : cannot infer RAM" SEVERITY FAILURE;
-
-- xpm_memory_tdpram: True Dual Port RAM
-- Xilinx Parameterized Macro, version 2022.1
@@ -99,18 +99,18 @@ BEGIN
WRITE_PROTECT => 1 -- DECIMAL
)
port map (
- dbiterra => OPEN, -- 1-bit output: Status signal to indicate double bit error occurrence
+ dbiterra => open, -- 1-bit output: Status signal to indicate double bit error occurrence
-- on the data output of port A.
- dbiterrb => OPEN, -- 1-bit output: Status signal to indicate double bit error occurrence
+ dbiterrb => open, -- 1-bit output: Status signal to indicate double bit error occurrence
-- on the data output of port A.
douta => q_a, -- READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
doutb => q_b, -- READ_DATA_WIDTH_B-bit output: Data output for port B read operations.
- sbiterra => OPEN, -- 1-bit output: Status signal to indicate single bit error occurrence
+ sbiterra => open, -- 1-bit output: Status signal to indicate single bit error occurrence
-- on the data output of port A.
- sbiterrb => OPEN, -- 1-bit output: Status signal to indicate single bit error occurrence
+ sbiterrb => open, -- 1-bit output: Status signal to indicate single bit error occurrence
-- on the data output of port B.
addra => address_a, -- ADDR_WIDTH_A-bit input: Address for port A write and read operations.
@@ -131,7 +131,7 @@ BEGIN
enb => '1', -- 1-bit input: Memory enable signal for port B. Must be high on clock
-- cycles when read or write operations are initiated. Pipelined
-- internally.
-
+
injectdbiterra => '0', -- 1-bit input: Controls double bit error injection on input data when
-- ECC enabled (Error injection capability is not available in
-- "decode_only" mode).
@@ -180,5 +180,5 @@ BEGIN
);
-- End of xpm_memory_tdpram_inst instantiation
-
-END SYN;
+
+end SYN;
\ No newline at end of file
diff --git a/libraries/technology/jesd204b/tb_tech_jesd204b.vhd b/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
index 59e9475c3104fd3c557130699c1b3ed0c09eb913..24ab672baaf643874071375306239f673aa444ac 100644
--- a/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
+++ b/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
@@ -412,7 +412,7 @@ begin
v_count := v_count + 1;
end if;
- if v_count > c_sysref_period - 1 -c_sysref_pulselength then
+ if v_count > c_sysref_period - 1 - c_sysref_pulselength then
jesd204b_sysref <= '1';
else
jesd204b_sysref <= '0';
diff --git a/libraries/technology/mac_10g/tech_mac_10g.vhd b/libraries/technology/mac_10g/tech_mac_10g.vhd
index 6ee1d167018c087391d0c623ef3689294fb955a2..f6838e15b4421b2eec283d278c3d118644e41249 100644
--- a/libraries/technology/mac_10g/tech_mac_10g.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g.vhd
@@ -297,4 +297,4 @@ begin
rx_src_out <= rx_mac_src_out_rl1;
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/technology/memory/tech_memory_component_pkg.vhd b/libraries/technology/memory/tech_memory_component_pkg.vhd
index fd8b5ba72704c14e9f595b784dc9232ba21441a4..b9a80aae9e1cdcf1232097d36faf3a0036178e83 100644
--- a/libraries/technology/memory/tech_memory_component_pkg.vhd
+++ b/libraries/technology/memory/tech_memory_component_pkg.vhd
@@ -1,4 +1,3 @@
-<<<<<<< HEAD
-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
@@ -517,573 +516,52 @@ package tech_memory_component_pkg is
);
end component;
-end tech_memory_component_pkg;
-=======
--------------------------------------------------------------------------------
---
--- Copyright (C) 2014
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
--- Purpose: IP components declarations for various devices that get wrapped by the tech components
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-PACKAGE tech_memory_component_pkg IS
-
- -----------------------------------------------------------------------------
- -- ip_stratixiv
- -----------------------------------------------------------------------------
-
- COMPONENT ip_stratixiv_ram_crwk_crw IS -- support different port data widths and corresponding address ranges
- GENERIC (
- g_adr_a_w : NATURAL := 5;
- g_dat_a_w : NATURAL := 32;
- g_adr_b_w : NATURAL := 7;
- g_dat_b_w : NATURAL := 8;
- g_nof_words_a : NATURAL := 2**5;
- g_nof_words_b : NATURAL := 2**7;
- g_rd_latency : NATURAL := 2; -- choose 1 or 2
- g_init_file : STRING := "UNUSED"
- );
- PORT (
- address_a : IN STD_LOGIC_VECTOR (g_adr_a_w-1 DOWNTO 0);
- address_b : IN STD_LOGIC_VECTOR (g_adr_b_w-1 DOWNTO 0);
- clock_a : IN STD_LOGIC := '1';
- clock_b : IN STD_LOGIC ;
- data_a : IN STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
- data_b : IN STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0);
- enable_a : IN STD_LOGIC := '1';
- enable_b : IN STD_LOGIC := '1';
- rden_a : IN STD_LOGIC := '1';
- rden_b : IN STD_LOGIC := '1';
- wren_a : IN STD_LOGIC := '0';
- wren_b : IN STD_LOGIC := '0';
- q_a : OUT STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
- q_b : OUT STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0)
- );
- END COMPONENT;
-
- COMPONENT ip_stratixiv_ram_crw_crw IS
- GENERIC (
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 8;
- g_nof_words : NATURAL := 2**5;
- g_rd_latency : NATURAL := 2; -- choose 1 or 2
- g_init_file : STRING := "UNUSED"
- );
- PORT (
- address_a : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
- address_b : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
- clock_a : IN STD_LOGIC := '1';
- clock_b : IN STD_LOGIC ;
- data_a : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- data_b : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- enable_a : IN STD_LOGIC := '1';
- enable_b : IN STD_LOGIC := '1';
- rden_a : IN STD_LOGIC := '1';
- rden_b : IN STD_LOGIC := '1';
- wren_a : IN STD_LOGIC := '0';
- wren_b : IN STD_LOGIC := '0';
- q_a : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- q_b : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
- );
- END COMPONENT;
-
- COMPONENT ip_stratixiv_ram_cr_cw IS
- GENERIC (
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 8;
- g_nof_words : NATURAL := 2**5;
- g_rd_latency : NATURAL := 2; -- choose 1 or 2
- g_init_file : STRING := "UNUSED"
- );
- PORT (
- data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdaddress : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
- rdclock : IN STD_LOGIC ;
- rdclocken : IN STD_LOGIC := '1';
- wraddress : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
- wrclock : IN STD_LOGIC := '1';
- wrclocken : IN STD_LOGIC := '1';
- wren : IN STD_LOGIC := '0';
- q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
- );
- END COMPONENT;
-
- COMPONENT ip_stratixiv_ram_r_w IS
- GENERIC (
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 8;
- g_nof_words : NATURAL := 2**5;
- g_init_file : STRING := "UNUSED"
- );
- PORT (
- clock : IN STD_LOGIC := '1';
- enable : IN STD_LOGIC := '1';
- data : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- rdaddress : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- wraddress : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- wren : IN STD_LOGIC := '0';
- q : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
- );
- END COMPONENT;
-
- COMPONENT ip_stratixiv_rom_r IS
- GENERIC (
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 8;
- g_nof_words : NATURAL := 2**5;
- g_init_file : STRING := "UNUSED"
- );
- PORT (
- address : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- clock : IN STD_LOGIC := '1';
- clken : IN STD_LOGIC := '1';
- q : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
- );
- END COMPONENT;
-
-
- -----------------------------------------------------------------------------
- -- ip_arria10
- -----------------------------------------------------------------------------
-
- COMPONENT ip_arria10_ram_crwk_crw IS
- GENERIC (
- g_adr_a_w : NATURAL := 5;
- g_dat_a_w : NATURAL := 32;
- g_adr_b_w : NATURAL := 4;
- g_dat_b_w : NATURAL := 64;
- g_nof_words_a : NATURAL := 2**5;
- g_nof_words_b : NATURAL := 2**4;
- g_rd_latency : NATURAL := 1; -- choose 1 or 2
- g_init_file : STRING := "UNUSED"
- );
- PORT
- (
- address_a : IN STD_LOGIC_VECTOR (g_adr_a_w-1 DOWNTO 0);
- address_b : IN STD_LOGIC_VECTOR (g_adr_b_w-1 DOWNTO 0);
- clk_a : IN STD_LOGIC := '1';
- clk_b : IN STD_LOGIC ;
- data_a : IN STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
- data_b : IN STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0);
- wren_a : IN STD_LOGIC := '0';
- wren_b : IN STD_LOGIC := '0';
- q_a : OUT STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
- q_b : OUT STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0)
- );
- END COMPONENT;
-
- COMPONENT ip_arria10_ram_crw_crw IS
- GENERIC (
- g_inferred : BOOLEAN := FALSE;
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 8;
- g_nof_words : NATURAL := 2**5;
- g_rd_latency : NATURAL := 1; -- choose 1 or 2
- g_init_file : STRING := "UNUSED"
- );
- PORT
- (
- address_a : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
- address_b : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
- clk_a : IN STD_LOGIC := '1';
- clk_b : IN STD_LOGIC ;
- data_a : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- data_b : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- wren_a : IN STD_LOGIC := '0';
- wren_b : IN STD_LOGIC := '0';
- q_a : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- q_b : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
- );
- END COMPONENT;
-
- COMPONENT ip_arria10_ram_cr_cw IS
- GENERIC (
- g_inferred : BOOLEAN := FALSE;
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 8;
- g_nof_words : NATURAL := 2**5;
- g_rd_latency : NATURAL := 1; -- choose 1 or 2
- g_init_file : STRING := "UNUSED"
- );
- PORT
- (
- data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdaddress : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
- rdclk : IN STD_LOGIC ;
- wraddress : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
- wrclk : IN STD_LOGIC := '1';
- wren : IN STD_LOGIC := '0';
- q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
- );
- END COMPONENT;
-
- COMPONENT ip_arria10_ram_r_w IS
- GENERIC (
- g_inferred : BOOLEAN := FALSE;
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 8;
- g_nof_words : NATURAL := 2**5;
- g_rd_latency : NATURAL := 1; -- choose 1 or 2
- g_init_file : STRING := "UNUSED"
- );
- PORT (
- clk : IN STD_LOGIC := '1';
- data : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0) := (OTHERS=>'0');
- rdaddress : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
- wraddress : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
- wren : IN STD_LOGIC := '0';
- q : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
- );
- END COMPONENT;
-
- -----------------------------------------------------------------------------
- -- ip_arria10_e3sge3
- -----------------------------------------------------------------------------
-
- COMPONENT ip_arria10_e3sge3_ram_crwk_crw IS
- GENERIC (
- g_adr_a_w : NATURAL := 5;
- g_dat_a_w : NATURAL := 32;
- g_adr_b_w : NATURAL := 4;
- g_dat_b_w : NATURAL := 64;
- g_nof_words_a : NATURAL := 2**5;
- g_nof_words_b : NATURAL := 2**4;
- g_rd_latency : NATURAL := 1; -- choose 1 or 2
- g_init_file : STRING := "UNUSED"
- );
- PORT
- (
- address_a : IN STD_LOGIC_VECTOR (g_adr_a_w-1 DOWNTO 0);
- address_b : IN STD_LOGIC_VECTOR (g_adr_b_w-1 DOWNTO 0);
- clk_a : IN STD_LOGIC := '1';
- clk_b : IN STD_LOGIC ;
- data_a : IN STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
- data_b : IN STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0);
- wren_a : IN STD_LOGIC := '0';
- wren_b : IN STD_LOGIC := '0';
- q_a : OUT STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
- q_b : OUT STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0)
- );
- END COMPONENT;
-
- COMPONENT ip_arria10_e3sge3_ram_crw_crw IS
- GENERIC (
- g_inferred : BOOLEAN := FALSE;
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 8;
- g_nof_words : NATURAL := 2**5;
- g_rd_latency : NATURAL := 1; -- choose 1 or 2
- g_init_file : STRING := "UNUSED"
- );
- PORT
- (
- address_a : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
- address_b : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
- clk_a : IN STD_LOGIC := '1';
- clk_b : IN STD_LOGIC ;
- data_a : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- data_b : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- wren_a : IN STD_LOGIC := '0';
- wren_b : IN STD_LOGIC := '0';
- q_a : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- q_b : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
- );
- END COMPONENT;
-
- COMPONENT ip_arria10_e3sge3_ram_cr_cw IS
- GENERIC (
- g_inferred : BOOLEAN := FALSE;
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 8;
- g_nof_words : NATURAL := 2**5;
- g_rd_latency : NATURAL := 1; -- choose 1 or 2
- g_init_file : STRING := "UNUSED"
- );
- PORT
- (
- data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdaddress : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
- rdclk : IN STD_LOGIC ;
- wraddress : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
- wrclk : IN STD_LOGIC := '1';
- wren : IN STD_LOGIC := '0';
- q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
- );
- END COMPONENT;
-
- COMPONENT ip_arria10_e3sge3_ram_r_w IS
- GENERIC (
- g_inferred : BOOLEAN := FALSE;
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 8;
- g_nof_words : NATURAL := 2**5;
- g_rd_latency : NATURAL := 1; -- choose 1 or 2
- g_init_file : STRING := "UNUSED"
- );
- PORT (
- clk : IN STD_LOGIC := '1';
- data : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0) := (OTHERS=>'0');
- rdaddress : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
- wraddress : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
- wren : IN STD_LOGIC := '0';
- q : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
- );
- END COMPONENT;
-
- -----------------------------------------------------------------------------
- -- ip_arria10_e1sg
- -----------------------------------------------------------------------------
-
- COMPONENT ip_arria10_e1sg_ram_crwk_crw IS
- GENERIC (
- g_adr_a_w : NATURAL := 5;
- g_dat_a_w : NATURAL := 32;
- g_adr_b_w : NATURAL := 4;
- g_dat_b_w : NATURAL := 64;
- g_nof_words_a : NATURAL := 2**5;
- g_nof_words_b : NATURAL := 2**4;
- g_rd_latency : NATURAL := 1; -- choose 1 or 2
- g_init_file : STRING := "UNUSED"
- );
- PORT
- (
- address_a : IN STD_LOGIC_VECTOR (g_adr_a_w-1 DOWNTO 0);
- address_b : IN STD_LOGIC_VECTOR (g_adr_b_w-1 DOWNTO 0);
- clk_a : IN STD_LOGIC := '1';
- clk_b : IN STD_LOGIC ;
- data_a : IN STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
- data_b : IN STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0);
- wren_a : IN STD_LOGIC := '0';
- wren_b : IN STD_LOGIC := '0';
- q_a : OUT STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
- q_b : OUT STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0)
- );
- END COMPONENT;
-
- COMPONENT ip_arria10_e1sg_ram_crw_crw IS
- GENERIC (
- g_inferred : BOOLEAN := FALSE;
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 8;
- g_nof_words : NATURAL := 2**5;
- g_rd_latency : NATURAL := 1; -- choose 1 or 2
- g_init_file : STRING := "UNUSED"
- );
- PORT
- (
- address_a : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
- address_b : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
- clk_a : IN STD_LOGIC := '1';
- clk_b : IN STD_LOGIC ;
- data_a : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- data_b : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- wren_a : IN STD_LOGIC := '0';
- wren_b : IN STD_LOGIC := '0';
- q_a : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- q_b : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
- );
- END COMPONENT;
-
- COMPONENT ip_arria10_e1sg_ram_cr_cw IS
- GENERIC (
- g_inferred : BOOLEAN := FALSE;
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 8;
- g_nof_words : NATURAL := 2**5;
- g_rd_latency : NATURAL := 1; -- choose 1 or 2
- g_init_file : STRING := "UNUSED"
- );
- PORT
- (
- data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdaddress : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
- rdclk : IN STD_LOGIC ;
- wraddress : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
- wrclk : IN STD_LOGIC := '1';
- wren : IN STD_LOGIC := '0';
- q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
- );
- END COMPONENT;
-
- COMPONENT ip_arria10_e1sg_ram_r_w IS
- GENERIC (
- g_inferred : BOOLEAN := FALSE;
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 8;
- g_nof_words : NATURAL := 2**5;
- g_rd_latency : NATURAL := 1; -- choose 1 or 2
- g_init_file : STRING := "UNUSED"
- );
- PORT (
- clk : IN STD_LOGIC := '1';
- data : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0) := (OTHERS=>'0');
- rdaddress : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
- wraddress : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
- wren : IN STD_LOGIC := '0';
- q : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
- );
- END COMPONENT;
-
- -----------------------------------------------------------------------------
- -- ip_arria10_e2sg
- -----------------------------------------------------------------------------
-
- COMPONENT ip_arria10_e2sg_ram_crwk_crw IS
- GENERIC (
- g_adr_a_w : NATURAL := 5;
- g_dat_a_w : NATURAL := 32;
- g_adr_b_w : NATURAL := 4;
- g_dat_b_w : NATURAL := 64;
- g_nof_words_a : NATURAL := 2**5;
- g_nof_words_b : NATURAL := 2**4;
- g_rd_latency : NATURAL := 1; -- choose 1 or 2
- g_init_file : STRING := "UNUSED"
- );
- PORT
- (
- address_a : IN STD_LOGIC_VECTOR (g_adr_a_w-1 DOWNTO 0);
- address_b : IN STD_LOGIC_VECTOR (g_adr_b_w-1 DOWNTO 0);
- clk_a : IN STD_LOGIC := '1';
- clk_b : IN STD_LOGIC ;
- data_a : IN STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
- data_b : IN STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0);
- wren_a : IN STD_LOGIC := '0';
- wren_b : IN STD_LOGIC := '0';
- q_a : OUT STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
- q_b : OUT STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0)
- );
- END COMPONENT;
-
- COMPONENT ip_arria10_e2sg_ram_crw_crw IS
- GENERIC (
- g_inferred : BOOLEAN := FALSE;
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 8;
- g_nof_words : NATURAL := 2**5;
- g_rd_latency : NATURAL := 1; -- choose 1 or 2
- g_init_file : STRING := "UNUSED"
- );
- PORT
- (
- address_a : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
- address_b : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
- clk_a : IN STD_LOGIC := '1';
- clk_b : IN STD_LOGIC ;
- data_a : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- data_b : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- wren_a : IN STD_LOGIC := '0';
- wren_b : IN STD_LOGIC := '0';
- q_a : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- q_b : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
- );
- END COMPONENT;
-
- COMPONENT ip_arria10_e2sg_ram_cr_cw IS
- GENERIC (
- g_inferred : BOOLEAN := FALSE;
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 8;
- g_nof_words : NATURAL := 2**5;
- g_rd_latency : NATURAL := 1; -- choose 1 or 2
- g_init_file : STRING := "UNUSED"
- );
- PORT
- (
- data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdaddress : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
- rdclk : IN STD_LOGIC ;
- wraddress : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
- wrclk : IN STD_LOGIC := '1';
- wren : IN STD_LOGIC := '0';
- q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
- );
- END COMPONENT;
-
- COMPONENT ip_arria10_e2sg_ram_r_w IS
- GENERIC (
- g_inferred : BOOLEAN := FALSE;
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 8;
- g_nof_words : NATURAL := 2**5;
- g_rd_latency : NATURAL := 1; -- choose 1 or 2
- g_init_file : STRING := "UNUSED"
- );
- PORT (
- clk : IN STD_LOGIC := '1';
- data : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0) := (OTHERS=>'0');
- rdaddress : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
- wraddress : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
- wren : IN STD_LOGIC := '0';
- q : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
- );
- END COMPONENT;
-
- -----------------------------------------------------------------------------
- -- ip_ultrascale
- -----------------------------------------------------------------------------
- COMPONENT ip_ultrascale_ram_crw_crw IS
- GENERIC (
- g_inferred : BOOLEAN := FALSE;
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 8;
- g_nof_words : NATURAL := 2**5;
- g_rd_latency : NATURAL := 1; -- choose 1 or 2
- g_init_file : STRING := "none"
- );
- PORT
- (
- address_a : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
- address_b : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
- clk_a : IN STD_LOGIC := '1';
- clk_b : IN STD_LOGIC ;
- data_a : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- data_b : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- wren_a : IN STD_LOGIC := '0';
- wren_b : IN STD_LOGIC := '0';
- q_a : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- q_b : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
- );
- END COMPONENT;
-
- COMPONENT ip_ultrascale_ram_cr_cw IS
- GENERIC (
- g_inferred : BOOLEAN := FALSE;
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 8;
- g_nof_words : NATURAL := 2**5;
- g_rd_latency : NATURAL := 1; -- choose 1 or 2
- g_init_file : STRING := "none"
- );
- PORT
- (
- data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- rdaddress : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
- rdclk : IN STD_LOGIC ;
- wraddress : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
- wrclk : IN STD_LOGIC := '1';
- wren : IN STD_LOGIC := '0';
- q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
- );
- END COMPONENT;
-
-END tech_memory_component_pkg;
->>>>>>> master
+ -----------------------------------------------------------------------------
+ -- ip_ultrascale
+ -----------------------------------------------------------------------------
+ component ip_ultrascale_ram_crw_crw is
+ generic (
+ g_inferred : boolean := FALSE;
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 8;
+ g_nof_words : natural := 2**5;
+ g_rd_latency : natural := 1; -- choose 1 or 2
+ g_init_file : string := "none"
+ );
+ port
+ (
+ address_a : in std_logic_vector (g_adr_w - 1 downto 0);
+ address_b : in std_logic_vector (g_adr_w - 1 downto 0);
+ clk_a : in std_logic := '1';
+ clk_b : in std_logic ;
+ data_a : in std_logic_vector (g_dat_w - 1 downto 0);
+ data_b : in std_logic_vector (g_dat_w - 1 downto 0);
+ wren_a : in std_logic := '0';
+ wren_b : in std_logic := '0';
+ q_a : out std_logic_vector (g_dat_w - 1 downto 0);
+ q_b : out std_logic_vector (g_dat_w - 1 downto 0)
+ );
+ end component;
+
+ component ip_ultrascale_ram_cr_cw is
+ generic (
+ g_inferred : boolean := FALSE;
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 8;
+ g_nof_words : natural := 2**5;
+ g_rd_latency : natural := 1; -- choose 1 or 2
+ g_init_file : string := "none"
+ );
+ port
+ (
+ data : in std_logic_vector (g_dat_w - 1 downto 0);
+ rdaddress : in std_logic_vector (g_adr_w - 1 downto 0);
+ rdclk : in std_logic ;
+ wraddress : in std_logic_vector (g_adr_w - 1 downto 0);
+ wrclk : in std_logic := '1';
+ wren : in std_logic := '0';
+ q : out std_logic_vector (g_dat_w - 1 downto 0)
+ );
+ end component;
+
+end tech_memory_component_pkg;
\ No newline at end of file
diff --git a/libraries/technology/memory/tech_memory_ram_cr_cw.vhd b/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
index 129f5a5c4d34f50e99fd2947863bcd8d6f51aec0..cf36d5441200a90ad5d0b4e4f66230d1697c954d 100644
--- a/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
@@ -26,20 +26,12 @@ use technology_lib.technology_pkg.all;
use technology_lib.technology_select_pkg.all;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-<<<<<<< HEAD
library ip_stratixiv_ram_lib;
library ip_arria10_ram_lib;
library ip_arria10_e3sge3_ram_lib;
library ip_arria10_e1sg_ram_lib;
library ip_arria10_e2sg_ram_lib;
-=======
-LIBRARY ip_stratixiv_ram_lib;
-LIBRARY ip_arria10_ram_lib;
-LIBRARY ip_arria10_e3sge3_ram_lib;
-LIBRARY ip_arria10_e1sg_ram_lib;
-LIBRARY ip_arria10_e2sg_ram_lib;
-LIBRARY ip_ultrascale_ram_lib;
->>>>>>> master
+library ip_ultrascale_ram_lib;
entity tech_memory_ram_cr_cw is
generic (
@@ -100,15 +92,15 @@ begin
end architecture;
=======
- GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
- PORT MAP (data, rdaddress, rdclock, wraddress, wrclock, wren, q);
- END GENERATE;
-
- gen_ip_ultrascale : IF g_technology=c_tech_ultrascale GENERATE
+ generic map (FALSE, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
+ port map (data, rdaddress, rdclock, wraddress, wrclock, wren, q);
+ end generate;
+
+ gen_ip_ultrascale : if g_technology = c_tech_ultrascale generate
u0 : ip_ultrascale_ram_cr_cw
- GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
- PORT MAP (data, rdaddress, rdclock, wraddress, wrclock, wren, q);
- END GENERATE;
+ generic map (FALSE, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
+ port map (data, rdaddress, rdclock, wraddress, wrclock, wren, q);
+ end generate;
-END ARCHITECTURE;
->>>>>>> master
+end architecture;
+>>>>>>> master
\ No newline at end of file
diff --git a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
index 411fcd3d90f8ebdd4c0096ac22525d5fb3768a77..7bdad1a88f8886054ced23b420c1c6f029fc98d7 100644
--- a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
@@ -1,4 +1,3 @@
-<<<<<<< HEAD
-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
@@ -32,6 +31,7 @@ library ip_arria10_ram_lib;
library ip_arria10_e3sge3_ram_lib;
library ip_arria10_e1sg_ram_lib;
library ip_arria10_e2sg_ram_lib;
+library ip_ultrascale_ram_lib;
entity tech_memory_ram_crw_crw is
generic (
@@ -96,112 +96,11 @@ begin
port map (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
end generate;
-end architecture;
-=======
--------------------------------------------------------------------------------
---
--- Copyright (C) 2014
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
-LIBRARY ieee, technology_lib;
-USE ieee.std_logic_1164.all;
-USE work.tech_memory_component_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
-USE technology_lib.technology_select_pkg.ALL;
-
--- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_stratixiv_ram_lib;
-LIBRARY ip_arria10_ram_lib;
-LIBRARY ip_arria10_e3sge3_ram_lib;
-LIBRARY ip_arria10_e1sg_ram_lib;
-LIBRARY ip_arria10_e2sg_ram_lib;
-LIBRARY ip_ultrascale_ram_lib;
-
-ENTITY tech_memory_ram_crw_crw IS
- GENERIC (
- g_technology : NATURAL := c_tech_select_default;
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 8;
- g_nof_words : NATURAL := 2**5;
- g_rd_latency : NATURAL := 2; -- choose 1 or 2
- g_init_file : STRING := "UNUSED"
- );
- PORT
- (
- address_a : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
- address_b : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
- clock_a : IN STD_LOGIC := '1';
- clock_b : IN STD_LOGIC ;
- data_a : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- data_b : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- enable_a : IN STD_LOGIC := '1';
- enable_b : IN STD_LOGIC := '1';
- rden_a : IN STD_LOGIC := '1';
- rden_b : IN STD_LOGIC := '1';
- wren_a : IN STD_LOGIC := '0';
- wren_b : IN STD_LOGIC := '0';
- q_a : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
- q_b : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
- );
-END tech_memory_ram_crw_crw;
-
-
-ARCHITECTURE str OF tech_memory_ram_crw_crw IS
-
-BEGIN
-
- gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
- u0 : ip_stratixiv_ram_crw_crw
- GENERIC MAP (g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
- PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, enable_a, enable_b, rden_a, rden_b, wren_a, wren_b, q_a, q_b);
- END GENERATE;
-
- gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
- u0 : ip_arria10_ram_crw_crw
- GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
- PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
- END GENERATE;
-
- gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
- u0 : ip_arria10_e3sge3_ram_crw_crw
- GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
- PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
- END GENERATE;
-
- gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
- u0 : ip_arria10_e1sg_ram_crw_crw
- GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
- PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
- END GENERATE;
-
- gen_ip_arria10_e2sg : IF g_technology=c_tech_arria10_e2sg GENERATE
- u0 : ip_arria10_e2sg_ram_crw_crw
- GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
- PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
- END GENERATE;
-
- gen_ip_ultrascale : IF g_technology=c_tech_ultrascale GENERATE
- u0 : ip_ultrascale_ram_crw_crw
- GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
- PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
- END GENERATE;
-
-
-END ARCHITECTURE;
->>>>>>> master
+ gen_ip_ultrascale : if g_technology = c_tech_ultrascale generate
+ u0 : ip_ultrascale_ram_crw_crw
+ generic map (FALSE, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
+ port map (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
+ end generate;
+
+
+end architecture;
\ No newline at end of file
diff --git a/libraries/technology/mult/tech_complex_mult.vhd b/libraries/technology/mult/tech_complex_mult.vhd
index 91a02b3b1a0dfd8c1d2e7f2f67d2fc857aa81a19..32769467abe710cae75f5a4ebb0ede1f08a1c1d6 100644
--- a/libraries/technology/mult/tech_complex_mult.vhd
+++ b/libraries/technology/mult/tech_complex_mult.vhd
@@ -115,7 +115,7 @@ begin
-- IP variants for <= 18 bit
-----------------------------------------------------------------------------
- gen_ip_stratixiv_ip : if g_variant ="IP " and g_technology = c_tech_stratixiv and c_dsp_dat_w <= c_dsp_mult_18_w generate
+ gen_ip_stratixiv_ip : if g_variant ="IP " and g_technology = c_tech_stratixiv and c_dsp_dat_w <= c_dsp_mult_18_w generate
-- Adapt DSP input widths
ar <= RESIZE_SVEC(in_ar, c_dsp_mult_18_w);
ai <= RESIZE_SVEC(in_ai, c_dsp_mult_18_w);
@@ -140,7 +140,7 @@ begin
result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
end generate;
- gen_ip_arria10_ip : if g_variant ="IP " and g_technology = c_tech_arria10_proto and c_dsp_dat_w <= c_dsp_mult_18_w generate
+ gen_ip_arria10_ip : if g_variant ="IP " and g_technology = c_tech_arria10_proto and c_dsp_dat_w <= c_dsp_mult_18_w generate
-- Adapt DSP input widths
ar <= RESIZE_SVEC(in_ar, c_dsp_mult_18_w);
ai <= RESIZE_SVEC(in_ai, c_dsp_mult_18_w);
@@ -165,7 +165,7 @@ begin
result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
end generate;
- gen_ip_arria10_e1sg_ip : if g_variant ="IP " and g_technology = c_tech_arria10_e1sg and c_dsp_dat_w <= c_dsp_mult_18_w generate
+ gen_ip_arria10_e1sg_ip : if g_variant ="IP " and g_technology = c_tech_arria10_e1sg and c_dsp_dat_w <= c_dsp_mult_18_w generate
-- Adapt DSP input widths
ar <= RESIZE_SVEC(in_ar, c_dsp_mult_18_w);
ai <= RESIZE_SVEC(in_ai, c_dsp_mult_18_w);
@@ -190,7 +190,7 @@ begin
result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
end generate;
- gen_ip_arria10_e2sg_ip : if g_variant ="IP " and g_technology = c_tech_arria10_e2sg and c_dsp_dat_w <= c_dsp_mult_18_w generate
+ gen_ip_arria10_e2sg_ip : if g_variant ="IP " and g_technology = c_tech_arria10_e2sg and c_dsp_dat_w <= c_dsp_mult_18_w generate
-- Adapt DSP input widths
ar <= RESIZE_SVEC(in_ar, c_dsp_mult_18_w);
ai <= RESIZE_SVEC(in_ai, c_dsp_mult_18_w);
@@ -220,7 +220,7 @@ begin
-- IP variants for > 18 bit and <= 27 bit
-----------------------------------------------------------------------------
- gen_ip_arria10_e1sg_ip_27b : if g_variant ="IP " and g_technology = c_tech_arria10_e1sg and c_dsp_dat_w > c_dsp_mult_18_w and c_dsp_dat_w <= c_dsp_mult_27_w generate
+ gen_ip_arria10_e1sg_ip_27b : if g_variant ="IP " and g_technology = c_tech_arria10_e1sg and c_dsp_dat_w > c_dsp_mult_18_w and c_dsp_dat_w <= c_dsp_mult_27_w generate
-- Adapt DSP input widths
ar <= RESIZE_SVEC(in_ar, c_dsp_mult_27_w);
ai <= RESIZE_SVEC(in_ai, c_dsp_mult_27_w);
@@ -245,7 +245,7 @@ begin
result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
end generate;
- gen_ip_arria10_e2sg_ip_27b : if g_variant ="IP " and g_technology = c_tech_arria10_e2sg and c_dsp_dat_w > c_dsp_mult_18_w and c_dsp_dat_w <= c_dsp_mult_27_w generate
+ gen_ip_arria10_e2sg_ip_27b : if g_variant ="IP " and g_technology = c_tech_arria10_e2sg and c_dsp_dat_w > c_dsp_mult_18_w and c_dsp_dat_w <= c_dsp_mult_27_w generate
-- Adapt DSP input widths
ar <= RESIZE_SVEC(in_ar, c_dsp_mult_27_w);
ai <= RESIZE_SVEC(in_ai, c_dsp_mult_27_w);
@@ -273,7 +273,7 @@ begin
-----------------------------------------------------------------------------
-- RTL variants that can infer multipliers for a technology, fits all widths
-----------------------------------------------------------------------------
- gen_ip_stratixiv_rtl : if g_variant ="RTL " and g_technology = c_tech_stratixiv generate
+ gen_ip_stratixiv_rtl : if g_variant ="RTL " and g_technology = c_tech_stratixiv generate
u0 : ip_stratixiv_complex_mult_rtl
generic map (
g_in_a_w => g_in_a_w,
@@ -299,7 +299,7 @@ begin
end generate;
-- RTL variant is the same for unb2, unb2a and unb2b
- gen_ip_arria10_rtl : if g_variant ="RTL " and (g_technology = c_tech_arria10_proto or
+ gen_ip_arria10_rtl : if g_variant ="RTL " and (g_technology = c_tech_arria10_proto or
g_technology = c_tech_arria10_e3sge3 or
g_technology = c_tech_arria10_e1sg or
g_technology = c_tech_arria10_e2sg) generate
@@ -328,7 +328,7 @@ begin
end generate;
-- RTL variant is the same for unb2, unb2a and unb2b
- gen_ip_arria10_rtl_canonical : if g_variant ="RTL_C " and (g_technology = c_tech_arria10_proto or
+ gen_ip_arria10_rtl_canonical : if g_variant ="RTL_C " and (g_technology = c_tech_arria10_proto or
g_technology = c_tech_arria10_e3sge3 or
g_technology = c_tech_arria10_e1sg or
g_technology = c_tech_arria10_e2sg) generate
@@ -358,4 +358,4 @@ begin
);
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/technology/mult/tech_mult.vhd b/libraries/technology/mult/tech_mult.vhd
index 2c15254f33573137e07aa8b36ddc97f43b187f59..b3fc8b5c5fe8b26007cc224aa216e37a46d50336 100644
--- a/libraries/technology/mult/tech_mult.vhd
+++ b/libraries/technology/mult/tech_mult.vhd
@@ -64,7 +64,7 @@ architecture str of tech_mult is
begin
- gen_ip_stratixiv_ip : if (g_technology = c_tech_stratixiv and g_variant ="IP ") generate
+ gen_ip_stratixiv_ip : if (g_technology = c_tech_stratixiv and g_variant ="IP ") generate
u0 : ip_stratixiv_mult
generic map(
g_in_a_w => g_in_a_w,
@@ -85,7 +85,7 @@ begin
);
end generate;
- gen_ip_stratixiv_rtl : if (g_technology = c_tech_stratixiv and g_variant ="RTL ") generate
+ gen_ip_stratixiv_rtl : if (g_technology = c_tech_stratixiv and g_variant ="RTL ") generate
u0 : ip_stratixiv_mult_rtl
generic map(
g_in_a_w => g_in_a_w,
@@ -107,7 +107,7 @@ begin
);
end generate;
- gen_ip_arria10_ip : if ((g_technology = c_tech_arria10_proto or g_technology = c_tech_arria10_e3sge3 or g_technology = c_tech_arria10_e1sg or g_technology = c_tech_arria10_e2sg ) and g_variant ="IP ") generate
+ gen_ip_arria10_ip : if ((g_technology = c_tech_arria10_proto or g_technology = c_tech_arria10_e3sge3 or g_technology = c_tech_arria10_e1sg or g_technology = c_tech_arria10_e2sg ) and g_variant ="IP ") generate
u0 : ip_arria10_mult
generic map(
g_in_a_w => g_in_a_w,
@@ -128,7 +128,7 @@ begin
);
end generate;
- gen_ip_arria10_rtl : if ((g_technology = c_tech_arria10_proto or g_technology = c_tech_arria10_e3sge3 or g_technology = c_tech_arria10_e1sg or g_technology = c_tech_arria10_e2sg ) and g_variant ="RTL ") generate
+ gen_ip_arria10_rtl : if ((g_technology = c_tech_arria10_proto or g_technology = c_tech_arria10_e3sge3 or g_technology = c_tech_arria10_e1sg or g_technology = c_tech_arria10_e2sg ) and g_variant ="RTL ") generate
u0 : ip_arria10_mult_rtl
generic map(
g_in_a_w => g_in_a_w,
@@ -152,8 +152,8 @@ begin
gen_trunk : for I in 0 to g_nof_mult - 1 generate
-- Truncate MSbits, also for signed (common_pkg.vhd for explanation of RESIZE_SVEC)
- out_p((I + 1) * g_out_p_w - 1 downto I * g_out_p_w) <= RESIZE_SVEC(prod((I + 1) * c_prod_w - 1 downto I * c_prod_w), g_out_p_w) when g_representation ="signed " else
+ out_p((I + 1) * g_out_p_w - 1 downto I * g_out_p_w) <= RESIZE_SVEC(prod((I + 1) * c_prod_w - 1 downto I * c_prod_w), g_out_p_w) when g_representation ="signed " else
RESIZE_UVEC(prod((I + 1) * c_prod_w - 1 downto I * c_prod_w), g_out_p_w);
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/technology/mult/tech_mult_add2.vhd b/libraries/technology/mult/tech_mult_add2.vhd
index c3fbcabeb6b17fc4219e4396810f1de84a551794..55d535520d648e033a9964c0400a65ae629dae07 100644
--- a/libraries/technology/mult/tech_mult_add2.vhd
+++ b/libraries/technology/mult/tech_mult_add2.vhd
@@ -60,7 +60,7 @@ architecture str of tech_mult_add2 is
begin
- gen_ip_stratixiv_rtl : if (g_technology = c_tech_stratixiv and g_variant ="RTL ") generate
+ gen_ip_stratixiv_rtl : if (g_technology = c_tech_stratixiv and g_variant ="RTL ") generate
u0 : ip_stratixiv_mult_add2_rtl
generic map(
g_in_a_w => g_in_a_w,
@@ -84,7 +84,7 @@ begin
);
end generate;
- gen_ip_arria10_e1sg_rtl : if (g_technology = c_tech_arria10_e1sg and g_variant ="RTL ") generate
+ gen_ip_arria10_e1sg_rtl : if (g_technology = c_tech_arria10_e1sg and g_variant ="RTL ") generate
u0 : ip_arria10_e1sg_mult_add2_rtl
generic map(
g_in_a_w => g_in_a_w,
@@ -108,7 +108,7 @@ begin
);
end generate;
- gen_ip_arria10_e2sg_rtl : if (g_technology = c_tech_arria10_e2sg and g_variant ="RTL ") generate
+ gen_ip_arria10_e2sg_rtl : if (g_technology = c_tech_arria10_e2sg and g_variant ="RTL ") generate
u0 : ip_arria10_e2sg_mult_add2_rtl
generic map(
g_in_a_w => g_in_a_w,
@@ -132,4 +132,4 @@ begin
);
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/technology/mult/tech_mult_add4.vhd b/libraries/technology/mult/tech_mult_add4.vhd
index d9eda2229a3e4b09ea1a1b042820119847184590..cefd9aa491d25faab8d6801bd8578254f49a16aa 100644
--- a/libraries/technology/mult/tech_mult_add4.vhd
+++ b/libraries/technology/mult/tech_mult_add4.vhd
@@ -63,7 +63,7 @@ architecture str of tech_mult_add4 is
begin
- gen_ip_stratixiv_rtl : if (g_technology = c_tech_stratixiv and g_variant ="RTL ") generate
+ gen_ip_stratixiv_rtl : if (g_technology = c_tech_stratixiv and g_variant ="RTL ") generate
u0 : ip_stratixiv_mult_add4_rtl
generic map(
g_in_a_w => g_in_a_w,
@@ -89,7 +89,7 @@ begin
);
end generate;
- gen_ip_arria10_e3sge3_rtl : if (g_technology = c_tech_arria10_e3sge3 and g_variant ="RTL ") generate
+ gen_ip_arria10_e3sge3_rtl : if (g_technology = c_tech_arria10_e3sge3 and g_variant ="RTL ") generate
u0 : ip_arria10_e3sge3_mult_add4_rtl
generic map(
g_in_a_w => g_in_a_w,
@@ -115,7 +115,7 @@ begin
);
end generate;
- gen_ip_arria10_e1sg_rtl : if (g_technology = c_tech_arria10_e1sg and g_variant ="RTL ") generate
+ gen_ip_arria10_e1sg_rtl : if (g_technology = c_tech_arria10_e1sg and g_variant ="RTL ") generate
u0 : ip_arria10_e1sg_mult_add4_rtl
generic map(
g_in_a_w => g_in_a_w,
@@ -141,7 +141,7 @@ begin
);
end generate;
- gen_ip_arria10_e2sg_rtl : if (g_technology = c_tech_arria10_e2sg and g_variant ="RTL ") generate
+ gen_ip_arria10_e2sg_rtl : if (g_technology = c_tech_arria10_e2sg and g_variant ="RTL ") generate
u0 : ip_arria10_e2sg_mult_add4_rtl
generic map(
g_in_a_w => g_in_a_w,
@@ -167,4 +167,4 @@ begin
);
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/technology/pll/tech_pll_component_pkg.vhd b/libraries/technology/pll/tech_pll_component_pkg.vhd
index e53bc0e706537297bd0381cef7f94d97d778d5bd..a6514568316804c572b11be4b97b2f5cbe7484f6 100644
--- a/libraries/technology/pll/tech_pll_component_pkg.vhd
+++ b/libraries/technology/pll/tech_pll_component_pkg.vhd
@@ -336,4 +336,4 @@ package tech_pll_component_pkg is
);
end component;
-end tech_pll_component_pkg;
+end tech_pll_component_pkg;
\ No newline at end of file
diff --git a/libraries/technology/technology_pkg.vhd b/libraries/technology/technology_pkg.vhd
index 6a404d99f8d01dd5a5c28ef1924977af542e47f6..2d0b552a9368912b27281a4d6f8f3b607dc0c0a3 100644
--- a/libraries/technology/technology_pkg.vhd
+++ b/libraries/technology/technology_pkg.vhd
@@ -1,4 +1,3 @@
-<<<<<<< HEAD
-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
@@ -50,7 +49,8 @@ package technology_pkg is
constant c_tech_arria10_e3sge3 : integer := 6; -- e.g. used on UniBoard2 second run (7 boards version "01" dec 2015)
constant c_tech_arria10_e1sg : integer := 7; -- e.g. used on UniBoard2b third run (5 ARTS boards version "01" feb 2017)
constant c_tech_arria10_e2sg : integer := 8; -- e.g. used on UniBoard2c (2 LOFAR2.0 SDP boards version "11" f 2021)
- constant c_tech_nof_technologies : integer := 9;
+ constant c_tech_ultrascale : integer := 9; -- e.g. used on Alveo FPGA platforms
+ constant c_tech_nof_technologies : integer := 10;
-- Functions
function tech_sel_a_b(sel : boolean; a, b : string) return string;
@@ -130,139 +130,4 @@ package body technology_pkg is
return r;
end;
-end technology_pkg;
-=======
--------------------------------------------------------------------------------
---
--- Copyright (C) 2014
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
--- Purpose: Define the list of FPGA technology identifiers
--- Description:
--- The technology dependent IP is organised per FPGA device type. Each FPGA
--- type that is supported has a c_tech_<device_name> identifier constant.
--- Remark:
--- . The package also contains some low level functions that often are copied
--- from common_pkg.vhd. They need to be redefined in this technology_pkg.vhd
--- because the common_lib also use technology dependent IP like RAM, FIFO,
--- DDIO. Therefore common_lib can not be used in the IP wrappers for those
--- IP blocks, because common_lib is compiled later.
--- . For technology wrappers that are not used by components in common_lib the
--- common_pkg.vhd can be used. Similar technology wrappers that are not used
--- by components in dp_lib can use the dp_stream_pkg.
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.MATH_REAL.ALL;
-
-PACKAGE technology_pkg IS
-
- -- Technology identifiers
- CONSTANT c_tech_inferred : INTEGER := 0;
- CONSTANT c_tech_virtex4 : INTEGER := 1; -- e.g. used on RSP3 for Lofar
- CONSTANT c_tech_stratixiv : INTEGER := 2; -- e.g. used on UniBoard1
- CONSTANT c_tech_virtex6 : INTEGER := 3; -- e.g. used on Roach2 for Casper
- CONSTANT c_tech_virtex7 : INTEGER := 4; -- e.g. used on Roach3 for Casper
- CONSTANT c_tech_arria10_proto : INTEGER := 5; -- e.g. used on UniBoard2 first proto (1 board version "00" may 2015)
- CONSTANT c_tech_arria10_e3sge3 : INTEGER := 6; -- e.g. used on UniBoard2 second run (7 boards version "01" dec 2015)
- CONSTANT c_tech_arria10_e1sg : INTEGER := 7; -- e.g. used on UniBoard2b third run (5 ARTS boards version "01" feb 2017)
- CONSTANT c_tech_arria10_e2sg : INTEGER := 8; -- e.g. used on UniBoard2c (2 LOFAR2.0 SDP boards version "11" f 2021)
- CONSTANT c_tech_ultrascale : INTEGER := 9; -- e.g. used on Alveo FPGA platforms
- CONSTANT c_tech_nof_technologies : INTEGER := 10;
-
- -- Functions
- FUNCTION tech_sel_a_b(sel : BOOLEAN; a, b : STRING) RETURN STRING;
- FUNCTION tech_sel_a_b(sel : BOOLEAN; a, b : INTEGER) RETURN INTEGER;
-
- FUNCTION tech_true_log2(n : NATURAL) RETURN NATURAL; -- tech_true_log2(n) = log2(n)
- FUNCTION tech_ceil_log2(n : NATURAL) RETURN NATURAL; -- tech_ceil_log2(n) = log2(n), but force tech_ceil_log2(1) = 1
-
- FUNCTION tech_ceil_div(n, d : NATURAL) RETURN NATURAL; -- tech_ceil_div = n/d + (n MOD d)/=0
-
- FUNCTION tech_nat_to_mbps_str( n : IN NATURAL ) RETURN STRING;
-
-END technology_pkg;
-
-PACKAGE BODY technology_pkg IS
-
- FUNCTION tech_sel_a_b(sel : BOOLEAN; a, b : STRING) RETURN STRING IS
- BEGIN
- IF sel=TRUE THEN RETURN a; ELSE RETURN b; END IF;
- END;
-
- FUNCTION tech_sel_a_b(sel : BOOLEAN; a, b : INTEGER) RETURN INTEGER IS
- BEGIN
- IF sel=TRUE THEN RETURN a; ELSE RETURN b; END IF;
- END;
-
- FUNCTION tech_true_log2(n : NATURAL) RETURN NATURAL IS
- -- Purpose: For calculating extra vector width of existing vector
- -- Description: Return mathematical ceil(log2(n))
- -- n log2()
- -- 0 -> -oo --> FAILURE
- -- 1 -> 0
- -- 2 -> 1
- -- 3 -> 2
- -- 4 -> 2
- -- 5 -> 3
- -- 6 -> 3
- -- 7 -> 3
- -- 8 -> 3
- -- 9 -> 4
- -- etc, up to n = NATURAL'HIGH = 2**31-1
- BEGIN
- RETURN natural(integer(ceil(log2(real(n)))));
- END;
-
- FUNCTION tech_ceil_log2(n : NATURAL) RETURN NATURAL IS
- -- Purpose: For calculating vector width of new vector
- -- Description:
- -- Same as tech_true_log2() except tech_ceil_log2(1) = 1, which is needed to support
- -- the vector width width for 1 address, to avoid NULL array for single
- -- word register address.
- BEGIN
- IF n = 1 THEN
- RETURN 1; -- avoid NULL array
- ELSE
- RETURN tech_true_log2(n);
- END IF;
- END;
-
- FUNCTION tech_ceil_div(n, d : NATURAL) RETURN NATURAL IS
- BEGIN
- RETURN n/d + tech_sel_a_b(n MOD d = 0, 0, 1);
- END;
-
- FUNCTION tech_nat_to_mbps_str( n : IN NATURAL ) RETURN STRING IS -- Converts a selection of naturals to Mbps strings, used for edited MegaWizard file in ip_stratixiv_hssi_*_generic.vhd
- VARIABLE r : STRING(1 TO 9);
- BEGIN
- CASE n is
- WHEN 2500 => r := "2500 Mbps";
- WHEN 3125 => r := "3125 Mbps";
- WHEN 5000 => r := "5000 Mbps";
- WHEN 6250 => r := "6250 Mbps";
- WHEN OTHERS =>
- r := "ERROR: tech_nat_to_mbps_str UNSUPPORTED DATA RATE"; -- This too long string will cause an error in Quartus synthesis
- REPORT r SEVERITY FAILURE; -- Severity Failure will stop the Modelsim simulation
- END CASE;
- RETURN r;
- END;
-
-END technology_pkg;
->>>>>>> master
+end technology_pkg;
\ No newline at end of file
diff --git a/libraries/technology/transceiver/sim_transceiver_gx.vhd b/libraries/technology/transceiver/sim_transceiver_gx.vhd
index 1644d3fab3d0a5ed1ec5e80728734d686efbde73..cd32efea2a9924cfda5baa4bb775514e74e7a651 100644
--- a/libraries/technology/transceiver/sim_transceiver_gx.vhd
+++ b/libraries/technology/transceiver/sim_transceiver_gx.vhd
@@ -238,4 +238,4 @@ begin
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/technology/transceiver/tech_transceiver_gx.vhd b/libraries/technology/transceiver/tech_transceiver_gx.vhd
index 1125d2eb2bfa3c94e2e6c0b4af36ad0af0ff6192..d39e33031c62fe34152e7be92ad95e7cd9e0af51 100644
--- a/libraries/technology/transceiver/tech_transceiver_gx.vhd
+++ b/libraries/technology/transceiver/tech_transceiver_gx.vhd
@@ -75,4 +75,4 @@ begin
port map (cal_rec_clk, tr_clk, rx_clk, rx_rst, rx_sosi_arr, rx_siso_arr, tx_clk, tx_rst, tx_sosi_arr, tx_siso_arr, rx_datain, tx_dataout, tx_state, tx_align_en, rx_state, rx_align_en);
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/technology/transceiver/tech_transceiver_gx_stratixiv.vhd b/libraries/technology/transceiver/tech_transceiver_gx_stratixiv.vhd
index 068da0ad4b0600a1ca9ee270c999b00256c4f433..fdb9147086f8451f1e6f8142660d12650bf59489 100644
--- a/libraries/technology/transceiver/tech_transceiver_gx_stratixiv.vhd
+++ b/libraries/technology/transceiver/tech_transceiver_gx_stratixiv.vhd
@@ -498,4 +498,4 @@ begin
reconfig_togxb => reconfig_togxb
);
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/technology/transceiver/tech_transceiver_rx_align.vhd b/libraries/technology/transceiver/tech_transceiver_rx_align.vhd
index bb2256c6699f369fe9ccb1ecccda17442f58a23d..5fe1e19bec74a20fa2780f8aee87a11ea970d2ed 100644
--- a/libraries/technology/transceiver/tech_transceiver_rx_align.vhd
+++ b/libraries/technology/transceiver/tech_transceiver_rx_align.vhd
@@ -158,4 +158,4 @@ begin
end case;
end process;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/technology/transceiver/tech_transceiver_rx_rst.vhd b/libraries/technology/transceiver/tech_transceiver_rx_rst.vhd
index 1945c6f918591f712832bc07f12d940174df7e93..cdf7e26b7d3cb09e88b0232a92e32f7b7f43bb11 100644
--- a/libraries/technology/transceiver/tech_transceiver_rx_rst.vhd
+++ b/libraries/technology/transceiver/tech_transceiver_rx_rst.vhd
@@ -152,4 +152,4 @@ begin
);
end generate;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/technology/transceiver/tech_transceiver_tx_align.vhd b/libraries/technology/transceiver/tech_transceiver_tx_align.vhd
index 764a989739a7adb0840ee56303f6f4f1e716d027..d023bc84a50ac7ae12271562d1274d310c5fa09f 100644
--- a/libraries/technology/transceiver/tech_transceiver_tx_align.vhd
+++ b/libraries/technology/transceiver/tech_transceiver_tx_align.vhd
@@ -124,4 +124,4 @@ begin
end case;
end process;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/technology/transceiver/tech_transceiver_tx_rst.vhd b/libraries/technology/transceiver/tech_transceiver_tx_rst.vhd
index 197297024e039f5f1363e95818cafac50b3ba960..4057c9df47ee4acb7f1470cadefc05040717a383 100644
--- a/libraries/technology/transceiver/tech_transceiver_tx_rst.vhd
+++ b/libraries/technology/transceiver/tech_transceiver_tx_rst.vhd
@@ -135,4 +135,4 @@ begin
);
end generate;
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/technology/xaui/sim_xaui.vhd b/libraries/technology/xaui/sim_xaui.vhd
index 2606e846f52d33b50a5ba59cab6ee1f6a83a3bd2..fda78983ea89301ef76fd2a63dadb78eb023a534 100644
--- a/libraries/technology/xaui/sim_xaui.vhd
+++ b/libraries/technology/xaui/sim_xaui.vhd
@@ -177,4 +177,4 @@ begin
end generate;
-end wrap;
+end wrap;
\ No newline at end of file
diff --git a/libraries/technology/xaui/tech_xaui.vhd b/libraries/technology/xaui/tech_xaui.vhd
index 697906390dc917198079098debc6551fac9d1c1c..c4baadedd389c72c0706000830cd0413cf324353 100644
--- a/libraries/technology/xaui/tech_xaui.vhd
+++ b/libraries/technology/xaui/tech_xaui.vhd
@@ -97,4 +97,4 @@ begin
xaui_tx_arr, xaui_rx_arr);
end generate;
-end str;
+end str;
\ No newline at end of file
diff --git a/libraries/technology/xaui/tech_xaui_align_dly.vhd b/libraries/technology/xaui/tech_xaui_align_dly.vhd
index 7839ddf640128d7e088aa2541213c17667430510..c6acca48b286528723c485398c497aa71bebacb4 100644
--- a/libraries/technology/xaui/tech_xaui_align_dly.vhd
+++ b/libraries/technology/xaui/tech_xaui_align_dly.vhd
@@ -67,4 +67,4 @@ begin
q_out => txc_rx_channelaligned_dly
);
-end rtl;
+end rtl;
\ No newline at end of file
diff --git a/libraries/technology/xaui/tech_xaui_stratixiv.vhd b/libraries/technology/xaui/tech_xaui_stratixiv.vhd
index 5923eaafd968aa9561dcabf7acf1a29119d82207..aa2530bf1c628a6cb00ce34c05e8f3467766ae36 100644
--- a/libraries/technology/xaui/tech_xaui_stratixiv.vhd
+++ b/libraries/technology/xaui/tech_xaui_stratixiv.vhd
@@ -328,4 +328,4 @@ begin
miso_arr => xaui_miso_arr
);
-end str;
+end str;
\ No newline at end of file
diff --git a/vhdl_style_fix.py b/vhdl_style_fix.py
index 4574106bcdabe7d0855c64d04618eb95b8e84c97..58e189437dc88ea4d3829dafc1ab734600f64023 100755
--- a/vhdl_style_fix.py
+++ b/vhdl_style_fix.py
@@ -133,8 +133,11 @@ class AddSpacesAroundOperators(BaseCheck):
operator += ch
else:
isoperator = True
- if new_line[-1] not in [" ", "("]:
- new_line.append(' ')
+ try:
+ if new_line[-1] not in [" ", "("]:
+ new_line.append(' ')
+ except IndexError:
+ pass
operator += ch
elif isoperator and ch.isnumeric():
@@ -292,8 +295,6 @@ class CaseResolutions(BaseCheck):
for i in range(self.n_data):
line = self.data[i]
sline = self.splitline(line)
- if sline:
- print(f"CaseResolution: {sline}")
for word in sline:
if word[-1] == ';':
word = word[:-1]