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Commit b3b8b1ab authored by Daniel van der Schuur's avatar Daniel van der Schuur
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-Removed the old, commented out QSYS component declaration.

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applications/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
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− 155
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...@@ -110,165 +110,97 @@ ARCHITECTURE str OF mmm_unb1_correlator IS ...@@ -110,165 +110,97 @@ ARCHITECTURE str OF mmm_unb1_correlator IS
); );
END COMPONENT; END COMPONENT;
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus v11.1 QSYS builder -- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- COMPONENT qsys_unb1_correlator is component qsys_unb1_correlator is
-- PORT ( port (
-- coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
-- coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
-- mm_clk : out std_logic; -- clk mm_clk : out std_logic; -- clk
-- coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
-- coe_address_export_from_the_pio_pps : out std_logic;--_vector(0 downto 0); -- export coe_address_export_from_the_pio_pps : out std_logic;--_vector(0 downto 0); -- export
-- coe_reset_export_from_the_pio_pps : out std_logic; -- export coe_reset_export_from_the_pio_pps : out std_logic; -- export
-- coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
-- coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
-- coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
-- coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
-- coe_reset_export_from_the_reg_wdi : out std_logic; -- export coe_reset_export_from_the_reg_wdi : out std_logic; -- export
-- coe_clk_export_from_the_rom_system_info : out std_logic; -- export coe_clk_export_from_the_rom_system_info : out std_logic; -- export
-- coe_read_export_from_the_reg_unb_sens : out std_logic; -- export coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
-- coe_write_export_from_the_reg_unb_sens : out std_logic; -- export coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
-- coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
-- coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
-- coe_read_export_from_the_reg_wdi : out std_logic; -- export coe_read_export_from_the_reg_wdi : out std_logic; -- export
-- coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
-- coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
-- coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
-- coe_clk_export_from_the_pio_pps : out std_logic; -- export coe_clk_export_from_the_pio_pps : out std_logic; -- export
-- coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
-- coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
-- coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export coe_address_export_from_the_reg_wdi : out std_logic;--_vector(0 downto 0); -- export
-- coe_address_export_from_the_reg_wdi : out std_logic;--_vector(0 downto 0); -- export coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
-- coe_write_export_from_the_pio_system_info : out std_logic; -- export coe_write_export_from_the_pio_system_info : out std_logic; -- export
-- coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
-- coe_write_export_from_the_pio_pps : out std_logic; -- export coe_write_export_from_the_pio_pps : out std_logic; -- export
-- coe_write_export_from_the_rom_system_info : out std_logic; -- export coe_write_export_from_the_rom_system_info : out std_logic; -- export
-- coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
-- phasedone_from_the_altpll_0 : out std_logic; -- export coe_read_export_from_the_rom_system_info : out std_logic; -- export
-- coe_read_export_from_the_rom_system_info : out std_logic; -- export phasedone_from_the_altpll_0 : out std_logic; -- export
-- reset_n : in std_logic := 'X'; -- reset_n reset_n : in std_logic := 'X'; -- reset_n
-- coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
-- coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
-- coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
-- clk_0 : in std_logic := 'X'; -- clk clk_0 : in std_logic := 'X'; -- clk
-- coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
-- tse_clk : out std_logic; -- clk tse_clk : out std_logic; -- clk
-- coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export epcs_clk : out std_logic; -- clk
-- epcs_clk : out std_logic; -- clk coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
-- coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export out_port_from_the_pio_debug_wave : out std_logic_vector(31 downto 0); -- export
-- out_port_from_the_pio_debug_wave : out std_logic_vector(31 downto 0); -- export coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
-- coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
-- coe_reset_export_from_the_pio_system_info : out std_logic; -- export coe_reset_export_from_the_pio_system_info : out std_logic; -- export
-- coe_read_export_from_the_pio_system_info : out std_logic; -- export coe_read_export_from_the_pio_system_info : out std_logic; -- export
-- coe_clk_export_from_the_reg_wdi : out std_logic; -- export coe_clk_export_from_the_reg_wdi : out std_logic; -- export
-- coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
-- out_port_from_the_pio_wdi : out std_logic; -- export out_port_from_the_pio_wdi : out std_logic; -- export
-- coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
-- coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
-- coe_write_export_from_the_reg_wdi : out std_logic; -- export coe_write_export_from_the_reg_wdi : out std_logic; -- export
-- coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
-- coe_read_export_from_the_pio_pps : out std_logic; -- export coe_read_export_from_the_pio_pps : out std_logic; -- export
-- coe_clk_export_from_the_pio_system_info : out std_logic; -- export coe_clk_export_from_the_pio_system_info : out std_logic; -- export
-- coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
-- coe_reset_export_from_the_rom_system_info : out std_logic; -- export coe_reset_export_from_the_rom_system_info : out std_logic; -- export
-- coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
-- coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
-- coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
-- coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
-- areset_to_the_altpll_0 : in std_logic := 'X'; -- export areset_to_the_altpll_0 : in std_logic := 'X'; -- export
-- locked_from_the_altpll_0 : out std_logic; -- export locked_from_the_altpll_0 : out std_logic; -- export
-- coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0) -- export coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
-- ); c3_from_the_altpll_0 : out std_logic; -- export
-- end component qsys_unb1_correlator; ram_diag_data_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
component qsys_unb1_correlator is ram_diag_data_buf_read_export : out std_logic; -- export
port ( ram_diag_data_buf_writedata_export : out std_logic_vector(31 downto 0); -- export
coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export ram_diag_data_buf_write_export : out std_logic; -- export
coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export ram_diag_data_buf_address_export : out std_logic_vector(16 downto 0); -- export
mm_clk : out std_logic; -- clk ram_diag_data_buf_clk_export : out std_logic; -- export
coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export ram_diag_data_buf_reset_export : out std_logic; -- export
coe_address_export_from_the_pio_pps : out std_logic;--_vector(0 downto 0); -- export reg_diag_data_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
coe_reset_export_from_the_pio_pps : out std_logic; -- export reg_diag_data_buf_read_export : out std_logic; -- export
coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export reg_diag_data_buf_writedata_export : out std_logic_vector(31 downto 0); -- export
coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export reg_diag_data_buf_write_export : out std_logic; -- export
coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export reg_diag_data_buf_address_export : out std_logic_vector(9 downto 0); -- export
coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export reg_diag_data_buf_clk_export : out std_logic; -- export
coe_reset_export_from_the_reg_wdi : out std_logic; -- export reg_diag_data_buf_reset_export : out std_logic -- export
coe_clk_export_from_the_rom_system_info : out std_logic; -- export );
coe_read_export_from_the_reg_unb_sens : out std_logic; -- export end component qsys_unb1_correlator;
coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
coe_read_export_from_the_reg_wdi : out std_logic; -- export
coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
coe_clk_export_from_the_pio_pps : out std_logic; -- export
coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
coe_address_export_from_the_reg_wdi : out std_logic;--_vector(0 downto 0); -- export
coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
coe_write_export_from_the_pio_system_info : out std_logic; -- export
coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
coe_write_export_from_the_pio_pps : out std_logic; -- export
coe_write_export_from_the_rom_system_info : out std_logic; -- export
coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
coe_read_export_from_the_rom_system_info : out std_logic; -- export
phasedone_from_the_altpll_0 : out std_logic; -- export
reset_n : in std_logic := 'X'; -- reset_n
coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
clk_0 : in std_logic := 'X'; -- clk
coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
tse_clk : out std_logic; -- clk
epcs_clk : out std_logic; -- clk
coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
out_port_from_the_pio_debug_wave : out std_logic_vector(31 downto 0); -- export
coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
coe_reset_export_from_the_pio_system_info : out std_logic; -- export
coe_read_export_from_the_pio_system_info : out std_logic; -- export
coe_clk_export_from_the_reg_wdi : out std_logic; -- export
coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
out_port_from_the_pio_wdi : out std_logic; -- export
coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
coe_write_export_from_the_reg_wdi : out std_logic; -- export
coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
coe_read_export_from_the_pio_pps : out std_logic; -- export
coe_clk_export_from_the_pio_system_info : out std_logic; -- export
coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
coe_reset_export_from_the_rom_system_info : out std_logic; -- export
coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
areset_to_the_altpll_0 : in std_logic := 'X'; -- export
locked_from_the_altpll_0 : out std_logic; -- export
coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
c3_from_the_altpll_0 : out std_logic; -- export
ram_diag_data_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
ram_diag_data_buf_read_export : out std_logic; -- export
ram_diag_data_buf_writedata_export : out std_logic_vector(31 downto 0); -- export
ram_diag_data_buf_write_export : out std_logic; -- export
ram_diag_data_buf_address_export : out std_logic_vector(16 downto 0); -- export
ram_diag_data_buf_clk_export : out std_logic; -- export
ram_diag_data_buf_reset_export : out std_logic; -- export
reg_diag_data_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_diag_data_buf_read_export : out std_logic; -- export
reg_diag_data_buf_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_diag_data_buf_write_export : out std_logic; -- export
reg_diag_data_buf_address_export : out std_logic_vector(9 downto 0); -- export
reg_diag_data_buf_clk_export : out std_logic; -- export
reg_diag_data_buf_reset_export : out std_logic -- export
);
end component qsys_unb1_correlator;
BEGIN BEGIN
mm_clk <= i_mm_clk; mm_clk <= i_mm_clk;
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $UPE/sim. -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
......
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