From b3b8b1ab65eeca57aaf35ce69bfd31050c20e56b Mon Sep 17 00:00:00 2001 From: Daniel van der Schuur <schuur@astron.nl> Date: Tue, 18 Nov 2014 15:58:21 +0000 Subject: [PATCH] -Removed the old, commented out QSYS component declaration. --- .../src/vhdl/mmm_unb1_correlator.vhd | 242 +++++++----------- 1 file changed, 87 insertions(+), 155 deletions(-) diff --git a/applications/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd b/applications/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd index fef5b02dd1..dd6fbcb5a1 100644 --- a/applications/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd +++ b/applications/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd @@ -110,165 +110,97 @@ ARCHITECTURE str OF mmm_unb1_correlator IS ); END COMPONENT; - ----------------------------------------------------------------------------- - -- this component declaration is copy-pasted from Quartus v11.1 QSYS builder - ----------------------------------------------------------------------------- --- COMPONENT qsys_unb1_correlator is --- PORT ( --- coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export --- coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export --- mm_clk : out std_logic; -- clk --- coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export --- coe_address_export_from_the_pio_pps : out std_logic;--_vector(0 downto 0); -- export --- coe_reset_export_from_the_pio_pps : out std_logic; -- export --- coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export --- coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export --- coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export --- coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export --- coe_reset_export_from_the_reg_wdi : out std_logic; -- export --- coe_clk_export_from_the_rom_system_info : out std_logic; -- export --- coe_read_export_from_the_reg_unb_sens : out std_logic; -- export --- coe_write_export_from_the_reg_unb_sens : out std_logic; -- export --- coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export --- coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export --- coe_read_export_from_the_reg_wdi : out std_logic; -- export --- coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export --- coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export --- coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export --- coe_clk_export_from_the_pio_pps : out std_logic; -- export --- coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export --- coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export --- coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export --- coe_address_export_from_the_reg_wdi : out std_logic;--_vector(0 downto 0); -- export --- coe_write_export_from_the_pio_system_info : out std_logic; -- export --- coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export --- coe_write_export_from_the_pio_pps : out std_logic; -- export --- coe_write_export_from_the_rom_system_info : out std_logic; -- export --- coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export --- phasedone_from_the_altpll_0 : out std_logic; -- export --- coe_read_export_from_the_rom_system_info : out std_logic; -- export --- reset_n : in std_logic := 'X'; -- reset_n --- coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export --- coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export --- coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export --- clk_0 : in std_logic := 'X'; -- clk --- coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export --- tse_clk : out std_logic; -- clk --- coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export --- epcs_clk : out std_logic; -- clk --- coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export --- out_port_from_the_pio_debug_wave : out std_logic_vector(31 downto 0); -- export --- coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export --- coe_reset_export_from_the_pio_system_info : out std_logic; -- export --- coe_read_export_from_the_pio_system_info : out std_logic; -- export --- coe_clk_export_from_the_reg_wdi : out std_logic; -- export --- coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export --- out_port_from_the_pio_wdi : out std_logic; -- export --- coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export --- coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export --- coe_write_export_from_the_reg_wdi : out std_logic; -- export --- coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export --- coe_read_export_from_the_pio_pps : out std_logic; -- export --- coe_clk_export_from_the_pio_system_info : out std_logic; -- export --- coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export --- coe_reset_export_from_the_rom_system_info : out std_logic; -- export --- coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export --- coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export --- coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export --- coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export --- areset_to_the_altpll_0 : in std_logic := 'X'; -- export --- locked_from_the_altpll_0 : out std_logic; -- export --- coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0) -- export --- ); --- end component qsys_unb1_correlator; - component qsys_unb1_correlator is - port ( - coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export - coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export - mm_clk : out std_logic; -- clk - coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export - coe_address_export_from_the_pio_pps : out std_logic;--_vector(0 downto 0); -- export - coe_reset_export_from_the_pio_pps : out std_logic; -- export - coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export - coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export - coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export - coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export - coe_reset_export_from_the_reg_wdi : out std_logic; -- export - coe_clk_export_from_the_rom_system_info : out std_logic; -- export - coe_read_export_from_the_reg_unb_sens : out std_logic; -- export - coe_write_export_from_the_reg_unb_sens : out std_logic; -- export - coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export - coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export - coe_read_export_from_the_reg_wdi : out std_logic; -- export - coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export - coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export - coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export - coe_clk_export_from_the_pio_pps : out std_logic; -- export - coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export - coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export - coe_address_export_from_the_reg_wdi : out std_logic;--_vector(0 downto 0); -- export - coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export - coe_write_export_from_the_pio_system_info : out std_logic; -- export - coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export - coe_write_export_from_the_pio_pps : out std_logic; -- export - coe_write_export_from_the_rom_system_info : out std_logic; -- export - coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export - coe_read_export_from_the_rom_system_info : out std_logic; -- export - phasedone_from_the_altpll_0 : out std_logic; -- export - reset_n : in std_logic := 'X'; -- reset_n - coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export - coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export - coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export - clk_0 : in std_logic := 'X'; -- clk - coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export - tse_clk : out std_logic; -- clk - epcs_clk : out std_logic; -- clk - coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export - out_port_from_the_pio_debug_wave : out std_logic_vector(31 downto 0); -- export - coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export - coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export - coe_reset_export_from_the_pio_system_info : out std_logic; -- export - coe_read_export_from_the_pio_system_info : out std_logic; -- export - coe_clk_export_from_the_reg_wdi : out std_logic; -- export - coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export - out_port_from_the_pio_wdi : out std_logic; -- export - coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export - coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export - coe_write_export_from_the_reg_wdi : out std_logic; -- export - coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export - coe_read_export_from_the_pio_pps : out std_logic; -- export - coe_clk_export_from_the_pio_system_info : out std_logic; -- export - coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export - coe_reset_export_from_the_rom_system_info : out std_logic; -- export - coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export - coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export - coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export - coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export - areset_to_the_altpll_0 : in std_logic := 'X'; -- export - locked_from_the_altpll_0 : out std_logic; -- export - coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export - c3_from_the_altpll_0 : out std_logic; -- export - ram_diag_data_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export - ram_diag_data_buf_read_export : out std_logic; -- export - ram_diag_data_buf_writedata_export : out std_logic_vector(31 downto 0); -- export - ram_diag_data_buf_write_export : out std_logic; -- export - ram_diag_data_buf_address_export : out std_logic_vector(16 downto 0); -- export - ram_diag_data_buf_clk_export : out std_logic; -- export - ram_diag_data_buf_reset_export : out std_logic; -- export - reg_diag_data_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export - reg_diag_data_buf_read_export : out std_logic; -- export - reg_diag_data_buf_writedata_export : out std_logic_vector(31 downto 0); -- export - reg_diag_data_buf_write_export : out std_logic; -- export - reg_diag_data_buf_address_export : out std_logic_vector(9 downto 0); -- export - reg_diag_data_buf_clk_export : out std_logic; -- export - reg_diag_data_buf_reset_export : out std_logic -- export - ); - end component qsys_unb1_correlator; + ----------------------------------------------------------------------------- + -- this component declaration is copy-pasted from Quartus v11.1 QSYS builder + ----------------------------------------------------------------------------- + component qsys_unb1_correlator is + port ( + coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export + coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export + mm_clk : out std_logic; -- clk + coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export + coe_address_export_from_the_pio_pps : out std_logic;--_vector(0 downto 0); -- export + coe_reset_export_from_the_pio_pps : out std_logic; -- export + coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export + coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export + coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export + coe_reset_export_from_the_reg_wdi : out std_logic; -- export + coe_clk_export_from_the_rom_system_info : out std_logic; -- export + coe_read_export_from_the_reg_unb_sens : out std_logic; -- export + coe_write_export_from_the_reg_unb_sens : out std_logic; -- export + coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export + coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export + coe_read_export_from_the_reg_wdi : out std_logic; -- export + coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export + coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export + coe_clk_export_from_the_pio_pps : out std_logic; -- export + coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export + coe_address_export_from_the_reg_wdi : out std_logic;--_vector(0 downto 0); -- export + coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export + coe_write_export_from_the_pio_system_info : out std_logic; -- export + coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export + coe_write_export_from_the_pio_pps : out std_logic; -- export + coe_write_export_from_the_rom_system_info : out std_logic; -- export + coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export + coe_read_export_from_the_rom_system_info : out std_logic; -- export + phasedone_from_the_altpll_0 : out std_logic; -- export + reset_n : in std_logic := 'X'; -- reset_n + coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export + coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export + clk_0 : in std_logic := 'X'; -- clk + coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export + tse_clk : out std_logic; -- clk + epcs_clk : out std_logic; -- clk + coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + out_port_from_the_pio_debug_wave : out std_logic_vector(31 downto 0); -- export + coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export + coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export + coe_reset_export_from_the_pio_system_info : out std_logic; -- export + coe_read_export_from_the_pio_system_info : out std_logic; -- export + coe_clk_export_from_the_reg_wdi : out std_logic; -- export + coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + out_port_from_the_pio_wdi : out std_logic; -- export + coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export + coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + coe_write_export_from_the_reg_wdi : out std_logic; -- export + coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + coe_read_export_from_the_pio_pps : out std_logic; -- export + coe_clk_export_from_the_pio_system_info : out std_logic; -- export + coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export + coe_reset_export_from_the_rom_system_info : out std_logic; -- export + coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export + coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export + coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export + coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export + areset_to_the_altpll_0 : in std_logic := 'X'; -- export + locked_from_the_altpll_0 : out std_logic; -- export + coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export + c3_from_the_altpll_0 : out std_logic; -- export + ram_diag_data_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + ram_diag_data_buf_read_export : out std_logic; -- export + ram_diag_data_buf_writedata_export : out std_logic_vector(31 downto 0); -- export + ram_diag_data_buf_write_export : out std_logic; -- export + ram_diag_data_buf_address_export : out std_logic_vector(16 downto 0); -- export + ram_diag_data_buf_clk_export : out std_logic; -- export + ram_diag_data_buf_reset_export : out std_logic; -- export + reg_diag_data_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + reg_diag_data_buf_read_export : out std_logic; -- export + reg_diag_data_buf_writedata_export : out std_logic_vector(31 downto 0); -- export + reg_diag_data_buf_write_export : out std_logic; -- export + reg_diag_data_buf_address_export : out std_logic_vector(9 downto 0); -- export + reg_diag_data_buf_clk_export : out std_logic; -- export + reg_diag_data_buf_reset_export : out std_logic -- export + ); + end component qsys_unb1_correlator; + BEGIN mm_clk <= i_mm_clk; - ---------------------------------------------------------------------------- -- MM <-> file I/O for simulation. The files are created in $UPE/sim. ---------------------------------------------------------------------------- -- GitLab