From b37db3e92251936ac7efc2f01764143a0529d476 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Tue, 9 Dec 2014 08:59:01 +0000
Subject: [PATCH] Time tx_ready and rx_ready after tr_rst release. Otherwise
tb_tb_tech_eth_10g u_sim misses the first packets.
---
libraries/technology/10gbase_r/sim_10gbase_r.vhd | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/libraries/technology/10gbase_r/sim_10gbase_r.vhd b/libraries/technology/10gbase_r/sim_10gbase_r.vhd
index 70b51d810b..47a50376b9 100644
--- a/libraries/technology/10gbase_r/sim_10gbase_r.vhd
+++ b/libraries/technology/10gbase_r/sim_10gbase_r.vhd
@@ -93,7 +93,7 @@ BEGIN
)
PORT MAP(
clk => clk_156,
- in_rst => '0',
+ in_rst => rst_156,
out_rst => xgmii_tx_ready_arr(i)
);
@@ -105,7 +105,7 @@ BEGIN
)
PORT MAP(
clk => clk_156,
- in_rst => '0',
+ in_rst => rst_156,
out_rst => xgmii_rx_ready_arr(i)
);
--
GitLab