Made tb_aduh_mean_sum and tb_aduh_power_sum self checking and added them to...

Made tb_aduh_mean_sum and tb_aduh_power_sum self checking and added them to the ADUH regression test.

libraries/io/aduh/hdllib.cfg

@@ -39,6 +39,8 @@ test_bench_files =
 
 regression_test_vhdl = 
     tb/vhdl/tb_aduh_dd.vhd
+    tb/vhdl/tb_aduh_mean_sum.vhd
+    tb/vhdl/tb_aduh_power_sum.vhd
     tb/vhdl/tb_aduh_verify.vhd
     tb/vhdl/tb_mms_aduh_quad.vhd
     tb/vhdl/tb_tb_lvdsh_dd_phs4.vhd

libraries/io/aduh/tb/vhdl/tb_aduh_mean_sum.vhd

@@ -34,7 +34,7 @@ USE dp_lib.tb_dp_pkg.ALL;
 -- > as 10
 -- > run 1 us
 -- observe in_sosi, sum and sum_sync in wave window
--- expected sum after sum_sync are: 0, 120, 376, ...
+-- expected sum at sum_sync are: 0, 120, 376, ...
 -- . sum([ 0:15]) = 120
 -- . sum([16:31]) = 376
 -- . sum([32:47]) = 632
@@ -42,7 +42,8 @@ USE dp_lib.tb_dp_pkg.ALL;
 
 ENTITY tb_aduh_mean_sum IS
   GENERIC (
-    g_random_control : BOOLEAN := TRUE  -- use TRUE for random stream flow control, use FALSE for initial debugging
+    g_nof_symbols_per_data  : NATURAL := 1;    -- choose 1 or 4, nof symbols (= ADC samples) per data word
+    g_random_control        : BOOLEAN := TRUE  -- use TRUE for random stream flow control, use FALSE for initial debugging
   );
 END tb_aduh_mean_sum;
 
@@ -53,20 +54,22 @@ ARCHITECTURE tb OF tb_aduh_mean_sum IS
   
   CONSTANT c_rl                    : NATURAL := 1;
   CONSTANT c_symbol_w              : NATURAL := 8;
-  CONSTANT c_nof_symbols_per_data  : NATURAL := 4;
-  CONSTANT c_nof_symbols_per_block : NATURAL := 8;         -- nof symbols (= ADC samples) per block
   
   CONSTANT c_sum_truncate          : BOOLEAN := TRUE;
   CONSTANT c_sum_w                 : NATURAL := c_word_w;   -- = 32
   
-  CONSTANT c_data_w                : NATURAL := c_nof_symbols_per_data*c_symbol_w;
+  CONSTANT c_data_w                : NATURAL := g_nof_symbols_per_data*c_symbol_w;
   
   CONSTANT c_nof_sync              : NATURAL := 10;
   CONSTANT c_nof_block_per_sync    : NATURAL := 2;
+  CONSTANT c_nof_symbols_per_block : NATURAL := 8;    -- nof symbols (= ADC samples) per block
   CONSTANT c_nof_symbols_per_sync  : NATURAL := c_nof_block_per_sync * c_nof_symbols_per_block;
   
   CONSTANT c_nof_accumulations     : NATURAL := c_nof_symbols_per_sync;  -- integration time in symbols
   
+  CONSTANT c_exp_sum_arr           : t_natural_arr(0 TO 3) := (0, 120, 376, 632);
+  
+  SIGNAL tb_almost_end   : STD_LOGIC := '0';
   SIGNAL tb_end          : STD_LOGIC := '0';
   SIGNAL rst             : STD_LOGIC;
   SIGNAL clk             : STD_LOGIC := '1';
@@ -75,7 +78,6 @@ ARCHITECTURE tb OF tb_aduh_mean_sum IS
   
   SIGNAL st_en           : STD_LOGIC := '1';
   SIGNAL st_sosi         : t_dp_sosi := c_dp_sosi_rst;
-  SIGNAL st_sosi_dly     : t_dp_sosi := c_dp_sosi_rst;
   SIGNAL st_siso         : t_dp_siso := c_dp_siso_rdy;
   
   SIGNAL bsn             : NATURAL;
@@ -84,7 +86,8 @@ ARCHITECTURE tb OF tb_aduh_mean_sum IS
   
   SIGNAL sum             : STD_LOGIC_VECTOR(c_sum_w-1 DOWNTO 0);
   SIGNAL sum_sync        : STD_LOGIC;
-  SIGNAL sum_sop         : STD_LOGIC;
+  
+  SIGNAL verify_done     : STD_LOGIC := '0';
   
 BEGIN
 
@@ -117,28 +120,27 @@ BEGIN
     END LOOP;
     
     st_sosi <= c_dp_sosi_rst;
-    proc_common_wait_some_cycles(clk, 15);
+    proc_common_wait_some_cycles(clk, 10);
+    proc_common_gen_pulse(clk, tb_almost_end);
+    proc_common_wait_some_cycles(clk, 10);
     tb_end <= '1';
     WAIT;
   END PROCESS;
 
-  st_sosi_dly <= st_sosi WHEN rising_edge(clk);
-
   -- Time stimuli  
-  bsn <= bsn + 1 WHEN rising_edge(clk) AND st_sosi.sync='1';
+  bsn <= bsn + 1 WHEN rising_edge(clk) AND st_sosi.eop='1';
   
   -- Add BSN to the ST data
-  p_in_sosi : PROCESS(st_sosi, st_sosi_dly, bsn)
+  p_in_sosi : PROCESS(st_sosi, bsn)
   BEGIN
-    in_sosi      <= st_sosi_dly;       -- data
+    in_sosi      <= st_sosi;           -- sync at sop, data
     in_sosi.bsn  <= TO_DP_BSN(bsn);    -- bsn at sop
-    in_sosi.sync <= st_sosi.sync;      -- sync before sop
   END PROCESS;
   
   u_dut : ENTITY work.aduh_mean_sum
   GENERIC MAP (
     g_symbol_w             => c_symbol_w,
-    g_nof_symbols_per_data => c_nof_symbols_per_data,  -- big endian in_data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
+    g_nof_symbols_per_data => g_nof_symbols_per_data,  -- big endian in_data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
     g_nof_accumulations    => c_nof_accumulations,     -- integration time in symbols
     g_sum_truncate         => c_sum_truncate,          -- when TRUE truncate (keep MS part) else resize (keep sign and LS part)
     g_sum_w                => c_sum_w                  -- typcially MM word width = 32
@@ -154,8 +156,30 @@ BEGIN
     
     -- Accumulation outputs
     sum         => sum,
-    sum_sync    => sum_sync,
-    sum_sop     => sum_sop
+    sum_sync    => sum_sync
   );
+  
+  -- Only verify sum for a few sum_sync
+  p_verify_sum : PROCESS
+    VARIABLE vI : NATURAL := 0;
+  BEGIN
+    WHILE vI < c_exp_sum_arr'LENGTH LOOP
+      WAIT UNTIL rising_edge(clk);
+      IF sum_sync='1' THEN
+        ASSERT sum = TO_SVEC(c_exp_sum_arr(vI), c_sum_w) REPORT "Unexpected voltage sum." SEVERITY ERROR;
+        vI := vI + 1;
+      END IF;
+    END LOOP;
+    verify_done <= '1';
+    WAIT;
+  END PROCESS;
+  
+  -- Verify that the tb has run with active data
+  p_verify_done : PROCESS
+  BEGIN
+    proc_common_wait_until_high(clk, verify_done);
+    ASSERT verify_done='1' REPORT "No sum output" SEVERITY ERROR;
+    WAIT;
+  END PROCESS;
       
 END tb;

libraries/io/aduh/tb/vhdl/tb_aduh_power_sum.vhd

@@ -35,13 +35,14 @@ USE dp_lib.tb_dp_pkg.ALL;
 -- > run 1 us
 -- observe in_sosi, pwr_sum and pwr_sum_sync in wave window
 -- expected pwr_sum after pwr_sync are: 0, 1240, 9176, ...
--- . sum([ 0:15].^2) =  1240
--- . sum([16:31].^2) =  9176
--- . sum([32:47].^2) = 25304
+-- . pwr_sum([ 0:15].^2) =  1240
+-- . pwr_sum([16:31].^2) =  9176
+-- . pwr_sum([32:47].^2) = 25304
 
 ENTITY tb_aduh_power_sum IS
   GENERIC (
-    g_random_control : BOOLEAN := TRUE  -- use TRUE for random stream flow control, use FALSE for initial debugging
+    g_nof_symbols_per_data  : NATURAL := 4;    -- choose 1 or 4, nof symbols (= ADC samples) per data word
+    g_random_control        : BOOLEAN := TRUE  -- use TRUE for random stream flow control, use FALSE for initial debugging
   );
 END tb_aduh_power_sum;
 
@@ -52,13 +53,12 @@ ARCHITECTURE tb OF tb_aduh_power_sum IS
   
   CONSTANT c_rl                    : NATURAL := 1;
   CONSTANT c_symbol_w              : NATURAL := 8;
-  CONSTANT c_nof_symbols_per_data  : NATURAL := 4;
   CONSTANT c_nof_symbols_per_block : NATURAL := 8;         -- nof symbols (= ADC samples) per block
   
   CONSTANT c_pwr_sum_truncate      : BOOLEAN := TRUE;
   CONSTANT c_pwr_sum_w             : NATURAL := c_word_w;   -- = 32
   
-  CONSTANT c_data_w                : NATURAL := c_nof_symbols_per_data*c_symbol_w;
+  CONSTANT c_data_w                : NATURAL := g_nof_symbols_per_data*c_symbol_w;
   
   CONSTANT c_nof_sync              : NATURAL := 10;
   CONSTANT c_nof_block_per_sync    : NATURAL := 2;
@@ -66,6 +66,9 @@ ARCHITECTURE tb OF tb_aduh_power_sum IS
   
   CONSTANT c_nof_accumulations     : NATURAL := c_nof_symbols_per_sync;  -- integration time in symbols
   
+  CONSTANT c_exp_sum_arr           : t_natural_arr(0 TO 3) := (0, 1240, 9176, 25304);
+  
+  SIGNAL tb_almost_end   : STD_LOGIC := '0';
   SIGNAL tb_end          : STD_LOGIC := '0';
   SIGNAL rst             : STD_LOGIC;
   SIGNAL clk             : STD_LOGIC := '1';
@@ -74,16 +77,14 @@ ARCHITECTURE tb OF tb_aduh_power_sum IS
   
   SIGNAL st_en           : STD_LOGIC := '1';
   SIGNAL st_sosi         : t_dp_sosi := c_dp_sosi_rst;
-  SIGNAL st_sosi_dly     : t_dp_sosi := c_dp_sosi_rst;
   SIGNAL st_siso         : t_dp_siso := c_dp_siso_rdy;
-  
-  SIGNAL bsn             : NATURAL;
-  
+  SIGNAL bsn             : NATURAL;  
   SIGNAL in_sosi         : t_dp_sosi := c_dp_sosi_rst;
   
   SIGNAL pwr_sum         : STD_LOGIC_VECTOR(c_pwr_sum_w-1 DOWNTO 0);
   SIGNAL pwr_sum_sync    : STD_LOGIC;
-  SIGNAL pwr_sum_sop     : STD_LOGIC;
+  
+  SIGNAL verify_done     : STD_LOGIC := '0';
   
 BEGIN
 
@@ -118,27 +119,26 @@ BEGIN
     
     st_sosi <= c_dp_sosi_rst;
     proc_common_wait_some_cycles(clk, 15);
+    proc_common_gen_pulse(clk, tb_almost_end);
+    proc_common_wait_some_cycles(clk, 10);
     tb_end <= '1';
     WAIT;
   END PROCESS;
   
-  st_sosi_dly <= st_sosi WHEN rising_edge(clk);
-
   -- Time stimuli  
-  bsn <= bsn + 1 WHEN rising_edge(clk) AND st_sosi.sync='1';
+  bsn <= bsn + 1 WHEN rising_edge(clk) AND st_sosi.eop='1';
   
   -- Add BSN to the ST data
-  p_in_sosi : PROCESS(st_sosi, st_sosi_dly, bsn)
+  p_in_sosi : PROCESS(st_sosi, bsn)
   BEGIN
-    in_sosi      <= st_sosi_dly;       -- data
-    in_sosi.bsn  <= TO_DP_BSN(bsn);    -- bsn at sop
-    in_sosi.sync <= st_sosi.sync;      -- sync before sop
+    in_sosi      <= st_sosi;         -- sync at sop, data
+    in_sosi.bsn  <= TO_DP_BSN(bsn);  -- bsn at sop
   END PROCESS;
   
   u_dut : ENTITY work.aduh_power_sum
   GENERIC MAP (
     g_symbol_w             => c_symbol_w,
-    g_nof_symbols_per_data => c_nof_symbols_per_data,  -- big endian in_data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
+    g_nof_symbols_per_data => g_nof_symbols_per_data,  -- big endian in_data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
     g_nof_accumulations    => c_nof_accumulations,     -- integration time in symbols
     g_pwr_sum_truncate     => c_pwr_sum_truncate,      -- when TRUE truncate (keep MS part) else resize (keep sign and LS part)
     g_pwr_sum_w            => c_pwr_sum_w              -- typcially MM word width = 32
@@ -154,8 +154,30 @@ BEGIN
     
     -- Accumulation outputs
     pwr_sum      => pwr_sum,
-    pwr_sum_sync => pwr_sum_sync,
-    pwr_sum_sop  => pwr_sum_sop
+    pwr_sum_sync => pwr_sum_sync
   );
       
+  -- Only verify pwr_sum for a few pwr_sum_sync
+  p_verify_sum : PROCESS
+    VARIABLE vI : NATURAL := 0;
+  BEGIN
+    WHILE vI < c_exp_sum_arr'LENGTH LOOP
+      WAIT UNTIL rising_edge(clk);
+      IF pwr_sum_sync='1' THEN
+        ASSERT pwr_sum = TO_SVEC(c_exp_sum_arr(vI), c_pwr_sum_w) REPORT "Unexpected power sum." SEVERITY ERROR;
+        vI := vI + 1;
+      END IF;
+    END LOOP;
+    verify_done <= '1';
+    WAIT;
+  END PROCESS;
+  
+  -- Verify that the tb has run with active data
+  p_verify_done : PROCESS
+  BEGIN
+    proc_common_wait_until_high(clk, verify_done);
+    ASSERT verify_done='1' REPORT "No power sum output" SEVERITY ERROR;
+    WAIT;
+  END PROCESS;
+  
 END tb;