Removed sum_sop, only need to use sum_sync.

libraries/io/aduh/src/vhdl/aduh_monitor.vhd

@@ -69,7 +69,7 @@ ENTITY aduh_monitor IS
     -- Monitor outputs
     stat_mean_sum  : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);  -- use fixed 64 bit sum width
     stat_pwr_sum   : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);  -- use fixed 64 bit sum width
-    stat_sop       : OUT STD_LOGIC                       -- at the sop there are new mean_sum and pwr_sum statistics available
+    stat_sync      : OUT STD_LOGIC                       -- at the stat_sync there are new mean_sum and pwr_sum statistics available
   );
 END aduh_monitor;
 
@@ -101,8 +101,7 @@ BEGIN
     
     -- Accumulation outputs
     sum         => stat_mean_sum,
-    sum_sync    => OPEN,
-    sum_sop     => OPEN
+    sum_sync    => OPEN
   );
 
   u_power : ENTITY work.aduh_power_sum
@@ -124,8 +123,7 @@ BEGIN
     
     -- Accumulation outputs
     pwr_sum      => stat_pwr_sum,
-    pwr_sum_sync => OPEN,
-    pwr_sum_sop  => stat_sop
+    pwr_sum_sync => stat_sync
   );
 
   u_data_mon: ENTITY diag_lib.diag_data_buffer

libraries/io/aduh/src/vhdl/aduh_monitor_reg.vhd

@@ -34,7 +34,7 @@
 --  |-----------------------------------------------------------------------|
 --
 -- . The new mean_sum and the power_sum are passed on the MM side when
---   st_mon_sop pulses.
+--   st_mon_sync pulses.
 
 LIBRARY IEEE, common_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
@@ -59,7 +59,7 @@ ENTITY aduh_monitor_reg IS
     -- MM registers in st_clk domain
     st_mon_mean_sum   : IN  STD_LOGIC_VECTOR(c_longword_w-1 DOWNTO 0);  -- use fixed 64 bit sum width
     st_mon_power_sum  : IN  STD_LOGIC_VECTOR(c_longword_w-1 DOWNTO 0);  -- use fixed 64 bit sum width
-    st_mon_sop        : IN  STD_LOGIC    -- at the mon_sop there are new mean_sum and pwr_sum statistics available
+    st_mon_sync       : IN  STD_LOGIC    -- at the mon_sync there are new mean_sum and pwr_sum statistics available
   );
 END aduh_monitor_reg;
 
@@ -151,7 +151,7 @@ BEGIN
         mm_mon_mean_sum  <= (OTHERS=>'0');
         mm_mon_power_sum <= (OTHERS=>'0');
       ELSIF rising_edge(mm_clk) THEN
-        IF st_mon_sop='1' THEN
+        IF st_mon_sync='1' THEN
           mm_mon_mean_sum  <= st_mon_mean_sum;
           mm_mon_power_sum <= st_mon_power_sum;
         END IF;
@@ -167,7 +167,7 @@ BEGIN
     PORT MAP (
       in_rst      => st_rst,
       in_clk      => st_clk,
-      in_new      => st_mon_sop,       -- when '1' then new in_dat is available after g_in_new_latency
+      in_new      => st_mon_sync,      -- when '1' then new in_dat is available after g_in_new_latency
       in_dat      => st_mon_mean_sum,
       in_done     => OPEN,             -- pulses when no more pending in_new
       out_rst     => mm_rst,
@@ -183,7 +183,7 @@ BEGIN
     PORT MAP (
       in_rst      => st_rst,
       in_clk      => st_clk,
-      in_new      => st_mon_sop,       -- when '1' then new in_dat is available after g_in_new_latency
+      in_new      => st_mon_sync,      -- when '1' then new in_dat is available after g_in_new_latency
       in_dat      => st_mon_power_sum,
       in_done     => OPEN,             -- pulses when no more pending in_new
       out_rst     => mm_rst,

libraries/io/aduh/src/vhdl/mms_aduh_monitor.vhd

@@ -66,7 +66,7 @@ ARCHITECTURE str OF mms_aduh_monitor IS
   -- Monitor outputs
   SIGNAL mon_mean_sum  : STD_LOGIC_VECTOR(c_longword_w-1 DOWNTO 0);  -- use fixed 64 bit sum width
   SIGNAL mon_power_sum : STD_LOGIC_VECTOR(c_longword_w-1 DOWNTO 0);  -- use fixed 64 bit sum width
-  SIGNAL mon_sop       : STD_LOGIC;  -- at the sop there are new mean_sum and pwr_sum statistics available
+  SIGNAL mon_sync      : STD_LOGIC;  -- at the mon_sync there are new mean_sum and pwr_sum statistics available
   
 BEGIN
 
@@ -88,7 +88,7 @@ BEGIN
     -- MM registers in st_clk domain
     st_mon_mean_sum   => mon_mean_sum,
     st_mon_power_sum  => mon_power_sum,
-    st_mon_sop        => mon_sop
+    st_mon_sync       => mon_sync
   );
   
   u_monitor : ENTITY work.aduh_monitor
@@ -115,7 +115,7 @@ BEGIN
     -- Monitor outputs
     stat_mean_sum  => mon_mean_sum,
     stat_pwr_sum   => mon_power_sum,
-    stat_sop       => mon_sop
+    stat_sync      => mon_sync
   );
   
 END str;