ready for revieuw

applications/lofar2/libraries/ddrctrl/hdllib.cfg

@@ -5,10 +5,10 @@ hdl_lib_uses_sim =
 hdl_lib_technology = 
 
 synth_files = 
-    src/vhdl/address_counter.vhd 
+    src/vhdl/ddrctrl_address_counter.vhd 
 
 test_bench_files =
-    tb/vhdl/tb_address_counter.vhd
+    tb/vhdl/tb_ddrctrl_address_counter.vhd
 
 regression_test_vhdl = 
 

applications/lofar2/libraries/ddrctrl/src/vhdl/address_counter.vhd → applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_address_counter.vhd

@@ -29,8 +29,6 @@
 --  https://support.astron.nl/confluence/display/SBe/VHDL+design+patterns+for+RTL+coding
 --  The maximum value of the address is determend by g_tech_ddr.
 
-
-
 LIBRARY IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib;
 USE IEEE.std_logic_1164.ALL;
 USE IEEE.numeric_std.ALL;
@@ -40,7 +38,8 @@ USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
 
-ENTITY address_counter IS
+
+ENTITY ddrctrl_address_counter IS
   GENERIC (
     g_tech_ddr		    : t_c_tech_ddr;
     g_sim_model       : BOOLEAN := TRUE
@@ -51,12 +50,14 @@ ENTITY address_counter IS
     in_sosi           : IN  t_dp_sosi;
     out_mosi          : OUT t_mem_ctlr_mosi
   );
-END address_counter;
+END ddrctrl_address_counter;
+
 
-ARCHITECTURE rtl OF address_counter IS
+ARCHITECTURE rtl OF ddrctrl_address_counter IS
 
   CONSTANT c_data_w	: NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); --576
   CONSTANT c_adr_w	: NATURAL := sel_a_b(g_sim_model, 4, func_tech_ddr_ctlr_address_w( g_tech_ddr )); --27;
+  CONSTANT c_max_adr: NATURAL := 2**(c_adr_w) - 1;
 
   SIGNAL   s_adr    : NATURAL range 0 to 2**(c_adr_w)-1 := 0;
 
@@ -72,7 +73,7 @@ BEGIN
       IF rst = '1' THEN
         s_adr <= 0;
       ELSIF in_sosi.valid = '1' THEN
-        IF (s_adr = 2**(c_adr_w) - 1) THEN
+        IF (s_adr = c_max_adr) THEN
           s_adr <= 0;
         ELSE
           s_adr <= s_adr + 1;

applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_address_counter.vhd → applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_address_counter.vhd

@@ -30,22 +30,23 @@ USE dp_lib.dp_stream_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 USE common_lib.common_pkg.ALL;
 
-ENTITY tb_address_counter IS
+ENTITY tb_ddrctrl_address_counter IS
   GENERIC (
     
     g_tech_ddr                : t_c_tech_ddr    := c_tech_ddr4_8g_1600m;
     g_sim_model               : BOOLEAN         := TRUE
 
   );
-END tb_address_counter;
+END tb_ddrctrl_address_counter;
 
-ARCHITECTURE tb OF tb_address_counter IS
+ARCHITECTURE tb OF tb_ddrctrl_address_counter IS
 
   CONSTANT  c_clk_freq        : NATURAL         := 200;     -- MHz
   CONSTANT  c_clk_period      : TIME            := (10**6 / c_clk_freq) * 1 ps;
 
   CONSTANT  c_data_w          : NATURAL         := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- 576
   CONSTANT  c_adr_w           : NATURAL         := 4;
+  CONSTANT  c_max_adr         : NATURAL         := 2**c_adr_w;
 
   SIGNAL    tb_end            : STD_LOGIC       := '0';
 
@@ -80,12 +81,13 @@ BEGIN
     WAIT UNTIL rising_edge(clk);  -- align to rising edge
     WAIT FOR c_clk_period*10;
 
+    ASSERT in_sosi.data(c_data_w - 1 DOWNTO 0) = out_mosi.wrdata(c_data_w - 1 DOWNTO 0) REPORT "Wrong wrdata 1"  SEVERITY ERROR;
+    ASSERT in_sosi.valid                       = out_mosi.wr                            REPORT "Wrong wr 1"      SEVERITY ERROR;
+
     FOR I IN 0 TO 6 LOOP
       in_data_enable    <= '1';
       in_data           <= NOT in_data;
-      ASSERT in_data(c_data_w - 1 DOWNTO 0) = out_mosi.wrdata(c_data_w - 1 DOWNTO 0) REPORT "Wrong wrdata 1"  SEVERITY ERROR;
-      ASSERT in_data_enable                 = out_mosi.wr                            REPORT "Wrong wr 1"      SEVERITY ERROR;
-      ASSERT I                              = TO_UINT(out_mosi.address)              REPORT "Wrong address 1" SEVERITY ERROR;
+      ASSERT I                                 = TO_UINT(out_mosi.address)              REPORT "Wrong address 1" SEVERITY ERROR;
       WAIT FOR c_clk_period*1;
       in_data_enable    <= '0';
       WAIT FOR c_clk_period*2;
@@ -98,9 +100,7 @@ BEGIN
     WAIT FOR c_clk_period*1;
 
     FOR I IN 0 TO 20 LOOP
-      ASSERT in_data(c_data_w - 1 DOWNTO 0) = out_mosi.wrdata(c_data_w - 1 DOWNTO 0) REPORT "Wrong wrdata 2"  SEVERITY ERROR;
-      ASSERT in_data_enable                 = out_mosi.wr                            REPORT "Wrong wr 2"      SEVERITY ERROR;
-      ASSERT I = TO_UINT(out_mosi.address) OR I - 16 = TO_UINT(out_mosi.address)     REPORT "Wrong address, I = " & NATURAL'image(I)  SEVERITY ERROR;
+      ASSERT I = TO_UINT(out_mosi.address)  OR I - c_max_adr = TO_UINT(out_mosi.address)    REPORT "Wrong address, I = " & NATURAL'image(I)  SEVERITY ERROR;
       in_data_enable    <= '1';
       in_data           <= NOT in_data;
       WAIT FOR c_clk_period*1;
@@ -115,7 +115,7 @@ BEGIN
     WAIT;
   END PROCESS;
 
-  u_address_counter : ENTITY work.address_counter
+  u_address_counter : ENTITY work.ddrctrl_address_counter
   GENERIC MAP (
     g_tech_ddr        => g_tech_ddr,
     g_sim_model       => g_sim_model