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RTSD
HDL
Commits
b1743314
Commit
b1743314
authored
2 years ago
by
Eric Kooistra
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Use proc_common_wait_until_clk_and_high() for correct rx_beamlet_* read out.
parent
3b0118bc
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1 merge request
!311
Correct beamlet output indexing in tr_10GbE_src_out.data. Verify exact beamlet...
Pipeline
#44827
passed
2 years ago
Stage: simulation
Stage: synthesis
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applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/tb_disturb2_unb2b_sdp_station_full_wg.vhd
+5
-8
5 additions, 8 deletions
...station_full_wg/tb_disturb2_unb2b_sdp_station_full_wg.vhd
with
5 additions
and
8 deletions
applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/tb_disturb2_unb2b_sdp_station_full_wg.vhd
+
5
−
8
View file @
b1743314
...
@@ -419,9 +419,9 @@ BEGIN
...
@@ -419,9 +419,9 @@ BEGIN
-- Read 3 packets to make sure we get 1 from each beamset. It can happen that two packets
-- Read 3 packets to make sure we get 1 from each beamset. It can happen that two packets
-- (but not three) from the same beamset are received back to back.
-- (but not three) from the same beamset are received back to back.
FOR
packet
IN
0
TO
10
LOOP
FOR
packet
IN
0
TO
2
LOOP
-- Get beamlet_index from packet header
-- Get beamlet_index from packet header
proc_common_wait_until_high
(
ext_clk
,
tr_10GbE_src_out
.
sop
);
proc_common_wait_until_
clk_and_
high
(
ext_clk
,
tr_10GbE_src_out
.
sop
);
FOR
I
IN
0
TO
8
LOOP
-- Packet header is 9.25 words wide, which can be discarded
FOR
I
IN
0
TO
8
LOOP
-- Packet header is 9.25 words wide, which can be discarded
IF
I
=
7
THEN
IF
I
=
7
THEN
rx_beamlet_scale
<=
tr_10GbE_src_out
.
data
(
55
DOWNTO
40
);
rx_beamlet_scale
<=
tr_10GbE_src_out
.
data
(
55
DOWNTO
40
);
...
@@ -434,8 +434,7 @@ BEGIN
...
@@ -434,8 +434,7 @@ BEGIN
rx_block_period
<=
tr_10GbE_src_out
.
data
(
63
DOWNTO
48
);
rx_block_period
<=
tr_10GbE_src_out
.
data
(
63
DOWNTO
48
);
rx_bsn
(
63
DOWNTO
16
)
<=
tr_10GbE_src_out
.
data
(
47
DOWNTO
0
);
rx_bsn
(
63
DOWNTO
16
)
<=
tr_10GbE_src_out
.
data
(
47
DOWNTO
0
);
END
IF
;
END
IF
;
proc_common_wait_until_high
(
ext_clk
,
tr_10GbE_src_out
.
valid
);
proc_common_wait_until_clk_and_high
(
ext_clk
,
tr_10GbE_src_out
.
valid
);
proc_common_wait_some_cycles
(
ext_clk
,
1
);
END
LOOP
;
END
LOOP
;
rx_bsn
(
15
DOWNTO
0
)
<=
tr_10GbE_src_out
.
data
(
63
DOWNTO
48
);
rx_bsn
(
15
DOWNTO
0
)
<=
tr_10GbE_src_out
.
data
(
63
DOWNTO
48
);
...
@@ -456,8 +455,7 @@ BEGIN
...
@@ -456,8 +455,7 @@ BEGIN
beamlet_arr2_re
(
v_beamlet_index_offset
+
1
)
<=
tr_10GbE_src_out
.
data
(
23
DOWNTO
16
);
beamlet_arr2_re
(
v_beamlet_index_offset
+
1
)
<=
tr_10GbE_src_out
.
data
(
23
DOWNTO
16
);
beamlet_arr2_im
(
v_beamlet_index_offset
+
2
)
<=
tr_10GbE_src_out
.
data
(
15
DOWNTO
8
);
beamlet_arr2_im
(
v_beamlet_index_offset
+
2
)
<=
tr_10GbE_src_out
.
data
(
15
DOWNTO
8
);
beamlet_arr2_re
(
v_beamlet_index_offset
+
2
)
<=
tr_10GbE_src_out
.
data
(
7
DOWNTO
0
);
beamlet_arr2_re
(
v_beamlet_index_offset
+
2
)
<=
tr_10GbE_src_out
.
data
(
7
DOWNTO
0
);
proc_common_wait_until_high
(
ext_clk
,
tr_10GbE_src_out
.
valid
);
proc_common_wait_until_clk_and_high
(
ext_clk
,
tr_10GbE_src_out
.
valid
);
proc_common_wait_some_cycles
(
ext_clk
,
1
);
rx_beamlet_cnt
<=
rx_beamlet_cnt
+
1
;
rx_beamlet_cnt
<=
rx_beamlet_cnt
+
1
;
rx_beamlet_sop
<=
'0'
;
rx_beamlet_sop
<=
'0'
;
-- . get beamlets during block, there are 4 complex beamlets per 64b word
-- . get beamlets during block, there are 4 complex beamlets per 64b word
...
@@ -470,8 +468,7 @@ BEGIN
...
@@ -470,8 +468,7 @@ BEGIN
beamlet_arr2_re
(
v_beamlet_index_offset
+
I
*
4
+
1
)
<=
tr_10GbE_src_out
.
data
(
23
DOWNTO
16
);
beamlet_arr2_re
(
v_beamlet_index_offset
+
I
*
4
+
1
)
<=
tr_10GbE_src_out
.
data
(
23
DOWNTO
16
);
beamlet_arr2_im
(
v_beamlet_index_offset
+
I
*
4
+
2
)
<=
tr_10GbE_src_out
.
data
(
15
DOWNTO
8
);
beamlet_arr2_im
(
v_beamlet_index_offset
+
I
*
4
+
2
)
<=
tr_10GbE_src_out
.
data
(
15
DOWNTO
8
);
beamlet_arr2_re
(
v_beamlet_index_offset
+
I
*
4
+
2
)
<=
tr_10GbE_src_out
.
data
(
7
DOWNTO
0
);
beamlet_arr2_re
(
v_beamlet_index_offset
+
I
*
4
+
2
)
<=
tr_10GbE_src_out
.
data
(
7
DOWNTO
0
);
proc_common_wait_until_high
(
ext_clk
,
tr_10GbE_src_out
.
valid
);
proc_common_wait_until_clk_and_high
(
ext_clk
,
tr_10GbE_src_out
.
valid
);
proc_common_wait_some_cycles
(
ext_clk
,
1
);
rx_beamlet_cnt
<=
rx_beamlet_cnt
+
1
;
rx_beamlet_cnt
<=
rx_beamlet_cnt
+
1
;
END
LOOP
;
END
LOOP
;
-- . get last beamlet of block
-- . get last beamlet of block
...
...
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