Add proc_common_wait_until_clk_and_high().

libraries/base/common/tb/vhdl/tb_common_pkg.vhd

@@ -81,6 +81,9 @@ PACKAGE tb_common_pkg IS
   PROCEDURE proc_common_wait_until_high(SIGNAL clk    : IN  STD_LOGIC;
                                         SIGNAL level  : IN  STD_LOGIC);
                                                 
+  PROCEDURE proc_common_wait_until_clk_and_high(SIGNAL clk    : IN  STD_LOGIC;
+                                                SIGNAL level  : IN  STD_LOGIC);
+
   PROCEDURE proc_common_wait_until_low(CONSTANT c_timeout : IN  NATURAL;
                                        SIGNAL   clk       : IN  STD_LOGIC;
                                        SIGNAL   level     : IN  STD_LOGIC);
@@ -88,6 +91,9 @@ PACKAGE tb_common_pkg IS
   PROCEDURE proc_common_wait_until_low(SIGNAL clk    : IN  STD_LOGIC;
                                        SIGNAL level  : IN  STD_LOGIC);
                                          
+  PROCEDURE proc_common_wait_until_clk_and_low(SIGNAL clk    : IN  STD_LOGIC;
+                                               SIGNAL level  : IN  STD_LOGIC);
+
   PROCEDURE proc_common_wait_until_hi_lo(CONSTANT c_timeout : IN  NATURAL;
                                          SIGNAL   clk       : IN  STD_LOGIC;
                                          SIGNAL   level     : IN  STD_LOGIC);
@@ -427,6 +433,12 @@ PACKAGE BODY tb_common_pkg IS
       WAIT UNTIL rising_edge(clk) AND level='1';
     END IF;
   END proc_common_wait_until_high;
+
+  PROCEDURE proc_common_wait_until_clk_and_high(SIGNAL clk    : IN  STD_LOGIC;
+                                                SIGNAL level  : IN  STD_LOGIC) IS
+  BEGIN
+    WAIT UNTIL rising_edge(clk) AND level='1';
+  END proc_common_wait_until_clk_and_high;
   
   PROCEDURE proc_common_wait_until_high(CONSTANT c_timeout : IN  NATURAL;
                                         SIGNAL   clk       : IN  STD_LOGIC;
@@ -452,6 +464,12 @@ PACKAGE BODY tb_common_pkg IS
     END IF;
   END proc_common_wait_until_low;
   
+  PROCEDURE proc_common_wait_until_clk_and_low(SIGNAL clk    : IN  STD_LOGIC;
+                                              SIGNAL level  : IN  STD_LOGIC) IS
+  BEGIN
+    WAIT UNTIL rising_edge(clk) AND level='0';
+  END proc_common_wait_until_clk_and_low;
+
   PROCEDURE proc_common_wait_until_low(CONSTANT c_timeout : IN  NATURAL;
                                        SIGNAL   clk       : IN  STD_LOGIC;
                                        SIGNAL   level     : IN  STD_LOGIC) IS