solved using rising_edge(not clock)

applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_address_counter.vhd

@@ -45,6 +45,7 @@ ENTITY ddrctrl_address_counter IS
     g_sim_model       : BOOLEAN                           := TRUE                                                                 -- determens if this is a simulation
   );
   PORT (
+    clk               : IN  STD_LOGIC;
     rst               : IN  STD_LOGIC;
     in_sosi           : IN  t_dp_sosi;                                                                                            -- input data
     out_mosi          : OUT t_mem_ctlr_mosi               := c_mem_ctlr_mosi_rst                                                  -- output data
@@ -57,30 +58,30 @@ ARCHITECTURE rtl OF ddrctrl_address_counter IS
   -- constants for readability
   CONSTANT c_data_w   : NATURAL                           := func_tech_ddr_ctlr_data_w( g_tech_ddr );                             -- the with of the input data and output data, 576
   CONSTANT c_adr_w    : NATURAL                           := sel_a_b(g_sim_model, 4, func_tech_ddr_ctlr_address_w( g_tech_ddr )); -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
-  CONSTANT c_max_adr  : NATURAL                           := 2**(c_adr_w) - 1;                                                    -- the maximal address that is possible within the vector length of the address
+  CONSTANT c_max_adr  : NATURAL                           := 2**(c_adr_w)-1;                                                      -- the maximal address that is possible within the vector length of the address
 
   -- signal for storing address
   SIGNAL   s_adr      : NATURAL range 0 to 2**(c_adr_w)-1 := 0;                                                                   -- a signal that contains the address
 
 BEGIN
 
-  -- The data is directly put through.
-  out_mosi.wrdata(c_data_w - 1 DOWNTO 0) <= in_sosi.data(c_data_w - 1 DOWNTO 0);
-  out_mosi.wr                            <= in_sosi.valid;
   out_mosi.address(c_adr_w -1 DOWNTO 0)  <= TO_UVEC(s_adr, c_adr_w);
 
   -- Increments the address each time in_sosi.valid = '1', if address = c_max_adr the address is reset to 0.
-  p_adr : PROCESS(rst, in_sosi.valid)
+  p_adr : PROCESS(rst, clk)
   BEGIN
-    IF rst = '1' THEN
-      s_adr <= 0;
-    ELSIF rising_edge(in_sosi.valid) THEN
-      IF s_adr = c_max_adr THEN
+    IF rising_edge(clk) THEN
+      out_mosi.wrdata(c_data_w - 1 DOWNTO 0) <= in_sosi.data(c_data_w - 1 DOWNTO 0);
+      out_mosi.wr                            <= in_sosi.valid;
+      IF rst = '1' THEN
         s_adr <= 0;
-      ELSE
-        s_adr <= s_adr + 1;
+      ELSIF in_sosi.valid = '1' THEN
+        IF s_adr = c_max_adr THEN
+          s_adr <= 0;
+        ELSE
+          s_adr <= s_adr + 1;
+        END IF;
       END IF;
     END IF;
   END PROCESS;
-
 END rtl;

applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_address_counter.vhd

@@ -62,9 +62,13 @@ ARCHITECTURE tb OF tb_ddrctrl_address_counter IS
 
   -- testbench signals
   SIGNAL    tb_end            : STD_LOGIC       := '0';                                     -- signal to turn the testbench off
-  SIGNAL    in_data           : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);                      -- signal which contains the data that is set as input
-  SIGNAL    in_data_enable    : STD_LOGIC;                                                  -- signal to determen if in_data is ready for reading
+  SIGNAL    in_data           : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0) := (OTHERS => '0');   -- signal which contains the data that is set as input
+  SIGNAL    d_in_data         : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0) := (OTHERS => '0');
+  SIGNAL    in_data_enable    : STD_LOGIC       := '0';                                     -- signal to determen if in_data is ready for reading
+  SIGNAL    d_in_data_enable  : STD_LOGIC       := '0';
   SIGNAL    lag_due_reset     : NATURAL         := 0;                                       -- signal to hold the address lag after a rest
+  SIGNAL    d_lag_due_reset   : NATURAL         := 0;
+  SIGNAL    d_rst             : STD_LOGIC       := '0';
 
 BEGIN
 
@@ -97,16 +101,29 @@ BEGIN
     -- stopping the test
     WAIT FOR c_clk_period*4;
     tb_end            <= '1';
-    ASSERT FALSE                                                                      REPORT "Test: OK"                                                            SEVERITY FAILURE;
+    ASSERT FALSE                                                                       REPORT "Test: OK"                                                            SEVERITY FAILURE;
   END PROCESS;
 
+  -- generating compare data for out_mosi
+  p_out_mosi : PROCESS
+  BEGIN
+    WAIT UNTIL rising_edge(clk);
+    if rising_edge(clk) THEN
+      d_in_data_enable <= in_data_enable;
+      d_in_data        <= in_data;
+      d_lag_due_reset  <= lag_due_reset;
+      d_rst            <= rst;
+    END IF;
+  END PROCESS;
+      
+
   -- verifying if the data is correct and if valid is correct
   p_verify_data_valid : PROCESS
   BEGIN
     WAIT UNTIL rising_edge(clk);
     IF rising_edge(clk) THEN
-      ASSERT in_sosi.data(c_data_w-1 DOWNTO 0) = out_mosi.wrdata(c_data_w-1 DOWNTO 0) REPORT "in_sosi.data does not match out_mosi.wrdata"                         SEVERITY ERROR;
-      ASSERT in_sosi.valid                     = out_mosi.wr                          REPORT "in_sosi.valid does not match out_mosi.wr"                            SEVERITY ERROR;
+      ASSERT d_in_data(c_data_w-1 DOWNTO 0) = out_mosi.wrdata(c_data_w-1 DOWNTO 0)     REPORT "in_sosi.data does not match out_mosi.wrdata"                         SEVERITY ERROR;
+      ASSERT d_in_data_enable               = out_mosi.wr                              REPORT "in_sosi.valid does not match out_mosi.wr"                            SEVERITY ERROR;
     END IF;
   END PROCESS;
 
@@ -114,12 +131,13 @@ BEGIN
   p_test_reset : PROCESS
   BEGIN
     rst <= '0';
-    WAIT FOR c_clk_period*(c_adr_size+3);
+    --WAIT FOR c_clk_period*1;
     IF lag_due_reset + TO_UINT(out_mosi.address) >= c_adr_size THEN
       lag_due_reset <= lag_due_reset+TO_UINT(out_mosi.address)-c_adr_size;
     ELSE
       lag_due_reset <= lag_due_reset+TO_UINT(out_mosi.address);
     END IF;
+    WAIT FOR c_clk_period*(c_adr_size+3);
     rst <= '1';
     WAIT FOR c_clk_period*1;
   END PROCESS;
@@ -129,13 +147,13 @@ BEGIN
   BEGIN
     FOR I IN 0 TO c_adr_size-1 LOOP
       WAIT UNTIL out_mosi.wr = '1';
-      IF rst = '1' THEN
+      IF d_rst = '1' THEN
         WAIT UNTIL out_mosi.wr = '1';
       END IF;
-      IF I >= lag_due_reset THEN
-        ASSERT I-lag_due_reset   = TO_UINT(out_mosi.address)                           REPORT "Wrong address, 1, I = " & NATURAL'image(I-lag_due_reset) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address))                SEVERITY ERROR;
+      IF I >= d_lag_due_reset THEN
+        ASSERT I-d_lag_due_reset   = TO_UINT(out_mosi.address)                         REPORT "Wrong address, 1, I = " & NATURAL'image(I-d_lag_due_reset) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address))              SEVERITY ERROR;
       ELSE
-        ASSERT (I-lag_due_reset)+c_adr_size = TO_UINT(out_mosi.address)                REPORT "Wrong address, 2, I = " & NATURAL'image((I-lag_due_reset)+c_adr_size) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address))   SEVERITY ERROR;
+        ASSERT (I-d_lag_due_reset)+c_adr_size = TO_UINT(out_mosi.address)                REPORT "Wrong address, 2, I = " & NATURAL'image((I-d_lag_due_reset)+c_adr_size) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address))   SEVERITY ERROR;
       END IF;
     END LOOP;
   END PROCESS;
@@ -148,6 +166,7 @@ BEGIN
     g_sim_model       => g_sim_model
   )
   PORT MAP (
+    clk               => clk,
     rst               => rst,
     in_sosi           => in_sosi,