getting modelsim errors out

libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_191/hdllib.cfg

 hdl_lib_name = ip_arria10_e2sg_alt_mem_if_jtag_master_191
 hdl_library_clause_name = alt_mem_if_jtag_master_191
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_jtag_dc_streaming_191 ip_arria10_e2sg_timing_adapter_191 ip_arria10_e2sg_altera_avalon_sc_fifo_191 ip_arria10_e2sg_altera_avalon_st_bytes_to_packets_1910 ip_arria10_e2sg_altera_avalon_st_packets_to_bytes_1910 ip_arria10_e2sg_altera_avalon_packets_to_master_1910 ip_arria10_e2sg_channel_adapter_191 ip_arria10_e2sg_altera_reset_controller_191
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_jtag_dc_streaming_191 ip_arria10_e2sg_timing_adapter_191 ip_arria10_e2sg_altera_avalon_sc_fifo_191 ip_arria10_e2sg_altera_avalon_st_bytes_to_packets_1910 ip_arria10_e2sg_altera_avalon_packets_to_master_1910 ip_arria10_e2sg_channel_adapter_191 ip_arria10_e2sg_altera_reset_controller_191
+#ip_arria10_e2sg_altera_avalon_st_packets_to_bytes_1910 
 
 hdl_lib_technology = ip_arria10_e2sg
 

libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_191/hdllib.cfg

 hdl_lib_name = ip_arria10_e2sg_altera_emif_191
 hdl_library_clause_name = altera_emif_191
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_merlin_master_translator_191 ip_arria10_e2sg_altera_merlin_slave_translator_191
+hdl_lib_uses_sim = 
+#ip_arria10_e2sg_altera_merlin_master_translator_191 ip_arria10_e2sg_altera_merlin_slave_translator_191
 hdl_lib_technology = ip_arria10_e2sg
 
 synth_files =

libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_1940/compile_ip.tcl

@@ -32,7 +32,7 @@ set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
 
 vmap  altera_eth_tse_mac_1940                 ./work/
 
-  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_1940/sim/altera_xcvr_native_a10_functions_h.sv"                                     -work altera_common_sv_packages  
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_191/sim/altera_xcvr_native_a10_functions_h.sv"                                     -work altera_common_sv_packages  
   vlog      "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_eth_tse_mac.v"                                                   -work altera_eth_tse_mac_1940                
   vlog      "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_clk_cntl.v"                                                  -work altera_eth_tse_mac_1940                
   vlog      "$IP_DIR/../altera_eth_tse_mac_1940/sim/mentor/altera_tse_crc328checker.v"                                             -work altera_eth_tse_mac_1940                

libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_1940/compile_ip.tcl

@@ -33,7 +33,7 @@ set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
               
 vmap  altera_eth_tse_pcs_pma_nf_phyip_1940    ./work/
 
-  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_1940/sim/altera_xcvr_native_a10_functions_h.sv"                                                           -work altera_common_sv_packages
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_191/sim/altera_xcvr_native_a10_functions_h.sv"                                                           -work altera_common_sv_packages
 
   vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_eth_tse_pcs_pma_nf_phyip.v"                                               -work altera_eth_tse_pcs_pma_nf_phyip_1940   
   vlog      "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_1940/sim/mentor/altera_tse_align_sync.v"                                                         -work altera_eth_tse_pcs_pma_nf_phyip_1940   

libraries/technology/ip_arria10_e2sg/altera_libraries/altera_iopll_1930/compile_ip.tcl

@@ -41,3 +41,5 @@ set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
 
 set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_core_pll_200MHz/sim"
   vlog  "$IP_DIR/../altera_iopll_1930/sim/ip_arria10_e2sg_jesd204b_rx_core_pll_200MHz_altera_iopll_1930_ibzmqny.vo" -work altera_iopll_1930
+
+

libraries/technology/ip_arria10_e2sg/altera_libraries/altera_iopll_1930/hdllib.cfg

@@ -11,7 +11,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_iopll_194/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_iopll_1930/compile_ip.tcl
 
 
 

libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_1930/hdllib.cfg

 hdl_lib_name = ip_arria10_e2sg_altera_lvds_1930
 hdl_library_clause_name = altera_lvds_1930
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_lvds_core20_1930
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_lvds_core20_191
 hdl_lib_technology = ip_arria10_e2sg
 
 synth_files =

libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_191/compile_ip.tcl

@@ -32,9 +32,9 @@ vmap  altera_lvds_core20_191                ./work/
 
   vlog -sv  "$IP_DIR/../altera_lvds_core20_191/sim/altera_lvds_core20.sv"                                       -work altera_lvds_core20_191               
   vlog      "$IP_DIR/../altera_lvds_core20_191/sim/altera_lvds_core20_pll.v"                                    -work altera_lvds_core20_191               
-#  vcom      "$IP_DIR/../altera_lvds_core20_191/sim/ip_arria10_e2sg_tse_sgmii_lvds_altera_lvds_core20_191_276h55y.vhd"  -work altera_lvds_core20_191               
-  vcom      "$IP_DIR/../altera_lvds_core20_191/sim/ip_arria10_e2sg_tse_sgmii_lvds_altera_lvds_core20_191_276h55y.sv"  -work altera_lvds_core20_191  
+  vcom      "$IP_DIR/../altera_lvds_core20_191/sim/ip_arria10_e2sg_tse_sgmii_lvds_altera_lvds_core20_191_276h55y.vhd"  -work altera_lvds_core20_191               
+#  vcom      "$IP_DIR/../altera_lvds_core20_191/sim/ip_arria10_e2sg_tse_sgmii_lvds_altera_lvds_core20_191_276h55y.sv"  -work altera_lvds_core20_191  
   vlog -sv  "$IP_DIR/../altera_lvds_core20_191/sim/altera_lvds_core20.sv"                                       -work altera_lvds_core20_191               
   vlog      "$IP_DIR/../altera_lvds_core20_191/sim/altera_lvds_core20_pll.v"                                    -work altera_lvds_core20_191               
-#  vcom      "$IP_DIR/../altera_lvds_core20_191/sim/ip_arria10_e2sg_tse_sgmii_lvds_altera_lvds_core20_191_ag343xq.vhd"  -work altera_lvds_core20_191  
-  vcom      "$IP_DIR/../altera_lvds_core20_191/sim/ip_arria10_e2sg_tse_sgmii_lvds_altera_lvds_core20_191_ag343xq.sv"  -work altera_lvds_core20_191  
+  vcom      "$IP_DIR/../altera_lvds_core20_191/sim/ip_arria10_e2sg_tse_sgmii_lvds_altera_lvds_core20_191_ag343xq.vhd"  -work altera_lvds_core20_191  
+#  vcom      "$IP_DIR/../altera_lvds_core20_191/sim/ip_arria10_e2sg_tse_sgmii_lvds_altera_lvds_core20_191_ag343xq.sv"  -work altera_lvds_core20_191  

libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/hdllib.cfg

 hdl_lib_name = ip_arria10_e2sg_altera_mm_interconnect_191
 hdl_library_clause_name = altera_mm_interconnect_191
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_merlin_master_translator_191 ip_arria10_e2sg_altera_merlin_slave_translator_191
+hdl_lib_uses_sim = 
+#ip_arria10_e2sg_altera_merlin_master_translator_191 ip_arria10_e2sg_altera_merlin_slave_translator_191
 hdl_lib_technology = ip_arria10_e2sg
 
 synth_files =

libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/compile_ip.tcl

@@ -99,7 +99,7 @@ set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
 
 # jesd204b rx
 set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
-  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_jesd204b_rx_altera_xcvr_native_a10_191_pebno5q.sv"      -L altera_common_sv_packages -work altera_xcvr_native_a10_191            
+  vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_jesd204b_rx_200MHz_altera_xcvr_native_a10_191_pebno5q.sv"      -L altera_common_sv_packages -work altera_xcvr_native_a10_191            
   vlog -sv  "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_pebno5q.sv"                              -L altera_common_sv_packages -work altera_xcvr_native_a10_191  
 
 # jesd204b tx

libraries/technology/ip_arria10_e2sg/ddio/sim/tb_ip_arria10_e2sg_ddio_1.vhd

@@ -96,7 +96,7 @@ BEGIN
   u_ddio_in : ENTITY work.ip_arria10_e2sg_ddio_in_1
 	PORT MAP (
 		datain    => in_data,
-		inclock   => clk,
+		ck   => clk,
 		dataout_h => data_h,
 		dataout_l => data_l
 	);

libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/hdllib.cfg

 hdl_lib_name = ip_arria10_e2sg_ddr4_8g_1600
 hdl_library_clause_name = ip_arria10_e2sg_ddr4_8g_1600_altera_emif_1910
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_merlin_master_translator_191 ip_arria10_e2sg_altera_emif_cal_slave_nf_191 ip_arria10_e2sg_altera_avalon_onchip_memory2_1920 ip_arria10_e2sg_altera_mm_interconnect_191 ip_arria10_e2sg_altera_reset_controller_191 ip_arria10_e2sg_altera_emif_arch_nf_191 ip_arria10_e2sg_altera_emif_1910 ip_arria10_e2sg_altera_avalon_mm_bridge_191 ip_arria10_e2sg_altera_merlin_slave_translator_191 ip_arria10_e2sg_altera_avalon_sc_fifo_191 ip_arria10_e2sg_altera_avalon_st_packets_to_bytes_1910 ip_arria10_e2sg_altera_ip_col_if_191 ip_arria10_e2sg_altera_jtag_dc_streaming_191 ip_arria10_e2sg_alt_mem_if_jtag_master_191 ip_arria10_e2sg_altera_avalon_st_bytes_to_packets_1910 ip_arria10_e2sg_altera_avalon_packets_to_master_1910 ip_arria10_e2sg_channel_adapter_191 ip_arria10_e2sg_timing_adapter_191
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_emif_cal_slave_nf_191 ip_arria10_e2sg_altera_avalon_onchip_memory2_1920 ip_arria10_e2sg_altera_mm_interconnect_191 ip_arria10_e2sg_altera_reset_controller_191 ip_arria10_e2sg_altera_emif_arch_nf_191 ip_arria10_e2sg_altera_avalon_mm_bridge_191 ip_arria10_e2sg_altera_merlin_slave_translator_191 ip_arria10_e2sg_altera_avalon_sc_fifo_191 ip_arria10_e2sg_altera_ip_col_if_191 ip_arria10_e2sg_altera_jtag_dc_streaming_191 ip_arria10_e2sg_alt_mem_if_jtag_master_191 ip_arria10_e2sg_altera_avalon_st_bytes_to_packets_1910 ip_arria10_e2sg_altera_avalon_packets_to_master_1910 ip_arria10_e2sg_channel_adapter_191 ip_arria10_e2sg_timing_adapter_191
+#ip_arria10_e2sg_altera_avalon_st_packets_to_bytes_1910 
+#ip_arria10_e2sg_altera_emif_1910 
+#ip_arria10_e2sg_altera_merlin_master_translator_191 
 
 hdl_lib_technology = ip_arria10_e2sg
 

libraries/technology/ip_arria10_e2sg/ddr4_8g_2400/compile_ip.tcl

-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2017
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on generated file mentor/msim_setup.tcl.
-# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
-# - replace QSYS_SIMDIR by IP_DIR
-# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-
-#vlib ./work/         ;# Assume library work already exist                                                                                        
-
-
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
-
-  vcom         "$IP_DIR/ip_arria10_e2sg_ddr4_8g_2400.vhd"

libraries/technology/ip_arria10_e2sg/ddr4_8g_2400/copy_hex_files.tcl

-#------------------------------------------------------------------------------
-#
-# Copyright (C) 2015
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-#
-#------------------------------------------------------------------------------
-
-# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
-
-# Copy ROM/RAM files to simulation directory
-if {[file isdirectory $IP_DIR]} {
-    file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_arch_nf_151_izxxuoi_seq_cal_sim.hex ./
-    file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_arch_nf_151_izxxuoi_seq_cal_synth.hex ./
-    file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_arch_nf_151_izxxuoi_seq_params_sim.hex ./
-    file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_arch_nf_151_izxxuoi_seq_params_synth.hex ./
-}

libraries/technology/ip_arria10_e2sg/ddr4_8g_2400/hdllib.cfg

-hdl_lib_name = ip_arria10_e2sg_ddr4_8g_2400
-hdl_library_clause_name = ip_arria10_e2sg_ddr4_8g_2400_altera_emif_194
-hdl_lib_uses_synth = 
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_merlin_master_translator_194 ip_arria10_e2sg_altera_emif_cal_slave_nf_194 ip_arria10_e2sg_altera_avalon_onchip_memory2_194 ip_arria10_e2sg_altera_mm_interconnect_194 ip_arria10_e2sg_altera_reset_controller_194 ip_arria10_e2sg_altera_emif_arch_nf_194 ip_arria10_e2sg_altera_emif_194 ip_arria10_e2sg_altera_avalon_mm_bridge_194 ip_arria10_e2sg_altera_merlin_slave_translator_194
-hdl_lib_technology = ip_arria10_e2sg
-
-synth_files =
-    
-test_bench_files = 
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/ddr4_8g_2400/compile_ip.tcl
-
-
-[quartus_project_file]
-quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/ip_arria10_e2sg_ddr4_8g_2400.qip
-
-[generate_ip_libs]
-qsys-generate_ip_files = 
-    ip_arria10_e2sg_ddr4_8g_2400.ip
-

libraries/technology/ip_arria10_e2sg/voltage_sense/hdllib.cfg

 hdl_lib_name = ip_arria10_e2sg_voltage_sense 
-hdl_library_clause_name = ip_arria10_e2sg_voltage_sense_altera_voltage_sense_194
+hdl_library_clause_name = ip_arria10_e2sg_voltage_sense_altera_voltage_sense_1910
 hdl_lib_uses_synth = 
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_arria10_e2sg