getting modelsim errors out

...sg/altera_libraries/alt_mem_if_jtag_master_191/hdllib.cfg

..._arria10_e2sg/altera_libraries/altera_emif_191/hdllib.cfg

...g/altera_libraries/altera_eth_tse_mac_1940/compile_ip.tcl

...aries/altera_eth_tse_pcs_pma_nf_phyip_1940/compile_ip.tcl

...10_e2sg/altera_libraries/altera_iopll_1930/compile_ip.tcl

...rria10_e2sg/altera_libraries/altera_iopll_1930/hdllib.cfg

...arria10_e2sg/altera_libraries/altera_lvds_1930/hdllib.cfg

...sg/altera_libraries/altera_lvds_core20_191/compile_ip.tcl

...sg/altera_libraries/altera_mm_interconnect_191/hdllib.cfg

...ltera_libraries/altera_xcvr_native_a10_191/compile_ip.tcl

...gy/ip_arria10_e2sg/ddio/sim/tb_ip_arria10_e2sg_ddio_1.vhd

libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/hdllib.cfg

...es/technology/ip_arria10_e2sg/ddr4_8g_2400/compile_ip.tcl

...echnology/ip_arria10_e2sg/ddr4_8g_2400/copy_hex_files.tcl

libraries/technology/ip_arria10_e2sg/ddr4_8g_2400/hdllib.cfg

...arria10_e2sg/ddr4_8g_2400/ip_arria10_e2sg_ddr4_8g_2400.ip

...aries/technology/ip_arria10_e2sg/voltage_sense/hdllib.cfg