L2SDP-61 : Added function RESET_MEM_MOSI_CTRL() and RESET_MEM_MISO_CTRL(), it...

L2SDP-61 : Added function RESET_MEM_MOSI_CTRL() and RESET_MEM_MISO_CTRL(), it works in sim with mm_pipeline.vhd and tb_tb_mm_bus.vhd, but not tried on HW yet.

libraries/base/common/src/vhdl/common_mem_pkg.vhd

@@ -80,6 +80,10 @@ PACKAGE common_mem_pkg IS
   TYPE t_mem_miso_arr IS ARRAY (INTEGER RANGE <>) OF t_mem_miso;
   TYPE t_mem_mosi_arr IS ARRAY (INTEGER RANGE <>) OF t_mem_mosi;
   
+  -- Reset only the control fields of the MM record
+  FUNCTION RESET_MEM_MOSI_CTRL(mosi : t_mem_mosi) RETURN t_mem_mosi;
+  FUNCTION RESET_MEM_MISO_CTRL(miso : t_mem_miso) RETURN t_mem_miso;
+
   -- Resize functions to fit an integer or an SLV in the corresponding t_mem_miso or t_mem_mosi field width
   FUNCTION TO_MEM_ADDRESS(n : INTEGER) RETURN STD_LOGIC_VECTOR;  -- unsigned, use integer to support 32 bit range
   FUNCTION TO_MEM_DATA(   n : INTEGER) RETURN STD_LOGIC_VECTOR;  -- unsigned, alias of TO_MEM_DATA()
@@ -169,6 +173,23 @@ END common_mem_pkg;
 
 PACKAGE BODY common_mem_pkg IS
 
+  -- Reset only the control fields of the MM record
+  FUNCTION RESET_MEM_MOSI_CTRL(mosi : t_mem_mosi) RETURN t_mem_mosi IS
+    VARIABLE v_mosi : t_mem_mosi := mosi;
+  BEGIN
+    v_mosi.rd := '0';
+    v_mosi.wr := '0';
+    RETURN v_mosi;
+  END RESET_MEM_MOSI_CTRL;
+  
+  FUNCTION RESET_MEM_MISO_CTRL(miso : t_mem_miso) RETURN t_mem_miso IS
+    VARIABLE v_miso : t_mem_miso := miso;
+  BEGIN
+    v_miso.rdval       := '0';
+    v_miso.waitrequest := '0';
+    RETURN v_miso;
+  END RESET_MEM_MISO_CTRL;
+
   -- Resize functions to fit an integer or an SLV in the corresponding t_mem_miso or t_mem_mosi field width
   FUNCTION TO_MEM_ADDRESS(n : INTEGER) RETURN STD_LOGIC_VECTOR IS
   BEGIN

libraries/base/mm/src/vhdl/mm_pipeline.vhd

@@ -127,10 +127,11 @@ BEGIN
   END GENERATE;
 
   gen_pipeline : IF g_pipeline = TRUE GENERATE
+    --p_reg : PROCESS(mm_rst, mosi_reg, mm_clk)   -- todo: check with synthesis that it is not necessary to have mosi_reg here
     p_reg : PROCESS(mm_rst, mm_clk)
     BEGIN
       IF mm_rst = '1' THEN
-        mosi_reg <= c_mem_mosi_rst;
+        mosi_reg <= RESET_MEM_MOSI_CTRL(mosi_reg);  -- todo: check with synthesis that mosi_reg data fields remain wires
       ELSIF rising_edge(mm_clk) THEN
         mosi_reg <= nxt_mosi_reg;
       END IF;