-Fixed typo in constant name.

libraries/dsp/st/src/vhdl/st_histogram_reg.vhd

@@ -64,12 +64,12 @@ END st_histogram_reg;
 
 ARCHITECTURE rtl OF st_histogram_reg IS
 
-  CONSTANT nof_addresses : NATURAL := 3;
+  CONSTANT c_nof_addresses : NATURAL := 3;
 
   CONSTANT c_mm_reg : t_c_mem := (latency  => 1,
-                                  adr_w    => ceil_log2(nof_addresses),
+                                  adr_w    => ceil_log2(c_nof_addresses),
                                   dat_w    => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
-                                  nof_dat  => nof_addresses,
+                                  nof_dat  => c_nof_addresses,
                                   init_sl  => '0');                                              
 
   SIGNAL mm_ram_clear    : STD_LOGIC;