Skip to content
Snippets Groups Projects
Commit adece307 authored by Reinier van der Walle's avatar Reinier van der Walle
Browse files

added clock uncertainty to increase performance in JESD IP

parent 4563567d
No related branches found
No related tags found
1 merge request!318added clock uncertainty to increase performance in JESD IP
Pipeline #46134 failed
Stage: simulation
Stage: synthesis
Stage: hardware