From adece307a1befe79dfe397b88dbb8b122a0e47ec Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Thu, 23 Mar 2023 14:33:02 +0100
Subject: [PATCH] added clock uncertainty to increase performance in JESD IP
---
.../quartus/lofar2_unb2b_sdp_station.sdc | 22 +++++++++++++++----
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station.sdc b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station.sdc
index ce015b6d62..24c9eaf954 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station.sdc
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station.sdc
@@ -97,8 +97,22 @@ set_clock_groups -asynchronous -group [get_clocks {*xcvr_native_a10_0|g_xcvr_nat
#-group [get_clocks {inst2|xcvr_4ch_native_phy_inst|xcvr_native_a10_0|g_xcvr_native_insts[?]|rx_pma_clk}] \
#-group [get_clocks {inst2|xcvr_pll_inst|xcvr_fpll_a10_0|tx_bonding_clocks[0]}]
+# JESD
+
+# Increase clock uncertainty to force link_clk to have Fmax > 234MHz
+set_clock_uncertainty -rise_from [get_clocks {*|iopll_0|link_clk}] -rise_to [get_clocks {*|iopll_0|link_clk}] 5.727
+set_clock_uncertainty -rise_from [get_clocks {*|iopll_0|link_clk}] -fall_to [get_clocks {*|iopll_0|link_clk}] 5.727
+set_clock_uncertainty -fall_from [get_clocks {*|iopll_0|link_clk}] -rise_to [get_clocks {*|iopll_0|link_clk}] 5.727
+set_clock_uncertainty -fall_from [get_clocks {*|iopll_0|link_clk}] -fall_to [get_clocks {*|iopll_0|link_clk}] 5.727
+
+# Increase clock uncertainty to force frame_clk to have Fmax > 222MHz
+set_clock_uncertainty -rise_from [get_clocks {*|iopll_0|frame_clk}] -rise_to [get_clocks {*|iopll_0|frame_clk}] 0.496
+set_clock_uncertainty -rise_from [get_clocks {*|iopll_0|frame_clk}] -fall_to [get_clocks {*|iopll_0|frame_clk}] 0.496
+set_clock_uncertainty -fall_from [get_clocks {*|iopll_0|frame_clk}] -rise_to [get_clocks {*|iopll_0|frame_clk}] 0.496
+set_clock_uncertainty -fall_from [get_clocks {*|iopll_0|frame_clk}] -fall_to [get_clocks {*|iopll_0|frame_clk}] 0.496
+
# false paths added for the jesd interface as these clocks are independent.
-set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*iopll_0|link_clk}]
-set_false_path -from [get_clocks {*iopll_0|link_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
-set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*iopll_0|frame_clk}]
-set_false_path -from [get_clocks {*iopll_0|frame_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
+#set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*iopll_0|link_clk}]
+#set_false_path -from [get_clocks {*iopll_0|link_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
+#set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*iopll_0|frame_clk}]
+#set_false_path -from [get_clocks {*iopll_0|frame_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
--
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