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Commit ad6e8e98 authored by Reinier van der Walle's avatar Reinier van der Walle
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2 channels are not supported by arria10 technology, now using 24 channels for arria10

parent 267040f7
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...@@ -65,7 +65,13 @@ BEGIN ...@@ -65,7 +65,13 @@ BEGIN
u_tr_10GbE_tx_only : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, FALSE, 5 ns, 0, 1, "TX_ONLY", c_644, c_156, c_data_type, TRUE) PORT MAP (tb_end_vec(2)); u_tr_10GbE_tx_only : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, FALSE, 5 ns, 0, 1, "TX_ONLY", c_644, c_156, c_data_type, TRUE) PORT MAP (tb_end_vec(2));
u_tr_10GbE_rx_only : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, FALSE, 5 ns, 0, 1, "RX_ONLY", c_644, c_156, c_data_type, TRUE) PORT MAP (tb_end_vec(3)); u_tr_10GbE_rx_only : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, FALSE, 5 ns, 0, 1, "RX_ONLY", c_644, c_156, c_data_type, TRUE) PORT MAP (tb_end_vec(3));
u_tr_10GbE_dp_clk_6_5ns : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, FALSE, 6.5 ns, 0, 1, "TX_RX", c_644, c_156, c_data_type, TRUE) PORT MAP (tb_end_vec(4)); u_tr_10GbE_dp_clk_6_5ns : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, FALSE, 6.5 ns, 0, 1, "TX_RX", c_644, c_156, c_data_type, TRUE) PORT MAP (tb_end_vec(4));
gen_2_channels : IF c_tech_select_default = c_tech_stratixiv GENERATE
u_tr_10GbE_nof_channels_is_2 : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, FALSE, 5 ns, 0, 2, "TX_RX", c_644, c_156, c_data_type, TRUE) PORT MAP (tb_end_vec(5)); u_tr_10GbE_nof_channels_is_2 : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, FALSE, 5 ns, 0, 2, "TX_RX", c_644, c_156, c_data_type, TRUE) PORT MAP (tb_end_vec(5));
END GENERATE;
-- For arria10, nof_channels need to be 1, 4, 12, 24, 48.
gen_24_channels : IF c_tech_select_default /= c_tech_stratixiv GENERATE
u_tr_10GbE_nof_channels_is_24 : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, FALSE, 5 ns, 0, 24, "TX_RX", c_644, c_156, c_data_type, TRUE) PORT MAP (tb_end_vec(5));
END GENERATE;
u_tr_10GbE_sim_level_is_1 : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, FALSE, 5 ns, 1, 1, "TX_RX", c_644, c_156, c_data_type, TRUE) PORT MAP (tb_end_vec(6)); u_tr_10GbE_sim_level_is_1 : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, FALSE, 5 ns, 1, 1, "TX_RX", c_644, c_156, c_data_type, TRUE) PORT MAP (tb_end_vec(6));
tb_end <= '1' WHEN tb_end_vec=c_tb_end_vec ELSE '0'; tb_end <= '1' WHEN tb_end_vec=c_tb_end_vec ELSE '0';
......
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