diff --git a/libraries/io/tr_10GbE/tb/vhdl/tb_tb_tr_10GbE.vhd b/libraries/io/tr_10GbE/tb/vhdl/tb_tb_tr_10GbE.vhd
index 1c4b56a1601f8bda4a6e91393fee7cd21ac91418..1fa2de711644f80c1bc3931fa4ef23f613152066 100644
--- a/libraries/io/tr_10GbE/tb/vhdl/tb_tb_tr_10GbE.vhd
+++ b/libraries/io/tr_10GbE/tb/vhdl/tb_tb_tr_10GbE.vhd
@@ -65,7 +65,13 @@ BEGIN
   u_tr_10GbE_tx_only           : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, FALSE, 5   ns, 0, 1, "TX_ONLY", c_644, c_156, c_data_type, TRUE) PORT MAP (tb_end_vec(2));
   u_tr_10GbE_rx_only           : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, FALSE, 5   ns, 0, 1, "RX_ONLY", c_644, c_156, c_data_type, TRUE) PORT MAP (tb_end_vec(3));
   u_tr_10GbE_dp_clk_6_5ns      : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, FALSE, 6.5 ns, 0, 1, "TX_RX",   c_644, c_156, c_data_type, TRUE) PORT MAP (tb_end_vec(4));
-  u_tr_10GbE_nof_channels_is_2 : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, FALSE, 5   ns, 0, 2, "TX_RX",   c_644, c_156, c_data_type, TRUE) PORT MAP (tb_end_vec(5));
+  gen_2_channels : IF c_tech_select_default = c_tech_stratixiv GENERATE
+    u_tr_10GbE_nof_channels_is_2 : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, FALSE, 5   ns, 0, 2, "TX_RX",   c_644, c_156, c_data_type, TRUE) PORT MAP (tb_end_vec(5));
+  END GENERATE;
+  -- For arria10, nof_channels need to be 1, 4, 12, 24, 48.
+  gen_24_channels : IF c_tech_select_default /= c_tech_stratixiv GENERATE
+  u_tr_10GbE_nof_channels_is_24 : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, FALSE, 5   ns, 0, 24, "TX_RX",   c_644, c_156, c_data_type, TRUE) PORT MAP (tb_end_vec(5));
+  END GENERATE;
   u_tr_10GbE_sim_level_is_1    : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, FALSE, 5   ns, 1, 1, "TX_RX",   c_644, c_156, c_data_type, TRUE) PORT MAP (tb_end_vec(6));
   
   tb_end <= '1' WHEN tb_end_vec=c_tb_end_vec ELSE '0';